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UefiCpuPkg/PiSmmCpuDxeSmm: Add SmmMemoryAttribute protocol
[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / PiSmmCpuDxeSmm.h
CommitLineData
529a5a86
MK		 1/** @file\r
2Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.\r
3\r
7ed6f781 4Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>\r
241f9149
LD		 5Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
6\r
529a5a86
MK		 7This program and the accompanying materials\r
8are licensed and made available under the terms and conditions of the BSD License\r
9which accompanies this distribution. The full text of the license may be found at\r
10http://opensource.org/licenses/bsd-license.php\r
11\r
12THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14\r
15**/\r
16\r
17#ifndef _CPU_PISMMCPUDXESMM_H_\r
18#define _CPU_PISMMCPUDXESMM_H_\r
19\r
20#include <PiSmm.h>\r
21\r
22#include <Protocol/MpService.h>\r
23#include <Protocol/SmmConfiguration.h>\r
24#include <Protocol/SmmCpu.h>\r
25#include <Protocol/SmmAccess2.h>\r
529a5a86
MK		 26#include <Protocol/SmmReadyToLock.h>\r
27#include <Protocol/SmmCpuService.h>\r
af4f4b34 28#include <Protocol/SmmMemoryAttribute.h>
529a5a86
MK		 29\r
30#include <Guid/AcpiS3Context.h>\r
717fb604 31#include <Guid/PiSmmMemoryAttributesTable.h>\r
529a5a86
MK		 32\r
33#include <Library/BaseLib.h>\r
34#include <Library/IoLib.h>\r
35#include <Library/TimerLib.h>\r
529a5a86
MK		 36#include <Library/SynchronizationLib.h>\r
37#include <Library/DebugLib.h>\r
38#include <Library/BaseMemoryLib.h>\r
39#include <Library/PcdLib.h>\r
40#include <Library/CacheMaintenanceLib.h>\r
41#include <Library/MtrrLib.h>\r
42#include <Library/SmmCpuPlatformHookLib.h>\r
43#include <Library/SmmServicesTableLib.h>\r
44#include <Library/MemoryAllocationLib.h>\r
45#include <Library/UefiBootServicesTableLib.h>\r
46#include <Library/UefiRuntimeServicesTableLib.h>\r
47#include <Library/DebugAgentLib.h>\r
48#include <Library/HobLib.h>\r
49#include <Library/LocalApicLib.h>\r
50#include <Library/UefiCpuLib.h>\r
51#include <Library/CpuExceptionHandlerLib.h>\r
52#include <Library/ReportStatusCodeLib.h>\r
53#include <Library/SmmCpuFeaturesLib.h>\r
54#include <Library/PeCoffGetEntryPointLib.h>\r
55\r
56#include <AcpiCpuData.h>\r
57#include <CpuHotPlugData.h>\r
58\r
59#include <Register/Cpuid.h>\r
f85d3ce2 60#include <Register/Msr.h>\r
529a5a86
MK		 61\r
62#include "CpuService.h"\r
63#include "SmmProfile.h"\r
64\r
65//\r
66// MSRs required for configuration of SMM Code Access Check\r
67//\r
68#define EFI_MSR_SMM_MCA_CAP 0x17D\r
69#define SMM_CODE_ACCESS_CHK_BIT BIT58\r
70\r
71#define SMM_FEATURE_CONTROL_LOCK_BIT BIT0\r
72#define SMM_CODE_CHK_EN_BIT BIT2\r
73\r
74///\r
75/// Page Table Entry\r
76///\r
77#define IA32_PG_P BIT0\r
78#define IA32_PG_RW BIT1\r
881520ea 79#define IA32_PG_U BIT2\r
529a5a86
MK		 80#define IA32_PG_WT BIT3\r
81#define IA32_PG_CD BIT4\r
82#define IA32_PG_A BIT5\r
881520ea 83#define IA32_PG_D BIT6\r
529a5a86
MK		 84#define IA32_PG_PS BIT7\r
85#define IA32_PG_PAT_2M BIT12\r
86#define IA32_PG_PAT_4K IA32_PG_PS\r
87#define IA32_PG_PMNT BIT62\r
88#define IA32_PG_NX BIT63\r
89\r
717fb604 90#define PAGE_ATTRIBUTE_BITS (IA32_PG_D | IA32_PG_A | IA32_PG_U | IA32_PG_RW | IA32_PG_P)\r
881520ea
JY		 91//\r
92// Bits 1, 2, 5, 6 are reserved in the IA32 PAE PDPTE\r
93// X64 PAE PDPTE does not have such restriction\r
94//\r
95#define IA32_PAE_PDPTE_ATTRIBUTE_BITS (IA32_PG_P)\r
96\r
717fb604
JY		 97#define PAGE_PROGATE_BITS (IA32_PG_NX | PAGE_ATTRIBUTE_BITS)\r
98\r
99#define PAGING_4K_MASK 0xFFF\r
100#define PAGING_2M_MASK 0x1FFFFF\r
101#define PAGING_1G_MASK 0x3FFFFFFF\r
102\r
103#define PAGING_PAE_INDEX_MASK 0x1FF\r
104\r
105#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull\r
106#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull\r
107#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull\r
108\r
7ed6f781
JF		 109#define SMRR_MAX_ADDRESS BASE_4GB\r
110\r
717fb604
JY		 111typedef enum {\r
112 PageNone,\r
113 Page4K,\r
114 Page2M,\r
115 Page1G,\r
116} PAGE_ATTRIBUTE;\r
117\r
118typedef struct {\r
119 PAGE_ATTRIBUTE Attribute;\r
120 UINT64 Length;\r
121 UINT64 AddressMask;\r
122} PAGE_ATTRIBUTE_TABLE;\r
123\r
529a5a86
MK		 124//\r
125// Size of Task-State Segment defined in IA32 Manual\r
126//\r
127#define TSS_SIZE 104\r
128#define TSS_X64_IST1_OFFSET 36\r
129#define TSS_IA32_CR3_OFFSET 28\r
130#define TSS_IA32_ESP_OFFSET 56\r
131\r
717fb604
JY		 132#define CR0_WP BIT16\r
133\r
529a5a86
MK		 134//\r
135// Code select value\r
136//\r
137#define PROTECT_MODE_CODE_SEGMENT 0x08\r
138#define LONG_MODE_CODE_SEGMENT 0x38\r
139\r
140//\r
141// The size 0x20 must be bigger than\r
142// the size of template code of SmmInit. Currently,\r
143// the size of SmmInit requires the 0x16 Bytes buffer\r
144// at least.\r
145//\r
146#define BACK_BUF_SIZE 0x20\r
147\r
148#define EXCEPTION_VECTOR_NUMBER 0x20\r
149\r
150#define INVALID_APIC_ID 0xFFFFFFFFFFFFFFFFULL\r
151\r
152typedef UINT32 SMM_CPU_ARRIVAL_EXCEPTIONS;\r
153#define ARRIVAL_EXCEPTION_BLOCKED 0x1\r
154#define ARRIVAL_EXCEPTION_DELAYED 0x2\r
155#define ARRIVAL_EXCEPTION_SMI_DISABLED 0x4\r
156\r
157//\r
158// Private structure for the SMM CPU module that is stored in DXE Runtime memory\r
159// Contains the SMM Configuration Protocols that is produced.\r
160// Contains a mix of DXE and SMM contents. All the fields must be used properly.\r
161//\r
162#define SMM_CPU_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('s', 'c', 'p', 'u')\r
163\r
164typedef struct {\r
165 UINTN Signature;\r
166\r
167 EFI_HANDLE SmmCpuHandle;\r
168\r
169 EFI_PROCESSOR_INFORMATION *ProcessorInfo;\r
170 SMM_CPU_OPERATION *Operation;\r
171 UINTN *CpuSaveStateSize;\r
172 VOID **CpuSaveState;\r
173\r
174 EFI_SMM_RESERVED_SMRAM_REGION SmmReservedSmramRegion[1];\r
175 EFI_SMM_ENTRY_CONTEXT SmmCoreEntryContext;\r
176 EFI_SMM_ENTRY_POINT SmmCoreEntry;\r
177\r
178 EFI_SMM_CONFIGURATION_PROTOCOL SmmConfiguration;\r
179} SMM_CPU_PRIVATE_DATA;\r
180\r
181extern SMM_CPU_PRIVATE_DATA *gSmmCpuPrivate;\r
182extern CPU_HOT_PLUG_DATA mCpuHotPlugData;\r
183extern UINTN mMaxNumberOfCpus;\r
184extern UINTN mNumberOfCpus;\r
529a5a86
MK		 185extern EFI_SMM_CPU_PROTOCOL mSmmCpu;\r
186\r
187///\r
188/// The mode of the CPU at the time an SMI occurs\r
189///\r
190extern UINT8 mSmmSaveStateRegisterLma;\r
191\r
529a5a86
MK		 192//\r
193// SMM CPU Protocol function prototypes.\r
194//\r
195\r
196/**\r
197 Read information from the CPU save state.\r
198\r
199 @param This EFI_SMM_CPU_PROTOCOL instance\r
200 @param Width The number of bytes to read from the CPU save state.\r
201 @param Register Specifies the CPU register to read form the save state.\r
202 @param CpuIndex Specifies the zero-based index of the CPU save state\r
203 @param Buffer Upon return, this holds the CPU register value read from the save state.\r
204\r
205 @retval EFI_SUCCESS The register was read from Save State\r
206 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor\r
207 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.\r
208\r
209**/\r
210EFI_STATUS\r
211EFIAPI\r
212SmmReadSaveState (\r
213 IN CONST EFI_SMM_CPU_PROTOCOL *This,\r
214 IN UINTN Width,\r
215 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
216 IN UINTN CpuIndex,\r
217 OUT VOID *Buffer\r
218 );\r
219\r
220/**\r
221 Write data to the CPU save state.\r
222\r
223 @param This EFI_SMM_CPU_PROTOCOL instance\r
224 @param Width The number of bytes to read from the CPU save state.\r
225 @param Register Specifies the CPU register to write to the save state.\r
226 @param CpuIndex Specifies the zero-based index of the CPU save state\r
227 @param Buffer Upon entry, this holds the new CPU register value.\r
228\r
229 @retval EFI_SUCCESS The register was written from Save State\r
230 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor\r
231 @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct\r
232\r
233**/\r
234EFI_STATUS\r
235EFIAPI\r
236SmmWriteSaveState (\r
237 IN CONST EFI_SMM_CPU_PROTOCOL *This,\r
238 IN UINTN Width,\r
239 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
240 IN UINTN CpuIndex,\r
241 IN CONST VOID *Buffer\r
242 );\r
243\r
244/**\r
245Read a CPU Save State register on the target processor.\r
246\r
247This function abstracts the differences that whether the CPU Save State register is in the\r
248IA32 CPU Save State Map or X64 CPU Save State Map.\r
249\r
250This function supports reading a CPU Save State register in SMBase relocation handler.\r
251\r
252@param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r
253@param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r
254@param[in] Width The number of bytes to read from the CPU save state.\r
255@param[out] Buffer Upon return, this holds the CPU register value read from the save state.\r
256\r
257@retval EFI_SUCCESS The register was read from Save State.\r
258@retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r
259@retval EFI_INVALID_PARAMTER This or Buffer is NULL.\r
260\r
261**/\r
262EFI_STATUS\r
263EFIAPI\r
264ReadSaveStateRegister (\r
265 IN UINTN CpuIndex,\r
266 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
267 IN UINTN Width,\r
268 OUT VOID *Buffer\r
269 );\r
270\r
271/**\r
272Write value to a CPU Save State register on the target processor.\r
273\r
274This function abstracts the differences that whether the CPU Save State register is in the\r
275IA32 CPU Save State Map or X64 CPU Save State Map.\r
276\r
277This function supports writing a CPU Save State register in SMBase relocation handler.\r
278\r
279@param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r
280@param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r
281@param[in] Width The number of bytes to read from the CPU save state.\r
282@param[in] Buffer Upon entry, this holds the new CPU register value.\r
283\r
284@retval EFI_SUCCESS The register was written to Save State.\r
285@retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r
286@retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct.\r
287\r
288**/\r
289EFI_STATUS\r
290EFIAPI\r
291WriteSaveStateRegister (\r
292 IN UINTN CpuIndex,\r
293 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
294 IN UINTN Width,\r
295 IN CONST VOID *Buffer\r
296 );\r
297\r
298//\r
299//\r
300//\r
301typedef struct {\r
302 UINT32 Offset;\r
303 UINT16 Segment;\r
304 UINT16 Reserved;\r
305} IA32_FAR_ADDRESS;\r
306\r
307extern IA32_FAR_ADDRESS gSmmJmpAddr;\r
308\r
309extern CONST UINT8 gcSmmInitTemplate[];\r
310extern CONST UINT16 gcSmmInitSize;\r
311extern UINT32 gSmmCr0;\r
312extern UINT32 gSmmCr3;\r
313extern UINT32 gSmmCr4;\r
314extern UINTN gSmmInitStack;\r
315\r
316/**\r
317 Semaphore operation for all processor relocate SMMBase.\r
318**/\r
319VOID\r
320EFIAPI\r
321SmmRelocationSemaphoreComplete (\r
322 VOID\r
323 );\r
324\r
325///\r
326/// The type of SMM CPU Information\r
327///\r
328typedef struct {\r
ed3d5ecb 329 SPIN_LOCK *Busy;\r
529a5a86
MK		 330 volatile EFI_AP_PROCEDURE Procedure;\r
331 volatile VOID *Parameter;\r
ed3d5ecb
JF		 332 volatile UINT32 *Run;\r
333 volatile BOOLEAN *Present;\r
529a5a86
MK		 334} SMM_CPU_DATA_BLOCK;\r
335\r
336typedef enum {\r
337 SmmCpuSyncModeTradition,\r
338 SmmCpuSyncModeRelaxedAp,\r
339 SmmCpuSyncModeMax\r
340} SMM_CPU_SYNC_MODE;\r
341\r
342typedef struct {\r
343 //\r
344 // Pointer to an array. The array should be located immediately after this structure\r
345 // so that UC cache-ability can be set together.\r
346 //\r
347 SMM_CPU_DATA_BLOCK *CpuData;\r
fe3a75bc 348 volatile UINT32 *Counter;\r
529a5a86 349 volatile UINT32 BspIndex;\r
fe3a75bc
JF		 350 volatile BOOLEAN *InsideSmm;\r
351 volatile BOOLEAN *AllCpusInSync;\r
529a5a86
MK		 352 volatile SMM_CPU_SYNC_MODE EffectiveSyncMode;\r
353 volatile BOOLEAN SwitchBsp;\r
354 volatile BOOLEAN *CandidateBsp;\r
355} SMM_DISPATCHER_MP_SYNC_DATA;\r
356\r
695e62d1
JF		 357#define MSR_SPIN_LOCK_INIT_NUM 15\r
358\r
529a5a86 359typedef struct {\r
dc99315b 360 SPIN_LOCK *SpinLock;\r
529a5a86
MK		 361 UINT32 MsrIndex;\r
362} MP_MSR_LOCK;\r
363\r
364#define SMM_PSD_OFFSET 0xfb00\r
365\r
1d648531
JF		 366///\r
367/// All global semaphores' pointer\r
368///\r
369typedef struct {\r
370 volatile UINT32 *Counter;\r
371 volatile BOOLEAN *InsideSmm;\r
372 volatile BOOLEAN *AllCpusInSync;\r
373 SPIN_LOCK *PFLock;\r
374 SPIN_LOCK *CodeAccessCheckLock;\r
6c4c15fa 375 SPIN_LOCK *MemoryMappedLock;\r
1d648531
JF		 376} SMM_CPU_SEMAPHORE_GLOBAL;\r
377\r
4e920581
JF		 378///\r
379/// All semaphores for each processor\r
380///\r
381typedef struct {\r
382 SPIN_LOCK *Busy;\r
383 volatile UINT32 *Run;\r
384 volatile BOOLEAN *Present;\r
385} SMM_CPU_SEMAPHORE_CPU;\r
386\r
695e62d1
JF		 387///\r
388/// All MSRs semaphores' pointer and counter\r
389///\r
390typedef struct {\r
391 SPIN_LOCK *Msr;\r
392 UINTN AvailableCounter;\r
393} SMM_CPU_SEMAPHORE_MSR;\r
4e920581 394\r
1d648531
JF		 395///\r
396/// All semaphores' information\r
397///\r
398typedef struct {\r
399 SMM_CPU_SEMAPHORE_GLOBAL SemaphoreGlobal;\r
4e920581 400 SMM_CPU_SEMAPHORE_CPU SemaphoreCpu;\r
695e62d1 401 SMM_CPU_SEMAPHORE_MSR SemaphoreMsr;\r
1d648531
JF		 402} SMM_CPU_SEMAPHORES;\r
403\r
529a5a86 404extern IA32_DESCRIPTOR gcSmiGdtr;\r
717fb604
JY		 405extern EFI_PHYSICAL_ADDRESS mGdtBuffer;\r
406extern UINTN mGdtBufferSize;\r
529a5a86
MK		 407extern IA32_DESCRIPTOR gcSmiIdtr;\r
408extern VOID *gcSmiIdtrPtr;\r
529a5a86 409extern UINT64 gPhyMask;\r
529a5a86 410extern SMM_DISPATCHER_MP_SYNC_DATA *mSmmMpSyncData;\r
529a5a86
MK		 411extern UINTN mSmmStackArrayBase;\r
412extern UINTN mSmmStackArrayEnd;\r
413extern UINTN mSmmStackSize;\r
414extern EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService;\r
415extern IA32_DESCRIPTOR gcSmiInitGdtr;\r
dc99315b
JF		 416extern SMM_CPU_SEMAPHORES mSmmCpuSemaphores;\r
417extern UINTN mSemaphoreSize;\r
fe3a75bc
JF		 418extern SPIN_LOCK *mPFLock;\r
419extern SPIN_LOCK *mConfigSmmCodeAccessCheckLock;\r
6c4c15fa 420extern SPIN_LOCK *mMemoryMappedLock;\r
7ed6f781
JF		 421extern EFI_SMRAM_DESCRIPTOR *mSmmCpuSmramRanges;\r
422extern UINTN mSmmCpuSmramRangeCount;\r
714c2603 423extern UINT8 mPhysicalAddressBits;\r
529a5a86 424\r
241f9149
LD		 425//\r
426// Copy of the PcdPteMemoryEncryptionAddressOrMask\r
427//\r
428extern UINT64 mAddressEncMask;\r
429\r
529a5a86
MK		 430/**\r
431 Create 4G PageTable in SMRAM.\r
432\r
717fb604 433 @param[in] Is32BitPageTable Whether the page table is 32-bit PAE\r
529a5a86
MK		 434 @return PageTable Address\r
435\r
436**/\r
437UINT32\r
438Gen4GPageTable (\r
881520ea 439 IN BOOLEAN Is32BitPageTable\r
529a5a86
MK		 440 );\r
441\r
442\r
443/**\r
444 Initialize global data for MP synchronization.\r
445\r
446 @param Stacks Base address of SMI stack buffer for all processors.\r
447 @param StackSize Stack size for each processor in SMM.\r
448\r
449**/\r
450UINT32\r
451InitializeMpServiceData (\r
452 IN VOID *Stacks,\r
453 IN UINTN StackSize\r
454 );\r
455\r
456/**\r
457 Initialize Timer for SMM AP Sync.\r
458\r
459**/\r
460VOID\r
461InitializeSmmTimer (\r
462 VOID\r
463 );\r
464\r
465/**\r
466 Start Timer for SMM AP Sync.\r
467\r
468**/\r
469UINT64\r
470EFIAPI\r
471StartSyncTimer (\r
472 VOID\r
473 );\r
474\r
475/**\r
476 Check if the SMM AP Sync timer is timeout.\r
477\r
478 @param Timer The start timer from the begin.\r
479\r
480**/\r
481BOOLEAN\r
482EFIAPI\r
483IsSyncTimerTimeout (\r
484 IN UINT64 Timer\r
485 );\r
486\r
487/**\r
488 Initialize IDT for SMM Stack Guard.\r
489\r
490**/\r
491VOID\r
492EFIAPI\r
493InitializeIDTSmmStackGuard (\r
494 VOID\r
495 );\r
496\r
fe5f1949
JY		 497/**\r
498 Initialize Gdt for all processors.\r
717fb604 499\r
fe5f1949
JY		 500 @param[in] Cr3 CR3 value.\r
501 @param[out] GdtStepSize The step size for GDT table.\r
502\r
503 @return GdtBase for processor 0.\r
504 GdtBase for processor X is: GdtBase + (GdtStepSize * X)\r
505**/\r
506VOID *\r
507InitGdt (\r
508 IN UINTN Cr3,\r
509 OUT UINTN *GdtStepSize\r
510 );\r
511\r
e4435f71
JY		 512/**\r
513 This function sets GDT/IDT buffer to be RO and XP.\r
514**/\r
515VOID\r
516PatchGdtIdtMap (\r
517 VOID\r
518 );\r
519\r
529a5a86
MK		 520/**\r
521\r
522 Register the SMM Foundation entry point.\r
523\r
524 @param This Pointer to EFI_SMM_CONFIGURATION_PROTOCOL instance\r
525 @param SmmEntryPoint SMM Foundation EntryPoint\r
526\r
527 @retval EFI_SUCCESS Successfully to register SMM foundation entry point\r
528\r
529**/\r
530EFI_STATUS\r
531EFIAPI\r
532RegisterSmmEntry (\r
533 IN CONST EFI_SMM_CONFIGURATION_PROTOCOL *This,\r
534 IN EFI_SMM_ENTRY_POINT SmmEntryPoint\r
535 );\r
536\r
537/**\r
538 Create PageTable for SMM use.\r
539\r
540 @return PageTable Address\r
541\r
542**/\r
543UINT32\r
544SmmInitPageTable (\r
545 VOID\r
546 );\r
547\r
548/**\r
549 Schedule a procedure to run on the specified CPU.\r
550\r
551 @param Procedure The address of the procedure to run\r
552 @param CpuIndex Target CPU number\r
553 @param ProcArguments The parameter to pass to the procedure\r
554\r
555 @retval EFI_INVALID_PARAMETER CpuNumber not valid\r
556 @retval EFI_INVALID_PARAMETER CpuNumber specifying BSP\r
557 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM\r
558 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy\r
559 @retval EFI_SUCCESS - The procedure has been successfully scheduled\r
560\r
561**/\r
562EFI_STATUS\r
563EFIAPI\r
564SmmStartupThisAp (\r
565 IN EFI_AP_PROCEDURE Procedure,\r
566 IN UINTN CpuIndex,\r
567 IN OUT VOID *ProcArguments OPTIONAL\r
568 );\r
569\r
570/**\r
571 Schedule a procedure to run on the specified CPU in a blocking fashion.\r
572\r
573 @param Procedure The address of the procedure to run\r
574 @param CpuIndex Target CPU Index\r
575 @param ProcArguments The parameter to pass to the procedure\r
576\r
577 @retval EFI_INVALID_PARAMETER CpuNumber not valid\r
578 @retval EFI_INVALID_PARAMETER CpuNumber specifying BSP\r
579 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM\r
580 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy\r
581 @retval EFI_SUCCESS The procedure has been successfully scheduled\r
582\r
583**/\r
584EFI_STATUS\r
585EFIAPI\r
586SmmBlockingStartupThisAp (\r
587 IN EFI_AP_PROCEDURE Procedure,\r
588 IN UINTN CpuIndex,\r
589 IN OUT VOID *ProcArguments OPTIONAL\r
590 );\r
591\r
e4435f71
JY		 592/**\r
593 This function sets the attributes for the memory region specified by BaseAddress and\r
594 Length from their current attributes to the attributes specified by Attributes.\r
595\r
596 @param[in] BaseAddress The physical address that is the start address of a memory region.\r
597 @param[in] Length The size in bytes of the memory region.\r
598 @param[in] Attributes The bit mask of attributes to set for the memory region.\r
599\r
600 @retval EFI_SUCCESS The attributes were set for the memory region.\r
601 @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r
602 BaseAddress and Length cannot be modified.\r
603 @retval EFI_INVALID_PARAMETER Length is zero.\r
604 Attributes specified an illegal combination of attributes that\r
605 cannot be set together.\r
606 @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r
607 the memory resource range.\r
608 @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r
609 resource range specified by BaseAddress and Length.\r
610 The bit mask of attributes is not support for the memory resource\r
611 range specified by BaseAddress and Length.\r
612\r
613**/\r
614EFI_STATUS\r
615EFIAPI\r
616SmmSetMemoryAttributes (\r
617 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
618 IN UINT64 Length,\r
619 IN UINT64 Attributes\r
620 );\r
621\r
622/**\r
623 This function clears the attributes for the memory region specified by BaseAddress and\r
624 Length from their current attributes to the attributes specified by Attributes.\r
625\r
626 @param[in] BaseAddress The physical address that is the start address of a memory region.\r
627 @param[in] Length The size in bytes of the memory region.\r
628 @param[in] Attributes The bit mask of attributes to clear for the memory region.\r
629\r
630 @retval EFI_SUCCESS The attributes were cleared for the memory region.\r
631 @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r
632 BaseAddress and Length cannot be modified.\r
633 @retval EFI_INVALID_PARAMETER Length is zero.\r
634 Attributes specified an illegal combination of attributes that\r
635 cannot be set together.\r
636 @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r
637 the memory resource range.\r
638 @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r
639 resource range specified by BaseAddress and Length.\r
640 The bit mask of attributes is not support for the memory resource\r
641 range specified by BaseAddress and Length.\r
642\r
643**/\r
644EFI_STATUS\r
645EFIAPI\r
646SmmClearMemoryAttributes (\r
647 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
648 IN UINT64 Length,\r
649 IN UINT64 Attributes\r
650 );\r
651\r
529a5a86
MK		 652/**\r
653 Initialize MP synchronization data.\r
654\r
655**/\r
656VOID\r
657EFIAPI\r
658InitializeMpSyncData (\r
659 VOID\r
660 );\r
661\r
662/**\r
663\r
664 Find out SMRAM information including SMRR base and SMRR size.\r
665\r
666 @param SmrrBase SMRR base\r
667 @param SmrrSize SMRR size\r
668\r
669**/\r
670VOID\r
671FindSmramInfo (\r
672 OUT UINT32 *SmrrBase,\r
673 OUT UINT32 *SmrrSize\r
674 );\r
675\r
676/**\r
0bdc9e75 677 Relocate SmmBases for each processor.\r
529a5a86 678\r
0bdc9e75 679 Execute on first boot and all S3 resumes\r
529a5a86
MK		 680\r
681**/\r
682VOID\r
0bdc9e75
SZ		 683EFIAPI\r
684SmmRelocateBases (\r
529a5a86
MK		 685 VOID\r
686 );\r
687\r
688/**\r
689 Page Fault handler for SMM use.\r
690\r
691 @param InterruptType Defines the type of interrupt or exception that\r
692 occurred on the processor.This parameter is processor architecture specific.\r
693 @param SystemContext A pointer to the processor context when\r
694 the interrupt occurred on the processor.\r
695**/\r
696VOID\r
697EFIAPI\r
698SmiPFHandler (\r
b8caae19
JF		 699 IN EFI_EXCEPTION_TYPE InterruptType,\r
700 IN EFI_SYSTEM_CONTEXT SystemContext\r
529a5a86
MK		 701 );\r
702\r
703/**\r
704 Perform the remaining tasks.\r
705\r
706**/\r
707VOID\r
708PerformRemainingTasks (\r
709 VOID\r
710 );\r
711\r
9f419739
JY		 712/**\r
713 Perform the pre tasks.\r
714\r
715**/\r
716VOID\r
717PerformPreTasks (\r
718 VOID\r
719 );\r
720\r
529a5a86
MK		 721/**\r
722 Initialize MSR spin lock by MSR index.\r
723\r
724 @param MsrIndex MSR index value.\r
725\r
726**/\r
727VOID\r
728InitMsrSpinLockByIndex (\r
729 IN UINT32 MsrIndex\r
730 );\r
731\r
732/**\r
733 Hook return address of SMM Save State so that semaphore code\r
734 can be executed immediately after AP exits SMM to indicate to\r
735 the BSP that an AP has exited SMM after SMBASE relocation.\r
736\r
737 @param[in] CpuIndex The processor index.\r
738 @param[in] RebasedFlag A pointer to a flag that is set to TRUE\r
739 immediately after AP exits SMM.\r
740\r
741**/\r
742VOID\r
743SemaphoreHook (\r
744 IN UINTN CpuIndex,\r
745 IN volatile BOOLEAN *RebasedFlag\r
746 );\r
747\r
748/**\r
749Configure SMM Code Access Check feature for all processors.\r
750SMM Feature Control MSR will be locked after configuration.\r
751**/\r
752VOID\r
753ConfigSmmCodeAccessCheck (\r
754 VOID\r
755 );\r
756\r
757/**\r
758 Hook the code executed immediately after an RSM instruction on the currently\r
759 executing CPU. The mode of code executed immediately after RSM must be\r
760 detected, and the appropriate hook must be selected. Always clear the auto\r
761 HALT restart flag if it is set.\r
762\r
763 @param[in] CpuIndex The processor index for the currently\r
764 executing CPU.\r
765 @param[in] CpuState Pointer to SMRAM Save State Map for the\r
766 currently executing CPU.\r
767 @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to\r
768 32-bit mode from 64-bit SMM.\r
769 @param[in] NewInstructionPointer Instruction pointer to use if resuming to\r
770 same mode as SMM.\r
771\r
772 @retval The value of the original instruction pointer before it was hooked.\r
773\r
774**/\r
775UINT64\r
776EFIAPI\r
777HookReturnFromSmm (\r
778 IN UINTN CpuIndex,\r
779 SMRAM_SAVE_STATE_MAP *CpuState,\r
780 UINT64 NewInstructionPointer32,\r
781 UINT64 NewInstructionPointer\r
782 );\r
783\r
784/**\r
785 Get the size of the SMI Handler in bytes.\r
786\r
787 @retval The size, in bytes, of the SMI Handler.\r
788\r
789**/\r
790UINTN\r
791EFIAPI\r
792GetSmiHandlerSize (\r
793 VOID\r
794 );\r
795\r
796/**\r
797 Install the SMI handler for the CPU specified by CpuIndex. This function\r
798 is called by the CPU that was elected as monarch during System Management\r
799 Mode initialization.\r
800\r
801 @param[in] CpuIndex The index of the CPU to install the custom SMI handler.\r
802 The value must be between 0 and the NumberOfCpus field\r
803 in the System Management System Table (SMST).\r
804 @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.\r
805 @param[in] SmiStack The stack to use when an SMI is processed by the\r
806 the CPU specified by CpuIndex.\r
807 @param[in] StackSize The size, in bytes, if the stack used when an SMI is\r
808 processed by the CPU specified by CpuIndex.\r
809 @param[in] GdtBase The base address of the GDT to use when an SMI is\r
810 processed by the CPU specified by CpuIndex.\r
811 @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is\r
812 processed by the CPU specified by CpuIndex.\r
813 @param[in] IdtBase The base address of the IDT to use when an SMI is\r
814 processed by the CPU specified by CpuIndex.\r
815 @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is\r
816 processed by the CPU specified by CpuIndex.\r
817 @param[in] Cr3 The base address of the page tables to use when an SMI\r
818 is processed by the CPU specified by CpuIndex.\r
819**/\r
820VOID\r
821EFIAPI\r
822InstallSmiHandler (\r
823 IN UINTN CpuIndex,\r
824 IN UINT32 SmBase,\r
825 IN VOID *SmiStack,\r
826 IN UINTN StackSize,\r
827 IN UINTN GdtBase,\r
828 IN UINTN GdtSize,\r
829 IN UINTN IdtBase,\r
830 IN UINTN IdtSize,\r
831 IN UINT32 Cr3\r
832 );\r
833\r
834/**\r
835 Search module name by input IP address and output it.\r
836\r
837 @param CallerIpAddress Caller instruction pointer.\r
838\r
839**/\r
840VOID\r
841DumpModuleInfoByIp (\r
842 IN UINTN CallerIpAddress\r
843 );\r
21c17193 844\r
717fb604
JY		 845/**\r
846 This function sets memory attribute according to MemoryAttributesTable.\r
847**/\r
848VOID\r
849SetMemMapAttributes (\r
850 VOID\r
851 );\r
852\r
d2fc7711
JY		 853/**\r
854 This function sets UEFI memory attribute according to UEFI memory map.\r
855**/\r
856VOID\r
857SetUefiMemMapAttributes (\r
858 VOID\r
859 );\r
860\r
861/**\r
862 Return if the Address is forbidden as SMM communication buffer.\r
863\r
864 @param[in] Address the address to be checked\r
865\r
866 @return TRUE The address is forbidden as SMM communication buffer.\r
867 @return FALSE The address is allowed as SMM communication buffer.\r
868**/\r
869BOOLEAN\r
870IsSmmCommBufferForbiddenAddress (\r
871 IN UINT64 Address\r
872 );\r
873\r
874/**\r
875 This function caches the UEFI memory map information.\r
876**/\r
877VOID\r
878GetUefiMemoryMap (\r
879 VOID\r
880 );\r
881\r
717fb604
JY		 882/**\r
883 This function sets memory attribute for page table.\r
884**/\r
885VOID\r
886SetPageTableAttributes (\r
887 VOID\r
888 );\r
889\r
890/**\r
891 Return page table base.\r
892\r
893 @return page table base.\r
894**/\r
895UINTN\r
896GetPageTableBase (\r
897 VOID\r
898 );\r
899\r
900/**\r
901 This function sets the attributes for the memory region specified by BaseAddress and\r
902 Length from their current attributes to the attributes specified by Attributes.\r
903\r
904 @param[in] BaseAddress The physical address that is the start address of a memory region.\r
905 @param[in] Length The size in bytes of the memory region.\r
906 @param[in] Attributes The bit mask of attributes to set for the memory region.\r
907 @param[out] IsSplitted TRUE means page table splitted. FALSE means page table not splitted.\r
908\r
909 @retval EFI_SUCCESS The attributes were set for the memory region.\r
910 @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r
911 BaseAddress and Length cannot be modified.\r
912 @retval EFI_INVALID_PARAMETER Length is zero.\r
913 Attributes specified an illegal combination of attributes that\r
914 cannot be set together.\r
915 @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r
916 the memory resource range.\r
917 @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r
918 resource range specified by BaseAddress and Length.\r
919 The bit mask of attributes is not support for the memory resource\r
920 range specified by BaseAddress and Length.\r
921\r
922**/\r
923EFI_STATUS\r
924EFIAPI\r
925SmmSetMemoryAttributesEx (\r
926 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
927 IN UINT64 Length,\r
928 IN UINT64 Attributes,\r
929 OUT BOOLEAN *IsSplitted OPTIONAL\r
930 );\r
931\r
932/**\r
933 This function clears the attributes for the memory region specified by BaseAddress and\r
934 Length from their current attributes to the attributes specified by Attributes.\r
935\r
936 @param[in] BaseAddress The physical address that is the start address of a memory region.\r
937 @param[in] Length The size in bytes of the memory region.\r
938 @param[in] Attributes The bit mask of attributes to clear for the memory region.\r
939 @param[out] IsSplitted TRUE means page table splitted. FALSE means page table not splitted.\r
940\r
941 @retval EFI_SUCCESS The attributes were cleared for the memory region.\r
942 @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r
943 BaseAddress and Length cannot be modified.\r
944 @retval EFI_INVALID_PARAMETER Length is zero.\r
945 Attributes specified an illegal combination of attributes that\r
946 cannot be set together.\r
947 @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r
948 the memory resource range.\r
949 @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r
950 resource range specified by BaseAddress and Length.\r
951 The bit mask of attributes is not support for the memory resource\r
952 range specified by BaseAddress and Length.\r
953\r
954**/\r
955EFI_STATUS\r
956EFIAPI\r
957SmmClearMemoryAttributesEx (\r
958 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
959 IN UINT64 Length,\r
960 IN UINT64 Attributes,\r
961 OUT BOOLEAN *IsSplitted OPTIONAL\r
962 );\r
963\r
21c17193
JY		 964/**\r
965 This API provides a way to allocate memory for page table.\r
966\r
967 This API can be called more once to allocate memory for page tables.\r
968\r
969 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the\r
970 allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL\r
971 is returned. If there is not enough memory remaining to satisfy the request, then NULL is\r
972 returned.\r
973\r
974 @param Pages The number of 4 KB pages to allocate.\r
975\r
976 @return A pointer to the allocated buffer or NULL if allocation fails.\r
977\r
978**/\r
979VOID *\r
980AllocatePageTableMemory (\r
981 IN UINTN Pages\r
982 );\r
983\r
717fb604
JY		 984/**\r
985 Allocate pages for code.\r
986\r
987 @param[in] Pages Number of pages to be allocated.\r
988\r
989 @return Allocated memory.\r
990**/\r
991VOID *\r
992AllocateCodePages (\r
993 IN UINTN Pages\r
994 );\r
995\r
996/**\r
997 Allocate aligned pages for code.\r
998\r
999 @param[in] Pages Number of pages to be allocated.\r
1000 @param[in] Alignment The requested alignment of the allocation.\r
1001 Must be a power of two.\r
1002 If Alignment is zero, then byte alignment is used.\r
1003\r
1004 @return Allocated memory.\r
1005**/\r
1006VOID *\r
1007AllocateAlignedCodePages (\r
1008 IN UINTN Pages,\r
1009 IN UINTN Alignment\r
1010 );\r
1011\r
0bdc9e75
SZ		 1012\r
1013//\r
1014// S3 related global variable and function prototype.\r
1015//\r
1016\r
1017extern BOOLEAN mSmmS3Flag;\r
1018\r
1019/**\r
1020 Initialize SMM S3 resume state structure used during S3 Resume.\r
1021\r
1022 @param[in] Cr3 The base address of the page tables to use in SMM.\r
1023\r
1024**/\r
1025VOID\r
1026InitSmmS3ResumeState (\r
1027 IN UINT32 Cr3\r
1028 );\r
1029\r
1030/**\r
1031 Get ACPI CPU data.\r
1032\r
1033**/\r
1034VOID\r
1035GetAcpiCpuData (\r
1036 VOID\r
1037 );\r
1038\r
1039/**\r
1040 Restore SMM Configuration in S3 boot path.\r
1041\r
1042**/\r
1043VOID\r
1044RestoreSmmConfigurationInS3 (\r
1045 VOID\r
1046 );\r
1047\r
b10d5ddc
SZ		 1048/**\r
1049 Get ACPI S3 enable flag.\r
1050\r
1051**/\r
1052VOID\r
1053GetAcpiS3EnableFlag (\r
1054 VOID\r
1055 );\r
1056\r
4a0f88dd
JF		 1057/**\r
1058 Transfer AP to safe hlt-loop after it finished restore CPU features on S3 patch.\r
1059\r
672b80c8
MK		 1060 @param[in] ApHltLoopCode The address of the safe hlt-loop function.\r
1061 @param[in] TopOfStack A pointer to the new stack to use for the ApHltLoopCode.\r
1062 @param[in] NumberToFinishAddress Address of Semaphore of APs finish count.\r
4a0f88dd
JF		 1063\r
1064**/\r
1065VOID\r
1066TransferApToSafeState (\r
672b80c8
MK		 1067 IN UINTN ApHltLoopCode,\r
1068 IN UINTN TopOfStack,\r
1069 IN UINTN NumberToFinishAddress\r
4a0f88dd
JF		 1070 );\r
1071\r
af4f4b34
JW		 1072/**
1073 This function set given attributes of the memory region specified by
1074 BaseAddress and Length.
1075
1076 @param This The EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL instance.
1077 @param BaseAddress The physical address that is the start address of
1078 a memory region.
1079 @param Length The size in bytes of the memory region.
1080 @param Attributes The bit mask of attributes to set for the memory
1081 region.
1082
1083 @retval EFI_SUCCESS The attributes were set for the memory region.
1084 @retval EFI_INVALID_PARAMETER Length is zero.
1085 Attributes specified an illegal combination of
1086 attributes that cannot be set together.
1087 @retval EFI_UNSUPPORTED The processor does not support one or more
1088 bytes of the memory resource range specified
1089 by BaseAddress and Length.
1090 The bit mask of attributes is not support for
1091 the memory resource range specified by
1092 BaseAddress and Length.
1093
1094**/
1095EFI_STATUS
1096EFIAPI
1097EdkiiSmmSetMemoryAttributes (
1098 IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This,
1099 IN EFI_PHYSICAL_ADDRESS BaseAddress,
1100 IN UINT64 Length,
1101 IN UINT64 Attributes
1102 );
1103
1104/**
1105 This function clears given attributes of the memory region specified by
1106 BaseAddress and Length.
1107
1108 @param This The EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL instance.
1109 @param BaseAddress The physical address that is the start address of
1110 a memory region.
1111 @param Length The size in bytes of the memory region.
1112 @param Attributes The bit mask of attributes to set for the memory
1113 region.
1114
1115 @retval EFI_SUCCESS The attributes were set for the memory region.
1116 @retval EFI_INVALID_PARAMETER Length is zero.
1117 Attributes specified an illegal combination of
1118 attributes that cannot be set together.
1119 @retval EFI_UNSUPPORTED The processor does not support one or more
1120 bytes of the memory resource range specified
1121 by BaseAddress and Length.
1122 The bit mask of attributes is not support for
1123 the memory resource range specified by
1124 BaseAddress and Length.
1125
1126**/
1127EFI_STATUS
1128EFIAPI
1129EdkiiSmmClearMemoryAttributes (
1130 IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This,
1131 IN EFI_PHYSICAL_ADDRESS BaseAddress,
1132 IN UINT64 Length,
1133 IN UINT64 Attributes
1134 );
1135
1136/**
1137 This function retrieve the attributes of the memory region specified by
1138 BaseAddress and Length. If different attributes are got from different part
1139 of the memory region, EFI_NO_MAPPING will be returned.
1140
1141 @param This The EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL instance.
1142 @param BaseAddress The physical address that is the start address of
1143 a memory region.
1144 @param Length The size in bytes of the memory region.
1145 @param Attributes Pointer to attributes returned.
1146
1147 @retval EFI_SUCCESS The attributes got for the memory region.
1148 @retval EFI_INVALID_PARAMETER Length is zero.
1149 Attributes is NULL.
1150 @retval EFI_NO_MAPPING Attributes are not consistent cross the memory
1151 region.
1152 @retval EFI_UNSUPPORTED The processor does not support one or more
1153 bytes of the memory resource range specified
1154 by BaseAddress and Length.
1155 The bit mask of attributes is not support for
1156 the memory resource range specified by
1157 BaseAddress and Length.
1158
1159**/
1160EFI_STATUS
1161EFIAPI
1162EdkiiSmmGetMemoryAttributes (
1163 IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This,
1164 IN EFI_PHYSICAL_ADDRESS BaseAddress,
1165 IN UINT64 Length,
1166 IN UINT64 *Attributes
1167 );
1168
529a5a86 1169#endif\r
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