projects / mirror_edk2.git / blame
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| 529a5a86 MK |
1 | /** @file\r |
| 2 | Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.\r | |
| 3 | \r | |
| f85d3ce2 | 4 | Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r |
| 529a5a86 MK |
5 | This program and the accompanying materials\r |
| 6 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 7 | which accompanies this distribution. The full text of the license may be found at\r | |
| 8 | http://opensource.org/licenses/bsd-license.php\r | |
| 9 | \r | |
| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 12 | \r | |
| 13 | **/\r | |
| 14 | \r | |
| 15 | #ifndef _CPU_PISMMCPUDXESMM_H_\r | |
| 16 | #define _CPU_PISMMCPUDXESMM_H_\r | |
| 17 | \r | |
| 18 | #include <PiSmm.h>\r | |
| 19 | \r | |
| 20 | #include <Protocol/MpService.h>\r | |
| 21 | #include <Protocol/SmmConfiguration.h>\r | |
| 22 | #include <Protocol/SmmCpu.h>\r | |
| 23 | #include <Protocol/SmmAccess2.h>\r | |
| 529a5a86 MK |
24 | #include <Protocol/SmmReadyToLock.h>\r |
| 25 | #include <Protocol/SmmCpuService.h>\r | |
| 26 | \r | |
| 27 | #include <Guid/AcpiS3Context.h>\r | |
| 28 | \r | |
| 29 | #include <Library/BaseLib.h>\r | |
| 30 | #include <Library/IoLib.h>\r | |
| 31 | #include <Library/TimerLib.h>\r | |
| 529a5a86 MK |
32 | #include <Library/SynchronizationLib.h>\r |
| 33 | #include <Library/DebugLib.h>\r | |
| 34 | #include <Library/BaseMemoryLib.h>\r | |
| 35 | #include <Library/PcdLib.h>\r | |
| 36 | #include <Library/CacheMaintenanceLib.h>\r | |
| 37 | #include <Library/MtrrLib.h>\r | |
| 38 | #include <Library/SmmCpuPlatformHookLib.h>\r | |
| 39 | #include <Library/SmmServicesTableLib.h>\r | |
| 40 | #include <Library/MemoryAllocationLib.h>\r | |
| 41 | #include <Library/UefiBootServicesTableLib.h>\r | |
| 42 | #include <Library/UefiRuntimeServicesTableLib.h>\r | |
| 43 | #include <Library/DebugAgentLib.h>\r | |
| 44 | #include <Library/HobLib.h>\r | |
| 45 | #include <Library/LocalApicLib.h>\r | |
| 46 | #include <Library/UefiCpuLib.h>\r | |
| 47 | #include <Library/CpuExceptionHandlerLib.h>\r | |
| 48 | #include <Library/ReportStatusCodeLib.h>\r | |
| 49 | #include <Library/SmmCpuFeaturesLib.h>\r | |
| 50 | #include <Library/PeCoffGetEntryPointLib.h>\r | |
| 51 | \r | |
| 52 | #include <AcpiCpuData.h>\r | |
| 53 | #include <CpuHotPlugData.h>\r | |
| 54 | \r | |
| 55 | #include <Register/Cpuid.h>\r | |
| f85d3ce2 | 56 | #include <Register/Msr.h>\r |
| 529a5a86 MK |
57 | \r |
| 58 | #include "CpuService.h"\r | |
| 59 | #include "SmmProfile.h"\r | |
| 60 | \r | |
| 61 | //\r | |
| 62 | // MSRs required for configuration of SMM Code Access Check\r | |
| 63 | //\r | |
| 64 | #define EFI_MSR_SMM_MCA_CAP 0x17D\r | |
| 65 | #define SMM_CODE_ACCESS_CHK_BIT BIT58\r | |
| 66 | \r | |
| 67 | #define SMM_FEATURE_CONTROL_LOCK_BIT BIT0\r | |
| 68 | #define SMM_CODE_CHK_EN_BIT BIT2\r | |
| 69 | \r | |
| 70 | ///\r | |
| 71 | /// Page Table Entry\r | |
| 72 | ///\r | |
| 73 | #define IA32_PG_P BIT0\r | |
| 74 | #define IA32_PG_RW BIT1\r | |
| 881520ea | 75 | #define IA32_PG_U BIT2\r |
| 529a5a86 MK |
76 | #define IA32_PG_WT BIT3\r |
| 77 | #define IA32_PG_CD BIT4\r | |
| 78 | #define IA32_PG_A BIT5\r | |
| 881520ea | 79 | #define IA32_PG_D BIT6\r |
| 529a5a86 MK |
80 | #define IA32_PG_PS BIT7\r |
| 81 | #define IA32_PG_PAT_2M BIT12\r | |
| 82 | #define IA32_PG_PAT_4K IA32_PG_PS\r | |
| 83 | #define IA32_PG_PMNT BIT62\r | |
| 84 | #define IA32_PG_NX BIT63\r | |
| 85 | \r | |
| 881520ea JY |
86 | #define PAGE_ATTRIBUTE_BITS (IA32_PG_RW | IA32_PG_P)\r |
| 87 | //\r | |
| 88 | // Bits 1, 2, 5, 6 are reserved in the IA32 PAE PDPTE\r | |
| 89 | // X64 PAE PDPTE does not have such restriction\r | |
| 90 | //\r | |
| 91 | #define IA32_PAE_PDPTE_ATTRIBUTE_BITS (IA32_PG_P)\r | |
| 92 | \r | |
| 529a5a86 MK |
93 | //\r |
| 94 | // Size of Task-State Segment defined in IA32 Manual\r | |
| 95 | //\r | |
| 96 | #define TSS_SIZE 104\r | |
| 97 | #define TSS_X64_IST1_OFFSET 36\r | |
| 98 | #define TSS_IA32_CR3_OFFSET 28\r | |
| 99 | #define TSS_IA32_ESP_OFFSET 56\r | |
| 100 | \r | |
| 101 | //\r | |
| 102 | // Code select value\r | |
| 103 | //\r | |
| 104 | #define PROTECT_MODE_CODE_SEGMENT 0x08\r | |
| 105 | #define LONG_MODE_CODE_SEGMENT 0x38\r | |
| 106 | \r | |
| 107 | //\r | |
| 108 | // The size 0x20 must be bigger than\r | |
| 109 | // the size of template code of SmmInit. Currently,\r | |
| 110 | // the size of SmmInit requires the 0x16 Bytes buffer\r | |
| 111 | // at least.\r | |
| 112 | //\r | |
| 113 | #define BACK_BUF_SIZE 0x20\r | |
| 114 | \r | |
| 115 | #define EXCEPTION_VECTOR_NUMBER 0x20\r | |
| 116 | \r | |
| 117 | #define INVALID_APIC_ID 0xFFFFFFFFFFFFFFFFULL\r | |
| 118 | \r | |
| 119 | typedef UINT32 SMM_CPU_ARRIVAL_EXCEPTIONS;\r | |
| 120 | #define ARRIVAL_EXCEPTION_BLOCKED 0x1\r | |
| 121 | #define ARRIVAL_EXCEPTION_DELAYED 0x2\r | |
| 122 | #define ARRIVAL_EXCEPTION_SMI_DISABLED 0x4\r | |
| 123 | \r | |
| 124 | //\r | |
| 125 | // Private structure for the SMM CPU module that is stored in DXE Runtime memory\r | |
| 126 | // Contains the SMM Configuration Protocols that is produced.\r | |
| 127 | // Contains a mix of DXE and SMM contents. All the fields must be used properly.\r | |
| 128 | //\r | |
| 129 | #define SMM_CPU_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('s', 'c', 'p', 'u')\r | |
| 130 | \r | |
| 131 | typedef struct {\r | |
| 132 | UINTN Signature;\r | |
| 133 | \r | |
| 134 | EFI_HANDLE SmmCpuHandle;\r | |
| 135 | \r | |
| 136 | EFI_PROCESSOR_INFORMATION *ProcessorInfo;\r | |
| 137 | SMM_CPU_OPERATION *Operation;\r | |
| 138 | UINTN *CpuSaveStateSize;\r | |
| 139 | VOID **CpuSaveState;\r | |
| 140 | \r | |
| 141 | EFI_SMM_RESERVED_SMRAM_REGION SmmReservedSmramRegion[1];\r | |
| 142 | EFI_SMM_ENTRY_CONTEXT SmmCoreEntryContext;\r | |
| 143 | EFI_SMM_ENTRY_POINT SmmCoreEntry;\r | |
| 144 | \r | |
| 145 | EFI_SMM_CONFIGURATION_PROTOCOL SmmConfiguration;\r | |
| 146 | } SMM_CPU_PRIVATE_DATA;\r | |
| 147 | \r | |
| 148 | extern SMM_CPU_PRIVATE_DATA *gSmmCpuPrivate;\r | |
| 149 | extern CPU_HOT_PLUG_DATA mCpuHotPlugData;\r | |
| 150 | extern UINTN mMaxNumberOfCpus;\r | |
| 151 | extern UINTN mNumberOfCpus;\r | |
| 529a5a86 MK |
152 | extern EFI_SMM_CPU_PROTOCOL mSmmCpu;\r |
| 153 | \r | |
| 154 | ///\r | |
| 155 | /// The mode of the CPU at the time an SMI occurs\r | |
| 156 | ///\r | |
| 157 | extern UINT8 mSmmSaveStateRegisterLma;\r | |
| 158 | \r | |
| 159 | \r | |
| 160 | //\r | |
| 161 | // SMM CPU Protocol function prototypes.\r | |
| 162 | //\r | |
| 163 | \r | |
| 164 | /**\r | |
| 165 | Read information from the CPU save state.\r | |
| 166 | \r | |
| 167 | @param This EFI_SMM_CPU_PROTOCOL instance\r | |
| 168 | @param Width The number of bytes to read from the CPU save state.\r | |
| 169 | @param Register Specifies the CPU register to read form the save state.\r | |
| 170 | @param CpuIndex Specifies the zero-based index of the CPU save state\r | |
| 171 | @param Buffer Upon return, this holds the CPU register value read from the save state.\r | |
| 172 | \r | |
| 173 | @retval EFI_SUCCESS The register was read from Save State\r | |
| 174 | @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor\r | |
| 175 | @retval EFI_INVALID_PARAMTER This or Buffer is NULL.\r | |
| 176 | \r | |
| 177 | **/\r | |
| 178 | EFI_STATUS\r | |
| 179 | EFIAPI\r | |
| 180 | SmmReadSaveState (\r | |
| 181 | IN CONST EFI_SMM_CPU_PROTOCOL *This,\r | |
| 182 | IN UINTN Width,\r | |
| 183 | IN EFI_SMM_SAVE_STATE_REGISTER Register,\r | |
| 184 | IN UINTN CpuIndex,\r | |
| 185 | OUT VOID *Buffer\r | |
| 186 | );\r | |
| 187 | \r | |
| 188 | /**\r | |
| 189 | Write data to the CPU save state.\r | |
| 190 | \r | |
| 191 | @param This EFI_SMM_CPU_PROTOCOL instance\r | |
| 192 | @param Width The number of bytes to read from the CPU save state.\r | |
| 193 | @param Register Specifies the CPU register to write to the save state.\r | |
| 194 | @param CpuIndex Specifies the zero-based index of the CPU save state\r | |
| 195 | @param Buffer Upon entry, this holds the new CPU register value.\r | |
| 196 | \r | |
| 197 | @retval EFI_SUCCESS The register was written from Save State\r | |
| 198 | @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor\r | |
| 199 | @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct\r | |
| 200 | \r | |
| 201 | **/\r | |
| 202 | EFI_STATUS\r | |
| 203 | EFIAPI\r | |
| 204 | SmmWriteSaveState (\r | |
| 205 | IN CONST EFI_SMM_CPU_PROTOCOL *This,\r | |
| 206 | IN UINTN Width,\r | |
| 207 | IN EFI_SMM_SAVE_STATE_REGISTER Register,\r | |
| 208 | IN UINTN CpuIndex,\r | |
| 209 | IN CONST VOID *Buffer\r | |
| 210 | );\r | |
| 211 | \r | |
| 212 | /**\r | |
| 213 | Read a CPU Save State register on the target processor.\r | |
| 214 | \r | |
| 215 | This function abstracts the differences that whether the CPU Save State register is in the\r | |
| 216 | IA32 CPU Save State Map or X64 CPU Save State Map.\r | |
| 217 | \r | |
| 218 | This function supports reading a CPU Save State register in SMBase relocation handler.\r | |
| 219 | \r | |
| 220 | @param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r | |
| 221 | @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r | |
| 222 | @param[in] Width The number of bytes to read from the CPU save state.\r | |
| 223 | @param[out] Buffer Upon return, this holds the CPU register value read from the save state.\r | |
| 224 | \r | |
| 225 | @retval EFI_SUCCESS The register was read from Save State.\r | |
| 226 | @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r | |
| 227 | @retval EFI_INVALID_PARAMTER This or Buffer is NULL.\r | |
| 228 | \r | |
| 229 | **/\r | |
| 230 | EFI_STATUS\r | |
| 231 | EFIAPI\r | |
| 232 | ReadSaveStateRegister (\r | |
| 233 | IN UINTN CpuIndex,\r | |
| 234 | IN EFI_SMM_SAVE_STATE_REGISTER Register,\r | |
| 235 | IN UINTN Width,\r | |
| 236 | OUT VOID *Buffer\r | |
| 237 | );\r | |
| 238 | \r | |
| 239 | /**\r | |
| 240 | Write value to a CPU Save State register on the target processor.\r | |
| 241 | \r | |
| 242 | This function abstracts the differences that whether the CPU Save State register is in the\r | |
| 243 | IA32 CPU Save State Map or X64 CPU Save State Map.\r | |
| 244 | \r | |
| 245 | This function supports writing a CPU Save State register in SMBase relocation handler.\r | |
| 246 | \r | |
| 247 | @param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r | |
| 248 | @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r | |
| 249 | @param[in] Width The number of bytes to read from the CPU save state.\r | |
| 250 | @param[in] Buffer Upon entry, this holds the new CPU register value.\r | |
| 251 | \r | |
| 252 | @retval EFI_SUCCESS The register was written to Save State.\r | |
| 253 | @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r | |
| 254 | @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct.\r | |
| 255 | \r | |
| 256 | **/\r | |
| 257 | EFI_STATUS\r | |
| 258 | EFIAPI\r | |
| 259 | WriteSaveStateRegister (\r | |
| 260 | IN UINTN CpuIndex,\r | |
| 261 | IN EFI_SMM_SAVE_STATE_REGISTER Register,\r | |
| 262 | IN UINTN Width,\r | |
| 263 | IN CONST VOID *Buffer\r | |
| 264 | );\r | |
| 265 | \r | |
| 266 | //\r | |
| 267 | //\r | |
| 268 | //\r | |
| 269 | typedef struct {\r | |
| 270 | UINT32 Offset;\r | |
| 271 | UINT16 Segment;\r | |
| 272 | UINT16 Reserved;\r | |
| 273 | } IA32_FAR_ADDRESS;\r | |
| 274 | \r | |
| 275 | extern IA32_FAR_ADDRESS gSmmJmpAddr;\r | |
| 276 | \r | |
| 277 | extern CONST UINT8 gcSmmInitTemplate[];\r | |
| 278 | extern CONST UINT16 gcSmmInitSize;\r | |
| 279 | extern UINT32 gSmmCr0;\r | |
| 280 | extern UINT32 gSmmCr3;\r | |
| 281 | extern UINT32 gSmmCr4;\r | |
| 282 | extern UINTN gSmmInitStack;\r | |
| 283 | \r | |
| 284 | /**\r | |
| 285 | Semaphore operation for all processor relocate SMMBase.\r | |
| 286 | **/\r | |
| 287 | VOID\r | |
| 288 | EFIAPI\r | |
| 289 | SmmRelocationSemaphoreComplete (\r | |
| 290 | VOID\r | |
| 291 | );\r | |
| 292 | \r | |
| 293 | ///\r | |
| 294 | /// The type of SMM CPU Information\r | |
| 295 | ///\r | |
| 296 | typedef struct {\r | |
| ed3d5ecb | 297 | SPIN_LOCK *Busy;\r |
| 529a5a86 MK |
298 | volatile EFI_AP_PROCEDURE Procedure;\r |
| 299 | volatile VOID *Parameter;\r | |
| ed3d5ecb JF |
300 | volatile UINT32 *Run;\r |
| 301 | volatile BOOLEAN *Present;\r | |
| 529a5a86 MK |
302 | } SMM_CPU_DATA_BLOCK;\r |
| 303 | \r | |
| 304 | typedef enum {\r | |
| 305 | SmmCpuSyncModeTradition,\r | |
| 306 | SmmCpuSyncModeRelaxedAp,\r | |
| 307 | SmmCpuSyncModeMax\r | |
| 308 | } SMM_CPU_SYNC_MODE;\r | |
| 309 | \r | |
| 310 | typedef struct {\r | |
| 311 | //\r | |
| 312 | // Pointer to an array. The array should be located immediately after this structure\r | |
| 313 | // so that UC cache-ability can be set together.\r | |
| 314 | //\r | |
| 315 | SMM_CPU_DATA_BLOCK *CpuData;\r | |
| fe3a75bc | 316 | volatile UINT32 *Counter;\r |
| 529a5a86 | 317 | volatile UINT32 BspIndex;\r |
| fe3a75bc JF |
318 | volatile BOOLEAN *InsideSmm;\r |
| 319 | volatile BOOLEAN *AllCpusInSync;\r | |
| 529a5a86 MK |
320 | volatile SMM_CPU_SYNC_MODE EffectiveSyncMode;\r |
| 321 | volatile BOOLEAN SwitchBsp;\r | |
| 322 | volatile BOOLEAN *CandidateBsp;\r | |
| 323 | } SMM_DISPATCHER_MP_SYNC_DATA;\r | |
| 324 | \r | |
| 695e62d1 JF |
325 | #define MSR_SPIN_LOCK_INIT_NUM 15\r |
| 326 | \r | |
| 529a5a86 | 327 | typedef struct {\r |
| dc99315b | 328 | SPIN_LOCK *SpinLock;\r |
| 529a5a86 MK |
329 | UINT32 MsrIndex;\r |
| 330 | } MP_MSR_LOCK;\r | |
| 331 | \r | |
| 332 | #define SMM_PSD_OFFSET 0xfb00\r | |
| 333 | \r | |
| 334 | typedef struct {\r | |
| 335 | UINT64 Signature; // Offset 0x00\r | |
| 336 | UINT16 Reserved1; // Offset 0x08\r | |
| 337 | UINT16 Reserved2; // Offset 0x0A\r | |
| 338 | UINT16 Reserved3; // Offset 0x0C\r | |
| 339 | UINT16 SmmCs; // Offset 0x0E\r | |
| 340 | UINT16 SmmDs; // Offset 0x10\r | |
| 341 | UINT16 SmmSs; // Offset 0x12\r | |
| 342 | UINT16 SmmOtherSegment; // Offset 0x14\r | |
| 343 | UINT16 Reserved4; // Offset 0x16\r | |
| 344 | UINT64 Reserved5; // Offset 0x18\r | |
| 345 | UINT64 Reserved6; // Offset 0x20\r | |
| 346 | UINT64 Reserved7; // Offset 0x28\r | |
| 347 | UINT64 SmmGdtPtr; // Offset 0x30\r | |
| 348 | UINT32 SmmGdtSize; // Offset 0x38\r | |
| 349 | UINT32 Reserved8; // Offset 0x3C\r | |
| 350 | UINT64 Reserved9; // Offset 0x40\r | |
| 351 | UINT64 Reserved10; // Offset 0x48\r | |
| 352 | UINT16 Reserved11; // Offset 0x50\r | |
| 353 | UINT16 Reserved12; // Offset 0x52\r | |
| 354 | UINT32 Reserved13; // Offset 0x54\r | |
| 355 | UINT64 MtrrBaseMaskPtr; // Offset 0x58\r | |
| 356 | } PROCESSOR_SMM_DESCRIPTOR;\r | |
| 357 | \r | |
| 1d648531 JF |
358 | \r |
| 359 | ///\r | |
| 360 | /// All global semaphores' pointer\r | |
| 361 | ///\r | |
| 362 | typedef struct {\r | |
| 363 | volatile UINT32 *Counter;\r | |
| 364 | volatile BOOLEAN *InsideSmm;\r | |
| 365 | volatile BOOLEAN *AllCpusInSync;\r | |
| 366 | SPIN_LOCK *PFLock;\r | |
| 367 | SPIN_LOCK *CodeAccessCheckLock;\r | |
| 6c4c15fa | 368 | SPIN_LOCK *MemoryMappedLock;\r |
| 1d648531 JF |
369 | } SMM_CPU_SEMAPHORE_GLOBAL;\r |
| 370 | \r | |
| 4e920581 JF |
371 | ///\r |
| 372 | /// All semaphores for each processor\r | |
| 373 | ///\r | |
| 374 | typedef struct {\r | |
| 375 | SPIN_LOCK *Busy;\r | |
| 376 | volatile UINT32 *Run;\r | |
| 377 | volatile BOOLEAN *Present;\r | |
| 378 | } SMM_CPU_SEMAPHORE_CPU;\r | |
| 379 | \r | |
| 695e62d1 JF |
380 | ///\r |
| 381 | /// All MSRs semaphores' pointer and counter\r | |
| 382 | ///\r | |
| 383 | typedef struct {\r | |
| 384 | SPIN_LOCK *Msr;\r | |
| 385 | UINTN AvailableCounter;\r | |
| 386 | } SMM_CPU_SEMAPHORE_MSR;\r | |
| 4e920581 | 387 | \r |
| 1d648531 JF |
388 | ///\r |
| 389 | /// All semaphores' information\r | |
| 390 | ///\r | |
| 391 | typedef struct {\r | |
| 392 | SMM_CPU_SEMAPHORE_GLOBAL SemaphoreGlobal;\r | |
| 4e920581 | 393 | SMM_CPU_SEMAPHORE_CPU SemaphoreCpu;\r |
| 695e62d1 | 394 | SMM_CPU_SEMAPHORE_MSR SemaphoreMsr;\r |
| 1d648531 JF |
395 | } SMM_CPU_SEMAPHORES;\r |
| 396 | \r | |
| 529a5a86 MK |
397 | extern IA32_DESCRIPTOR gcSmiGdtr;\r |
| 398 | extern IA32_DESCRIPTOR gcSmiIdtr;\r | |
| 399 | extern VOID *gcSmiIdtrPtr;\r | |
| 400 | extern CONST PROCESSOR_SMM_DESCRIPTOR gcPsd;\r | |
| 401 | extern UINT64 gPhyMask;\r | |
| 529a5a86 | 402 | extern SMM_DISPATCHER_MP_SYNC_DATA *mSmmMpSyncData;\r |
| 529a5a86 MK |
403 | extern UINTN mSmmStackArrayBase;\r |
| 404 | extern UINTN mSmmStackArrayEnd;\r | |
| 405 | extern UINTN mSmmStackSize;\r | |
| 406 | extern EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService;\r | |
| 407 | extern IA32_DESCRIPTOR gcSmiInitGdtr;\r | |
| dc99315b JF |
408 | extern SMM_CPU_SEMAPHORES mSmmCpuSemaphores;\r |
| 409 | extern UINTN mSemaphoreSize;\r | |
| fe3a75bc JF |
410 | extern SPIN_LOCK *mPFLock;\r |
| 411 | extern SPIN_LOCK *mConfigSmmCodeAccessCheckLock;\r | |
| 6c4c15fa | 412 | extern SPIN_LOCK *mMemoryMappedLock;\r |
| 529a5a86 MK |
413 | \r |
| 414 | /**\r | |
| 415 | Create 4G PageTable in SMRAM.\r | |
| 416 | \r | |
| 417 | @param ExtraPages Additional page numbers besides for 4G memory\r | |
| 881520ea | 418 | @param Is32BitPageTable Whether the page table is 32-bit PAE\r |
| 529a5a86 MK |
419 | @return PageTable Address\r |
| 420 | \r | |
| 421 | **/\r | |
| 422 | UINT32\r | |
| 423 | Gen4GPageTable (\r | |
| 881520ea JY |
424 | IN UINTN ExtraPages,\r |
| 425 | IN BOOLEAN Is32BitPageTable\r | |
| 529a5a86 MK |
426 | );\r |
| 427 | \r | |
| 428 | \r | |
| 429 | /**\r | |
| 430 | Initialize global data for MP synchronization.\r | |
| 431 | \r | |
| 432 | @param Stacks Base address of SMI stack buffer for all processors.\r | |
| 433 | @param StackSize Stack size for each processor in SMM.\r | |
| 434 | \r | |
| 435 | **/\r | |
| 436 | UINT32\r | |
| 437 | InitializeMpServiceData (\r | |
| 438 | IN VOID *Stacks,\r | |
| 439 | IN UINTN StackSize\r | |
| 440 | );\r | |
| 441 | \r | |
| 442 | /**\r | |
| 443 | Initialize Timer for SMM AP Sync.\r | |
| 444 | \r | |
| 445 | **/\r | |
| 446 | VOID\r | |
| 447 | InitializeSmmTimer (\r | |
| 448 | VOID\r | |
| 449 | );\r | |
| 450 | \r | |
| 451 | /**\r | |
| 452 | Start Timer for SMM AP Sync.\r | |
| 453 | \r | |
| 454 | **/\r | |
| 455 | UINT64\r | |
| 456 | EFIAPI\r | |
| 457 | StartSyncTimer (\r | |
| 458 | VOID\r | |
| 459 | );\r | |
| 460 | \r | |
| 461 | /**\r | |
| 462 | Check if the SMM AP Sync timer is timeout.\r | |
| 463 | \r | |
| 464 | @param Timer The start timer from the begin.\r | |
| 465 | \r | |
| 466 | **/\r | |
| 467 | BOOLEAN\r | |
| 468 | EFIAPI\r | |
| 469 | IsSyncTimerTimeout (\r | |
| 470 | IN UINT64 Timer\r | |
| 471 | );\r | |
| 472 | \r | |
| 473 | /**\r | |
| 474 | Initialize IDT for SMM Stack Guard.\r | |
| 475 | \r | |
| 476 | **/\r | |
| 477 | VOID\r | |
| 478 | EFIAPI\r | |
| 479 | InitializeIDTSmmStackGuard (\r | |
| 480 | VOID\r | |
| 481 | );\r | |
| 482 | \r | |
| fe5f1949 JY |
483 | /**\r |
| 484 | Initialize Gdt for all processors.\r | |
| 485 | \r | |
| 486 | @param[in] Cr3 CR3 value.\r | |
| 487 | @param[out] GdtStepSize The step size for GDT table.\r | |
| 488 | \r | |
| 489 | @return GdtBase for processor 0.\r | |
| 490 | GdtBase for processor X is: GdtBase + (GdtStepSize * X)\r | |
| 491 | **/\r | |
| 492 | VOID *\r | |
| 493 | InitGdt (\r | |
| 494 | IN UINTN Cr3,\r | |
| 495 | OUT UINTN *GdtStepSize\r | |
| 496 | );\r | |
| 497 | \r | |
| 529a5a86 MK |
498 | /**\r |
| 499 | \r | |
| 500 | Register the SMM Foundation entry point.\r | |
| 501 | \r | |
| 502 | @param This Pointer to EFI_SMM_CONFIGURATION_PROTOCOL instance\r | |
| 503 | @param SmmEntryPoint SMM Foundation EntryPoint\r | |
| 504 | \r | |
| 505 | @retval EFI_SUCCESS Successfully to register SMM foundation entry point\r | |
| 506 | \r | |
| 507 | **/\r | |
| 508 | EFI_STATUS\r | |
| 509 | EFIAPI\r | |
| 510 | RegisterSmmEntry (\r | |
| 511 | IN CONST EFI_SMM_CONFIGURATION_PROTOCOL *This,\r | |
| 512 | IN EFI_SMM_ENTRY_POINT SmmEntryPoint\r | |
| 513 | );\r | |
| 514 | \r | |
| 515 | /**\r | |
| 516 | Create PageTable for SMM use.\r | |
| 517 | \r | |
| 518 | @return PageTable Address\r | |
| 519 | \r | |
| 520 | **/\r | |
| 521 | UINT32\r | |
| 522 | SmmInitPageTable (\r | |
| 523 | VOID\r | |
| 524 | );\r | |
| 525 | \r | |
| 526 | /**\r | |
| 527 | Schedule a procedure to run on the specified CPU.\r | |
| 528 | \r | |
| 529 | @param Procedure The address of the procedure to run\r | |
| 530 | @param CpuIndex Target CPU number\r | |
| 531 | @param ProcArguments The parameter to pass to the procedure\r | |
| 532 | \r | |
| 533 | @retval EFI_INVALID_PARAMETER CpuNumber not valid\r | |
| 534 | @retval EFI_INVALID_PARAMETER CpuNumber specifying BSP\r | |
| 535 | @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM\r | |
| 536 | @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy\r | |
| 537 | @retval EFI_SUCCESS - The procedure has been successfully scheduled\r | |
| 538 | \r | |
| 539 | **/\r | |
| 540 | EFI_STATUS\r | |
| 541 | EFIAPI\r | |
| 542 | SmmStartupThisAp (\r | |
| 543 | IN EFI_AP_PROCEDURE Procedure,\r | |
| 544 | IN UINTN CpuIndex,\r | |
| 545 | IN OUT VOID *ProcArguments OPTIONAL\r | |
| 546 | );\r | |
| 547 | \r | |
| 548 | /**\r | |
| 549 | Schedule a procedure to run on the specified CPU in a blocking fashion.\r | |
| 550 | \r | |
| 551 | @param Procedure The address of the procedure to run\r | |
| 552 | @param CpuIndex Target CPU Index\r | |
| 553 | @param ProcArguments The parameter to pass to the procedure\r | |
| 554 | \r | |
| 555 | @retval EFI_INVALID_PARAMETER CpuNumber not valid\r | |
| 556 | @retval EFI_INVALID_PARAMETER CpuNumber specifying BSP\r | |
| 557 | @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM\r | |
| 558 | @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy\r | |
| 559 | @retval EFI_SUCCESS The procedure has been successfully scheduled\r | |
| 560 | \r | |
| 561 | **/\r | |
| 562 | EFI_STATUS\r | |
| 563 | EFIAPI\r | |
| 564 | SmmBlockingStartupThisAp (\r | |
| 565 | IN EFI_AP_PROCEDURE Procedure,\r | |
| 566 | IN UINTN CpuIndex,\r | |
| 567 | IN OUT VOID *ProcArguments OPTIONAL\r | |
| 568 | );\r | |
| 569 | \r | |
| 570 | /**\r | |
| 571 | Initialize MP synchronization data.\r | |
| 572 | \r | |
| 573 | **/\r | |
| 574 | VOID\r | |
| 575 | EFIAPI\r | |
| 576 | InitializeMpSyncData (\r | |
| 577 | VOID\r | |
| 578 | );\r | |
| 579 | \r | |
| 580 | /**\r | |
| 581 | \r | |
| 582 | Find out SMRAM information including SMRR base and SMRR size.\r | |
| 583 | \r | |
| 584 | @param SmrrBase SMRR base\r | |
| 585 | @param SmrrSize SMRR size\r | |
| 586 | \r | |
| 587 | **/\r | |
| 588 | VOID\r | |
| 589 | FindSmramInfo (\r | |
| 590 | OUT UINT32 *SmrrBase,\r | |
| 591 | OUT UINT32 *SmrrSize\r | |
| 592 | );\r | |
| 593 | \r | |
| 594 | /**\r | |
| 0bdc9e75 | 595 | Relocate SmmBases for each processor.\r |
| 529a5a86 | 596 | \r |
| 0bdc9e75 | 597 | Execute on first boot and all S3 resumes\r |
| 529a5a86 MK |
598 | \r |
| 599 | **/\r | |
| 600 | VOID\r | |
| 0bdc9e75 SZ |
601 | EFIAPI\r |
| 602 | SmmRelocateBases (\r | |
| 529a5a86 MK |
603 | VOID\r |
| 604 | );\r | |
| 605 | \r | |
| 606 | /**\r | |
| 607 | Page Fault handler for SMM use.\r | |
| 608 | \r | |
| 609 | @param InterruptType Defines the type of interrupt or exception that\r | |
| 610 | occurred on the processor.This parameter is processor architecture specific.\r | |
| 611 | @param SystemContext A pointer to the processor context when\r | |
| 612 | the interrupt occurred on the processor.\r | |
| 613 | **/\r | |
| 614 | VOID\r | |
| 615 | EFIAPI\r | |
| 616 | SmiPFHandler (\r | |
| 617 | IN EFI_EXCEPTION_TYPE InterruptType,\r | |
| 618 | IN EFI_SYSTEM_CONTEXT SystemContext\r | |
| 619 | );\r | |
| 620 | \r | |
| 621 | /**\r | |
| 622 | Perform the remaining tasks.\r | |
| 623 | \r | |
| 624 | **/\r | |
| 625 | VOID\r | |
| 626 | PerformRemainingTasks (\r | |
| 627 | VOID\r | |
| 628 | );\r | |
| 629 | \r | |
| 9f419739 JY |
630 | /**\r |
| 631 | Perform the pre tasks.\r | |
| 632 | \r | |
| 633 | **/\r | |
| 634 | VOID\r | |
| 635 | PerformPreTasks (\r | |
| 636 | VOID\r | |
| 637 | );\r | |
| 638 | \r | |
| 529a5a86 MK |
639 | /**\r |
| 640 | Initialize MSR spin lock by MSR index.\r | |
| 641 | \r | |
| 642 | @param MsrIndex MSR index value.\r | |
| 643 | \r | |
| 644 | **/\r | |
| 645 | VOID\r | |
| 646 | InitMsrSpinLockByIndex (\r | |
| 647 | IN UINT32 MsrIndex\r | |
| 648 | );\r | |
| 649 | \r | |
| 650 | /**\r | |
| 651 | Hook return address of SMM Save State so that semaphore code\r | |
| 652 | can be executed immediately after AP exits SMM to indicate to\r | |
| 653 | the BSP that an AP has exited SMM after SMBASE relocation.\r | |
| 654 | \r | |
| 655 | @param[in] CpuIndex The processor index.\r | |
| 656 | @param[in] RebasedFlag A pointer to a flag that is set to TRUE\r | |
| 657 | immediately after AP exits SMM.\r | |
| 658 | \r | |
| 659 | **/\r | |
| 660 | VOID\r | |
| 661 | SemaphoreHook (\r | |
| 662 | IN UINTN CpuIndex,\r | |
| 663 | IN volatile BOOLEAN *RebasedFlag\r | |
| 664 | );\r | |
| 665 | \r | |
| 666 | /**\r | |
| 667 | Configure SMM Code Access Check feature for all processors.\r | |
| 668 | SMM Feature Control MSR will be locked after configuration.\r | |
| 669 | **/\r | |
| 670 | VOID\r | |
| 671 | ConfigSmmCodeAccessCheck (\r | |
| 672 | VOID\r | |
| 673 | );\r | |
| 674 | \r | |
| 675 | /**\r | |
| 676 | Hook the code executed immediately after an RSM instruction on the currently\r | |
| 677 | executing CPU. The mode of code executed immediately after RSM must be\r | |
| 678 | detected, and the appropriate hook must be selected. Always clear the auto\r | |
| 679 | HALT restart flag if it is set.\r | |
| 680 | \r | |
| 681 | @param[in] CpuIndex The processor index for the currently\r | |
| 682 | executing CPU.\r | |
| 683 | @param[in] CpuState Pointer to SMRAM Save State Map for the\r | |
| 684 | currently executing CPU.\r | |
| 685 | @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to\r | |
| 686 | 32-bit mode from 64-bit SMM.\r | |
| 687 | @param[in] NewInstructionPointer Instruction pointer to use if resuming to\r | |
| 688 | same mode as SMM.\r | |
| 689 | \r | |
| 690 | @retval The value of the original instruction pointer before it was hooked.\r | |
| 691 | \r | |
| 692 | **/\r | |
| 693 | UINT64\r | |
| 694 | EFIAPI\r | |
| 695 | HookReturnFromSmm (\r | |
| 696 | IN UINTN CpuIndex,\r | |
| 697 | SMRAM_SAVE_STATE_MAP *CpuState,\r | |
| 698 | UINT64 NewInstructionPointer32,\r | |
| 699 | UINT64 NewInstructionPointer\r | |
| 700 | );\r | |
| 701 | \r | |
| 702 | /**\r | |
| 703 | Get the size of the SMI Handler in bytes.\r | |
| 704 | \r | |
| 705 | @retval The size, in bytes, of the SMI Handler.\r | |
| 706 | \r | |
| 707 | **/\r | |
| 708 | UINTN\r | |
| 709 | EFIAPI\r | |
| 710 | GetSmiHandlerSize (\r | |
| 711 | VOID\r | |
| 712 | );\r | |
| 713 | \r | |
| 714 | /**\r | |
| 715 | Install the SMI handler for the CPU specified by CpuIndex. This function\r | |
| 716 | is called by the CPU that was elected as monarch during System Management\r | |
| 717 | Mode initialization.\r | |
| 718 | \r | |
| 719 | @param[in] CpuIndex The index of the CPU to install the custom SMI handler.\r | |
| 720 | The value must be between 0 and the NumberOfCpus field\r | |
| 721 | in the System Management System Table (SMST).\r | |
| 722 | @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.\r | |
| 723 | @param[in] SmiStack The stack to use when an SMI is processed by the\r | |
| 724 | the CPU specified by CpuIndex.\r | |
| 725 | @param[in] StackSize The size, in bytes, if the stack used when an SMI is\r | |
| 726 | processed by the CPU specified by CpuIndex.\r | |
| 727 | @param[in] GdtBase The base address of the GDT to use when an SMI is\r | |
| 728 | processed by the CPU specified by CpuIndex.\r | |
| 729 | @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is\r | |
| 730 | processed by the CPU specified by CpuIndex.\r | |
| 731 | @param[in] IdtBase The base address of the IDT to use when an SMI is\r | |
| 732 | processed by the CPU specified by CpuIndex.\r | |
| 733 | @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is\r | |
| 734 | processed by the CPU specified by CpuIndex.\r | |
| 735 | @param[in] Cr3 The base address of the page tables to use when an SMI\r | |
| 736 | is processed by the CPU specified by CpuIndex.\r | |
| 737 | **/\r | |
| 738 | VOID\r | |
| 739 | EFIAPI\r | |
| 740 | InstallSmiHandler (\r | |
| 741 | IN UINTN CpuIndex,\r | |
| 742 | IN UINT32 SmBase,\r | |
| 743 | IN VOID *SmiStack,\r | |
| 744 | IN UINTN StackSize,\r | |
| 745 | IN UINTN GdtBase,\r | |
| 746 | IN UINTN GdtSize,\r | |
| 747 | IN UINTN IdtBase,\r | |
| 748 | IN UINTN IdtSize,\r | |
| 749 | IN UINT32 Cr3\r | |
| 750 | );\r | |
| 751 | \r | |
| 752 | /**\r | |
| 753 | Search module name by input IP address and output it.\r | |
| 754 | \r | |
| 755 | @param CallerIpAddress Caller instruction pointer.\r | |
| 756 | \r | |
| 757 | **/\r | |
| 758 | VOID\r | |
| 759 | DumpModuleInfoByIp (\r | |
| 760 | IN UINTN CallerIpAddress\r | |
| 761 | );\r | |
| 21c17193 JY |
762 | \r |
| 763 | /**\r | |
| 764 | This API provides a way to allocate memory for page table.\r | |
| 765 | \r | |
| 766 | This API can be called more once to allocate memory for page tables.\r | |
| 767 | \r | |
| 768 | Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the\r | |
| 769 | allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL\r | |
| 770 | is returned. If there is not enough memory remaining to satisfy the request, then NULL is\r | |
| 771 | returned.\r | |
| 772 | \r | |
| 773 | @param Pages The number of 4 KB pages to allocate.\r | |
| 774 | \r | |
| 775 | @return A pointer to the allocated buffer or NULL if allocation fails.\r | |
| 776 | \r | |
| 777 | **/\r | |
| 778 | VOID *\r | |
| 779 | AllocatePageTableMemory (\r | |
| 780 | IN UINTN Pages\r | |
| 781 | );\r | |
| 782 | \r | |
| 0bdc9e75 SZ |
783 | \r |
| 784 | //\r | |
| 785 | // S3 related global variable and function prototype.\r | |
| 786 | //\r | |
| 787 | \r | |
| 788 | extern BOOLEAN mSmmS3Flag;\r | |
| 789 | \r | |
| 790 | /**\r | |
| 791 | Initialize SMM S3 resume state structure used during S3 Resume.\r | |
| 792 | \r | |
| 793 | @param[in] Cr3 The base address of the page tables to use in SMM.\r | |
| 794 | \r | |
| 795 | **/\r | |
| 796 | VOID\r | |
| 797 | InitSmmS3ResumeState (\r | |
| 798 | IN UINT32 Cr3\r | |
| 799 | );\r | |
| 800 | \r | |
| 801 | /**\r | |
| 802 | Get ACPI CPU data.\r | |
| 803 | \r | |
| 804 | **/\r | |
| 805 | VOID\r | |
| 806 | GetAcpiCpuData (\r | |
| 807 | VOID\r | |
| 808 | );\r | |
| 809 | \r | |
| 810 | /**\r | |
| 811 | Restore SMM Configuration in S3 boot path.\r | |
| 812 | \r | |
| 813 | **/\r | |
| 814 | VOID\r | |
| 815 | RestoreSmmConfigurationInS3 (\r | |
| 816 | VOID\r | |
| 817 | );\r | |
| 818 | \r | |
| 529a5a86 | 819 | #endif\r |