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UefiCpuPkg: Add PiSmmCpuDxeSmm module no IA32/X64 files
[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / PiSmmCpuDxeSmm.h
CommitLineData
529a5a86
MK		 1/** @file\r
2Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.\r
3\r
4Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>\r
5This program and the accompanying materials\r
6are licensed and made available under the terms and conditions of the BSD License\r
7which accompanies this distribution. The full text of the license may be found at\r
8http://opensource.org/licenses/bsd-license.php\r
9\r
10THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/\r
14\r
15#ifndef _CPU_PISMMCPUDXESMM_H_\r
16#define _CPU_PISMMCPUDXESMM_H_\r
17\r
18#include <PiSmm.h>\r
19\r
20#include <Protocol/MpService.h>\r
21#include <Protocol/SmmConfiguration.h>\r
22#include <Protocol/SmmCpu.h>\r
23#include <Protocol/SmmAccess2.h>\r
24#include <Protocol/SmmCpuSaveState.h>\r
25#include <Protocol/SmmReadyToLock.h>\r
26#include <Protocol/SmmCpuService.h>\r
27\r
28#include <Guid/AcpiS3Context.h>\r
29\r
30#include <Library/BaseLib.h>\r
31#include <Library/IoLib.h>\r
32#include <Library/TimerLib.h>\r
33#include <Library/SmmLib.h>\r
34#include <Library/SynchronizationLib.h>\r
35#include <Library/DebugLib.h>\r
36#include <Library/BaseMemoryLib.h>\r
37#include <Library/PcdLib.h>\r
38#include <Library/CacheMaintenanceLib.h>\r
39#include <Library/MtrrLib.h>\r
40#include <Library/SmmCpuPlatformHookLib.h>\r
41#include <Library/SmmServicesTableLib.h>\r
42#include <Library/MemoryAllocationLib.h>\r
43#include <Library/UefiBootServicesTableLib.h>\r
44#include <Library/UefiRuntimeServicesTableLib.h>\r
45#include <Library/DebugAgentLib.h>\r
46#include <Library/HobLib.h>\r
47#include <Library/LocalApicLib.h>\r
48#include <Library/UefiCpuLib.h>\r
49#include <Library/CpuExceptionHandlerLib.h>\r
50#include <Library/ReportStatusCodeLib.h>\r
51#include <Library/SmmCpuFeaturesLib.h>\r
52#include <Library/PeCoffGetEntryPointLib.h>\r
53\r
54#include <AcpiCpuData.h>\r
55#include <CpuHotPlugData.h>\r
56\r
57#include <Register/Cpuid.h>\r
58\r
59#include "CpuService.h"\r
60#include "SmmProfile.h"\r
61\r
62//\r
63// MSRs required for configuration of SMM Code Access Check\r
64//\r
65#define EFI_MSR_SMM_MCA_CAP 0x17D\r
66#define SMM_CODE_ACCESS_CHK_BIT BIT58\r
67\r
68#define SMM_FEATURE_CONTROL_LOCK_BIT BIT0\r
69#define SMM_CODE_CHK_EN_BIT BIT2\r
70\r
71///\r
72/// Page Table Entry\r
73///\r
74#define IA32_PG_P BIT0\r
75#define IA32_PG_RW BIT1\r
76#define IA32_PG_WT BIT3\r
77#define IA32_PG_CD BIT4\r
78#define IA32_PG_A BIT5\r
79#define IA32_PG_PS BIT7\r
80#define IA32_PG_PAT_2M BIT12\r
81#define IA32_PG_PAT_4K IA32_PG_PS\r
82#define IA32_PG_PMNT BIT62\r
83#define IA32_PG_NX BIT63\r
84\r
85//\r
86// Size of Task-State Segment defined in IA32 Manual\r
87//\r
88#define TSS_SIZE 104\r
89#define TSS_X64_IST1_OFFSET 36\r
90#define TSS_IA32_CR3_OFFSET 28\r
91#define TSS_IA32_ESP_OFFSET 56\r
92\r
93//\r
94// Code select value\r
95//\r
96#define PROTECT_MODE_CODE_SEGMENT 0x08\r
97#define LONG_MODE_CODE_SEGMENT 0x38\r
98\r
99//\r
100// The size 0x20 must be bigger than\r
101// the size of template code of SmmInit. Currently,\r
102// the size of SmmInit requires the 0x16 Bytes buffer\r
103// at least.\r
104//\r
105#define BACK_BUF_SIZE 0x20\r
106\r
107#define EXCEPTION_VECTOR_NUMBER 0x20\r
108\r
109#define INVALID_APIC_ID 0xFFFFFFFFFFFFFFFFULL\r
110\r
111typedef UINT32 SMM_CPU_ARRIVAL_EXCEPTIONS;\r
112#define ARRIVAL_EXCEPTION_BLOCKED 0x1\r
113#define ARRIVAL_EXCEPTION_DELAYED 0x2\r
114#define ARRIVAL_EXCEPTION_SMI_DISABLED 0x4\r
115\r
116//\r
117// Private structure for the SMM CPU module that is stored in DXE Runtime memory\r
118// Contains the SMM Configuration Protocols that is produced.\r
119// Contains a mix of DXE and SMM contents. All the fields must be used properly.\r
120//\r
121#define SMM_CPU_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('s', 'c', 'p', 'u')\r
122\r
123typedef struct {\r
124 UINTN Signature;\r
125\r
126 EFI_HANDLE SmmCpuHandle;\r
127\r
128 EFI_PROCESSOR_INFORMATION *ProcessorInfo;\r
129 SMM_CPU_OPERATION *Operation;\r
130 UINTN *CpuSaveStateSize;\r
131 VOID **CpuSaveState;\r
132\r
133 EFI_SMM_RESERVED_SMRAM_REGION SmmReservedSmramRegion[1];\r
134 EFI_SMM_ENTRY_CONTEXT SmmCoreEntryContext;\r
135 EFI_SMM_ENTRY_POINT SmmCoreEntry;\r
136\r
137 EFI_SMM_CONFIGURATION_PROTOCOL SmmConfiguration;\r
138} SMM_CPU_PRIVATE_DATA;\r
139\r
140extern SMM_CPU_PRIVATE_DATA *gSmmCpuPrivate;\r
141extern CPU_HOT_PLUG_DATA mCpuHotPlugData;\r
142extern UINTN mMaxNumberOfCpus;\r
143extern UINTN mNumberOfCpus;\r
144extern BOOLEAN mRestoreSmmConfigurationInS3;\r
145extern EFI_SMM_CPU_PROTOCOL mSmmCpu;\r
146\r
147///\r
148/// The mode of the CPU at the time an SMI occurs\r
149///\r
150extern UINT8 mSmmSaveStateRegisterLma;\r
151\r
152\r
153//\r
154// SMM CPU Protocol function prototypes.\r
155//\r
156\r
157/**\r
158 Read information from the CPU save state.\r
159\r
160 @param This EFI_SMM_CPU_PROTOCOL instance\r
161 @param Width The number of bytes to read from the CPU save state.\r
162 @param Register Specifies the CPU register to read form the save state.\r
163 @param CpuIndex Specifies the zero-based index of the CPU save state\r
164 @param Buffer Upon return, this holds the CPU register value read from the save state.\r
165\r
166 @retval EFI_SUCCESS The register was read from Save State\r
167 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor\r
168 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.\r
169\r
170**/\r
171EFI_STATUS\r
172EFIAPI\r
173SmmReadSaveState (\r
174 IN CONST EFI_SMM_CPU_PROTOCOL *This,\r
175 IN UINTN Width,\r
176 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
177 IN UINTN CpuIndex,\r
178 OUT VOID *Buffer\r
179 );\r
180\r
181/**\r
182 Write data to the CPU save state.\r
183\r
184 @param This EFI_SMM_CPU_PROTOCOL instance\r
185 @param Width The number of bytes to read from the CPU save state.\r
186 @param Register Specifies the CPU register to write to the save state.\r
187 @param CpuIndex Specifies the zero-based index of the CPU save state\r
188 @param Buffer Upon entry, this holds the new CPU register value.\r
189\r
190 @retval EFI_SUCCESS The register was written from Save State\r
191 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor\r
192 @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct\r
193\r
194**/\r
195EFI_STATUS\r
196EFIAPI\r
197SmmWriteSaveState (\r
198 IN CONST EFI_SMM_CPU_PROTOCOL *This,\r
199 IN UINTN Width,\r
200 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
201 IN UINTN CpuIndex,\r
202 IN CONST VOID *Buffer\r
203 );\r
204\r
205/**\r
206Read a CPU Save State register on the target processor.\r
207\r
208This function abstracts the differences that whether the CPU Save State register is in the\r
209IA32 CPU Save State Map or X64 CPU Save State Map.\r
210\r
211This function supports reading a CPU Save State register in SMBase relocation handler.\r
212\r
213@param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r
214@param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r
215@param[in] Width The number of bytes to read from the CPU save state.\r
216@param[out] Buffer Upon return, this holds the CPU register value read from the save state.\r
217\r
218@retval EFI_SUCCESS The register was read from Save State.\r
219@retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r
220@retval EFI_INVALID_PARAMTER This or Buffer is NULL.\r
221\r
222**/\r
223EFI_STATUS\r
224EFIAPI\r
225ReadSaveStateRegister (\r
226 IN UINTN CpuIndex,\r
227 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
228 IN UINTN Width,\r
229 OUT VOID *Buffer\r
230 );\r
231\r
232/**\r
233Write value to a CPU Save State register on the target processor.\r
234\r
235This function abstracts the differences that whether the CPU Save State register is in the\r
236IA32 CPU Save State Map or X64 CPU Save State Map.\r
237\r
238This function supports writing a CPU Save State register in SMBase relocation handler.\r
239\r
240@param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r
241@param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r
242@param[in] Width The number of bytes to read from the CPU save state.\r
243@param[in] Buffer Upon entry, this holds the new CPU register value.\r
244\r
245@retval EFI_SUCCESS The register was written to Save State.\r
246@retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r
247@retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct.\r
248\r
249**/\r
250EFI_STATUS\r
251EFIAPI\r
252WriteSaveStateRegister (\r
253 IN UINTN CpuIndex,\r
254 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
255 IN UINTN Width,\r
256 IN CONST VOID *Buffer\r
257 );\r
258\r
259//\r
260//\r
261//\r
262typedef struct {\r
263 UINT32 Offset;\r
264 UINT16 Segment;\r
265 UINT16 Reserved;\r
266} IA32_FAR_ADDRESS;\r
267\r
268extern IA32_FAR_ADDRESS gSmmJmpAddr;\r
269\r
270extern CONST UINT8 gcSmmInitTemplate[];\r
271extern CONST UINT16 gcSmmInitSize;\r
272extern UINT32 gSmmCr0;\r
273extern UINT32 gSmmCr3;\r
274extern UINT32 gSmmCr4;\r
275extern UINTN gSmmInitStack;\r
276\r
277/**\r
278 Semaphore operation for all processor relocate SMMBase.\r
279**/\r
280VOID\r
281EFIAPI\r
282SmmRelocationSemaphoreComplete (\r
283 VOID\r
284 );\r
285\r
286///\r
287/// The type of SMM CPU Information\r
288///\r
289typedef struct {\r
290 SPIN_LOCK Busy;\r
291 volatile EFI_AP_PROCEDURE Procedure;\r
292 volatile VOID *Parameter;\r
293 volatile UINT32 Run;\r
294 volatile BOOLEAN Present;\r
295} SMM_CPU_DATA_BLOCK;\r
296\r
297typedef enum {\r
298 SmmCpuSyncModeTradition,\r
299 SmmCpuSyncModeRelaxedAp,\r
300 SmmCpuSyncModeMax\r
301} SMM_CPU_SYNC_MODE;\r
302\r
303typedef struct {\r
304 //\r
305 // Pointer to an array. The array should be located immediately after this structure\r
306 // so that UC cache-ability can be set together.\r
307 //\r
308 SMM_CPU_DATA_BLOCK *CpuData;\r
309 volatile UINT32 Counter;\r
310 volatile UINT32 BspIndex;\r
311 volatile BOOLEAN InsideSmm;\r
312 volatile BOOLEAN AllCpusInSync;\r
313 volatile SMM_CPU_SYNC_MODE EffectiveSyncMode;\r
314 volatile BOOLEAN SwitchBsp;\r
315 volatile BOOLEAN *CandidateBsp;\r
316} SMM_DISPATCHER_MP_SYNC_DATA;\r
317\r
318typedef struct {\r
319 SPIN_LOCK SpinLock;\r
320 UINT32 MsrIndex;\r
321} MP_MSR_LOCK;\r
322\r
323#define SMM_PSD_OFFSET 0xfb00\r
324\r
325typedef struct {\r
326 UINT64 Signature; // Offset 0x00\r
327 UINT16 Reserved1; // Offset 0x08\r
328 UINT16 Reserved2; // Offset 0x0A\r
329 UINT16 Reserved3; // Offset 0x0C\r
330 UINT16 SmmCs; // Offset 0x0E\r
331 UINT16 SmmDs; // Offset 0x10\r
332 UINT16 SmmSs; // Offset 0x12\r
333 UINT16 SmmOtherSegment; // Offset 0x14\r
334 UINT16 Reserved4; // Offset 0x16\r
335 UINT64 Reserved5; // Offset 0x18\r
336 UINT64 Reserved6; // Offset 0x20\r
337 UINT64 Reserved7; // Offset 0x28\r
338 UINT64 SmmGdtPtr; // Offset 0x30\r
339 UINT32 SmmGdtSize; // Offset 0x38\r
340 UINT32 Reserved8; // Offset 0x3C\r
341 UINT64 Reserved9; // Offset 0x40\r
342 UINT64 Reserved10; // Offset 0x48\r
343 UINT16 Reserved11; // Offset 0x50\r
344 UINT16 Reserved12; // Offset 0x52\r
345 UINT32 Reserved13; // Offset 0x54\r
346 UINT64 MtrrBaseMaskPtr; // Offset 0x58\r
347} PROCESSOR_SMM_DESCRIPTOR;\r
348\r
349extern IA32_DESCRIPTOR gcSmiGdtr;\r
350extern IA32_DESCRIPTOR gcSmiIdtr;\r
351extern VOID *gcSmiIdtrPtr;\r
352extern CONST PROCESSOR_SMM_DESCRIPTOR gcPsd;\r
353extern UINT64 gPhyMask;\r
354extern ACPI_CPU_DATA mAcpiCpuData;\r
355extern SMM_DISPATCHER_MP_SYNC_DATA *mSmmMpSyncData;\r
356extern VOID *mGdtForAp;\r
357extern VOID *mIdtForAp;\r
358extern VOID *mMachineCheckHandlerForAp;\r
359extern UINTN mSmmStackArrayBase;\r
360extern UINTN mSmmStackArrayEnd;\r
361extern UINTN mSmmStackSize;\r
362extern EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService;\r
363extern IA32_DESCRIPTOR gcSmiInitGdtr;\r
364\r
365/**\r
366 Create 4G PageTable in SMRAM.\r
367\r
368 @param ExtraPages Additional page numbers besides for 4G memory\r
369 @return PageTable Address\r
370\r
371**/\r
372UINT32\r
373Gen4GPageTable (\r
374 IN UINTN ExtraPages\r
375 );\r
376\r
377\r
378/**\r
379 Initialize global data for MP synchronization.\r
380\r
381 @param Stacks Base address of SMI stack buffer for all processors.\r
382 @param StackSize Stack size for each processor in SMM.\r
383\r
384**/\r
385UINT32\r
386InitializeMpServiceData (\r
387 IN VOID *Stacks,\r
388 IN UINTN StackSize\r
389 );\r
390\r
391/**\r
392 Initialize Timer for SMM AP Sync.\r
393\r
394**/\r
395VOID\r
396InitializeSmmTimer (\r
397 VOID\r
398 );\r
399\r
400/**\r
401 Start Timer for SMM AP Sync.\r
402\r
403**/\r
404UINT64\r
405EFIAPI\r
406StartSyncTimer (\r
407 VOID\r
408 );\r
409\r
410/**\r
411 Check if the SMM AP Sync timer is timeout.\r
412\r
413 @param Timer The start timer from the begin.\r
414\r
415**/\r
416BOOLEAN\r
417EFIAPI\r
418IsSyncTimerTimeout (\r
419 IN UINT64 Timer\r
420 );\r
421\r
422/**\r
423 Initialize IDT for SMM Stack Guard.\r
424\r
425**/\r
426VOID\r
427EFIAPI\r
428InitializeIDTSmmStackGuard (\r
429 VOID\r
430 );\r
431\r
432/**\r
433\r
434 Register the SMM Foundation entry point.\r
435\r
436 @param This Pointer to EFI_SMM_CONFIGURATION_PROTOCOL instance\r
437 @param SmmEntryPoint SMM Foundation EntryPoint\r
438\r
439 @retval EFI_SUCCESS Successfully to register SMM foundation entry point\r
440\r
441**/\r
442EFI_STATUS\r
443EFIAPI\r
444RegisterSmmEntry (\r
445 IN CONST EFI_SMM_CONFIGURATION_PROTOCOL *This,\r
446 IN EFI_SMM_ENTRY_POINT SmmEntryPoint\r
447 );\r
448\r
449/**\r
450 Create PageTable for SMM use.\r
451\r
452 @return PageTable Address\r
453\r
454**/\r
455UINT32\r
456SmmInitPageTable (\r
457 VOID\r
458 );\r
459\r
460/**\r
461 Schedule a procedure to run on the specified CPU.\r
462\r
463 @param Procedure The address of the procedure to run\r
464 @param CpuIndex Target CPU number\r
465 @param ProcArguments The parameter to pass to the procedure\r
466\r
467 @retval EFI_INVALID_PARAMETER CpuNumber not valid\r
468 @retval EFI_INVALID_PARAMETER CpuNumber specifying BSP\r
469 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM\r
470 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy\r
471 @retval EFI_SUCCESS - The procedure has been successfully scheduled\r
472\r
473**/\r
474EFI_STATUS\r
475EFIAPI\r
476SmmStartupThisAp (\r
477 IN EFI_AP_PROCEDURE Procedure,\r
478 IN UINTN CpuIndex,\r
479 IN OUT VOID *ProcArguments OPTIONAL\r
480 );\r
481\r
482/**\r
483 Schedule a procedure to run on the specified CPU in a blocking fashion.\r
484\r
485 @param Procedure The address of the procedure to run\r
486 @param CpuIndex Target CPU Index\r
487 @param ProcArguments The parameter to pass to the procedure\r
488\r
489 @retval EFI_INVALID_PARAMETER CpuNumber not valid\r
490 @retval EFI_INVALID_PARAMETER CpuNumber specifying BSP\r
491 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM\r
492 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy\r
493 @retval EFI_SUCCESS The procedure has been successfully scheduled\r
494\r
495**/\r
496EFI_STATUS\r
497EFIAPI\r
498SmmBlockingStartupThisAp (\r
499 IN EFI_AP_PROCEDURE Procedure,\r
500 IN UINTN CpuIndex,\r
501 IN OUT VOID *ProcArguments OPTIONAL\r
502 );\r
503\r
504/**\r
505 Initialize MP synchronization data.\r
506\r
507**/\r
508VOID\r
509EFIAPI\r
510InitializeMpSyncData (\r
511 VOID\r
512 );\r
513\r
514/**\r
515\r
516 Find out SMRAM information including SMRR base and SMRR size.\r
517\r
518 @param SmrrBase SMRR base\r
519 @param SmrrSize SMRR size\r
520\r
521**/\r
522VOID\r
523FindSmramInfo (\r
524 OUT UINT32 *SmrrBase,\r
525 OUT UINT32 *SmrrSize\r
526 );\r
527\r
528/**\r
529 The function is invoked before SMBASE relocation in S3 path to restores CPU status.\r
530\r
531 The function is invoked before SMBASE relocation in S3 path. It does first time microcode load\r
532 and restores MTRRs for both BSP and APs.\r
533\r
534**/\r
535VOID\r
536EarlyInitializeCpu (\r
537 VOID\r
538 );\r
539\r
540/**\r
541 The function is invoked after SMBASE relocation in S3 path to restores CPU status.\r
542\r
543 The function is invoked after SMBASE relocation in S3 path. It restores configuration according to\r
544 data saved by normal boot path for both BSP and APs.\r
545\r
546**/\r
547VOID\r
548InitializeCpu (\r
549 VOID\r
550 );\r
551\r
552/**\r
553 Page Fault handler for SMM use.\r
554\r
555 @param InterruptType Defines the type of interrupt or exception that\r
556 occurred on the processor.This parameter is processor architecture specific.\r
557 @param SystemContext A pointer to the processor context when\r
558 the interrupt occurred on the processor.\r
559**/\r
560VOID\r
561EFIAPI\r
562SmiPFHandler (\r
563 IN EFI_EXCEPTION_TYPE InterruptType,\r
564 IN EFI_SYSTEM_CONTEXT SystemContext\r
565 );\r
566\r
567/**\r
568 Perform the remaining tasks.\r
569\r
570**/\r
571VOID\r
572PerformRemainingTasks (\r
573 VOID\r
574 );\r
575\r
576/**\r
577 Initialize MSR spin lock by MSR index.\r
578\r
579 @param MsrIndex MSR index value.\r
580\r
581**/\r
582VOID\r
583InitMsrSpinLockByIndex (\r
584 IN UINT32 MsrIndex\r
585 );\r
586\r
587/**\r
588 Hook return address of SMM Save State so that semaphore code\r
589 can be executed immediately after AP exits SMM to indicate to\r
590 the BSP that an AP has exited SMM after SMBASE relocation.\r
591\r
592 @param[in] CpuIndex The processor index.\r
593 @param[in] RebasedFlag A pointer to a flag that is set to TRUE\r
594 immediately after AP exits SMM.\r
595\r
596**/\r
597VOID\r
598SemaphoreHook (\r
599 IN UINTN CpuIndex,\r
600 IN volatile BOOLEAN *RebasedFlag\r
601 );\r
602\r
603/**\r
604Configure SMM Code Access Check feature for all processors.\r
605SMM Feature Control MSR will be locked after configuration.\r
606**/\r
607VOID\r
608ConfigSmmCodeAccessCheck (\r
609 VOID\r
610 );\r
611\r
612/**\r
613 Hook the code executed immediately after an RSM instruction on the currently\r
614 executing CPU. The mode of code executed immediately after RSM must be\r
615 detected, and the appropriate hook must be selected. Always clear the auto\r
616 HALT restart flag if it is set.\r
617\r
618 @param[in] CpuIndex The processor index for the currently\r
619 executing CPU.\r
620 @param[in] CpuState Pointer to SMRAM Save State Map for the\r
621 currently executing CPU.\r
622 @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to\r
623 32-bit mode from 64-bit SMM.\r
624 @param[in] NewInstructionPointer Instruction pointer to use if resuming to\r
625 same mode as SMM.\r
626\r
627 @retval The value of the original instruction pointer before it was hooked.\r
628\r
629**/\r
630UINT64\r
631EFIAPI\r
632HookReturnFromSmm (\r
633 IN UINTN CpuIndex,\r
634 SMRAM_SAVE_STATE_MAP *CpuState,\r
635 UINT64 NewInstructionPointer32,\r
636 UINT64 NewInstructionPointer\r
637 );\r
638\r
639/**\r
640 Get the size of the SMI Handler in bytes.\r
641\r
642 @retval The size, in bytes, of the SMI Handler.\r
643\r
644**/\r
645UINTN\r
646EFIAPI\r
647GetSmiHandlerSize (\r
648 VOID\r
649 );\r
650\r
651/**\r
652 Install the SMI handler for the CPU specified by CpuIndex. This function\r
653 is called by the CPU that was elected as monarch during System Management\r
654 Mode initialization.\r
655\r
656 @param[in] CpuIndex The index of the CPU to install the custom SMI handler.\r
657 The value must be between 0 and the NumberOfCpus field\r
658 in the System Management System Table (SMST).\r
659 @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.\r
660 @param[in] SmiStack The stack to use when an SMI is processed by the\r
661 the CPU specified by CpuIndex.\r
662 @param[in] StackSize The size, in bytes, if the stack used when an SMI is\r
663 processed by the CPU specified by CpuIndex.\r
664 @param[in] GdtBase The base address of the GDT to use when an SMI is\r
665 processed by the CPU specified by CpuIndex.\r
666 @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is\r
667 processed by the CPU specified by CpuIndex.\r
668 @param[in] IdtBase The base address of the IDT to use when an SMI is\r
669 processed by the CPU specified by CpuIndex.\r
670 @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is\r
671 processed by the CPU specified by CpuIndex.\r
672 @param[in] Cr3 The base address of the page tables to use when an SMI\r
673 is processed by the CPU specified by CpuIndex.\r
674**/\r
675VOID\r
676EFIAPI\r
677InstallSmiHandler (\r
678 IN UINTN CpuIndex,\r
679 IN UINT32 SmBase,\r
680 IN VOID *SmiStack,\r
681 IN UINTN StackSize,\r
682 IN UINTN GdtBase,\r
683 IN UINTN GdtSize,\r
684 IN UINTN IdtBase,\r
685 IN UINTN IdtSize,\r
686 IN UINT32 Cr3\r
687 );\r
688\r
689/**\r
690 Search module name by input IP address and output it.\r
691\r
692 @param CallerIpAddress Caller instruction pointer.\r
693\r
694**/\r
695VOID\r
696DumpModuleInfoByIp (\r
697 IN UINTN CallerIpAddress\r
698 );\r
699#endif\r
EFI Development Kit II mirror for PVE