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UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmmCr3" with PatchInstructionX86()
[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / PiSmmCpuDxeSmm.h
CommitLineData
529a5a86
MK		 1/** @file\r
2Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.\r
3\r
6e601a41 4Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
241f9149
LD		 5Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
6\r
529a5a86
MK		 7This program and the accompanying materials\r
8are licensed and made available under the terms and conditions of the BSD License\r
9which accompanies this distribution. The full text of the license may be found at\r
10http://opensource.org/licenses/bsd-license.php\r
11\r
12THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14\r
15**/\r
16\r
17#ifndef _CPU_PISMMCPUDXESMM_H_\r
18#define _CPU_PISMMCPUDXESMM_H_\r
19\r
20#include <PiSmm.h>\r
21\r
22#include <Protocol/MpService.h>\r
23#include <Protocol/SmmConfiguration.h>\r
24#include <Protocol/SmmCpu.h>\r
25#include <Protocol/SmmAccess2.h>\r
529a5a86
MK		 26#include <Protocol/SmmReadyToLock.h>\r
27#include <Protocol/SmmCpuService.h>\r
827330cc 28#include <Protocol/SmmMemoryAttribute.h>\r
529a5a86
MK		 29\r
30#include <Guid/AcpiS3Context.h>\r
717fb604 31#include <Guid/PiSmmMemoryAttributesTable.h>\r
529a5a86
MK		 32\r
33#include <Library/BaseLib.h>\r
34#include <Library/IoLib.h>\r
35#include <Library/TimerLib.h>\r
529a5a86
MK		 36#include <Library/SynchronizationLib.h>\r
37#include <Library/DebugLib.h>\r
38#include <Library/BaseMemoryLib.h>\r
39#include <Library/PcdLib.h>\r
40#include <Library/CacheMaintenanceLib.h>\r
41#include <Library/MtrrLib.h>\r
42#include <Library/SmmCpuPlatformHookLib.h>\r
43#include <Library/SmmServicesTableLib.h>\r
44#include <Library/MemoryAllocationLib.h>\r
45#include <Library/UefiBootServicesTableLib.h>\r
46#include <Library/UefiRuntimeServicesTableLib.h>\r
47#include <Library/DebugAgentLib.h>\r
48#include <Library/HobLib.h>\r
49#include <Library/LocalApicLib.h>\r
50#include <Library/UefiCpuLib.h>\r
51#include <Library/CpuExceptionHandlerLib.h>\r
52#include <Library/ReportStatusCodeLib.h>\r
53#include <Library/SmmCpuFeaturesLib.h>\r
54#include <Library/PeCoffGetEntryPointLib.h>\r
55\r
56#include <AcpiCpuData.h>\r
57#include <CpuHotPlugData.h>\r
58\r
59#include <Register/Cpuid.h>\r
f85d3ce2 60#include <Register/Msr.h>\r
529a5a86
MK		 61\r
62#include "CpuService.h"\r
63#include "SmmProfile.h"\r
64\r
65//\r
66// MSRs required for configuration of SMM Code Access Check\r
67//\r
68#define EFI_MSR_SMM_MCA_CAP 0x17D\r
69#define SMM_CODE_ACCESS_CHK_BIT BIT58\r
70\r
71#define SMM_FEATURE_CONTROL_LOCK_BIT BIT0\r
72#define SMM_CODE_CHK_EN_BIT BIT2\r
73\r
74///\r
75/// Page Table Entry\r
76///\r
77#define IA32_PG_P BIT0\r
78#define IA32_PG_RW BIT1\r
881520ea 79#define IA32_PG_U BIT2\r
529a5a86
MK		 80#define IA32_PG_WT BIT3\r
81#define IA32_PG_CD BIT4\r
82#define IA32_PG_A BIT5\r
881520ea 83#define IA32_PG_D BIT6\r
529a5a86
MK		 84#define IA32_PG_PS BIT7\r
85#define IA32_PG_PAT_2M BIT12\r
86#define IA32_PG_PAT_4K IA32_PG_PS\r
87#define IA32_PG_PMNT BIT62\r
88#define IA32_PG_NX BIT63\r
89\r
717fb604 90#define PAGE_ATTRIBUTE_BITS (IA32_PG_D | IA32_PG_A | IA32_PG_U | IA32_PG_RW | IA32_PG_P)\r
881520ea
JY		 91//\r
92// Bits 1, 2, 5, 6 are reserved in the IA32 PAE PDPTE\r
93// X64 PAE PDPTE does not have such restriction\r
94//\r
95#define IA32_PAE_PDPTE_ATTRIBUTE_BITS (IA32_PG_P)\r
96\r
717fb604
JY		 97#define PAGE_PROGATE_BITS (IA32_PG_NX | PAGE_ATTRIBUTE_BITS)\r
98\r
99#define PAGING_4K_MASK 0xFFF\r
100#define PAGING_2M_MASK 0x1FFFFF\r
101#define PAGING_1G_MASK 0x3FFFFFFF\r
102\r
103#define PAGING_PAE_INDEX_MASK 0x1FF\r
104\r
105#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull\r
106#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull\r
107#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull\r
108\r
7ed6f781
JF		 109#define SMRR_MAX_ADDRESS BASE_4GB\r
110\r
717fb604
JY		 111typedef enum {\r
112 PageNone,\r
113 Page4K,\r
114 Page2M,\r
115 Page1G,\r
116} PAGE_ATTRIBUTE;\r
117\r
118typedef struct {\r
119 PAGE_ATTRIBUTE Attribute;\r
120 UINT64 Length;\r
121 UINT64 AddressMask;\r
122} PAGE_ATTRIBUTE_TABLE;\r
123\r
529a5a86
MK		 124//\r
125// Size of Task-State Segment defined in IA32 Manual\r
126//\r
127#define TSS_SIZE 104\r
128#define TSS_X64_IST1_OFFSET 36\r
129#define TSS_IA32_CR3_OFFSET 28\r
130#define TSS_IA32_ESP_OFFSET 56\r
131\r
717fb604
JY		 132#define CR0_WP BIT16\r
133\r
529a5a86
MK		 134//\r
135// Code select value\r
136//\r
137#define PROTECT_MODE_CODE_SEGMENT 0x08\r
138#define LONG_MODE_CODE_SEGMENT 0x38\r
139\r
140//\r
141// The size 0x20 must be bigger than\r
142// the size of template code of SmmInit. Currently,\r
143// the size of SmmInit requires the 0x16 Bytes buffer\r
144// at least.\r
145//\r
146#define BACK_BUF_SIZE 0x20\r
147\r
148#define EXCEPTION_VECTOR_NUMBER 0x20\r
149\r
150#define INVALID_APIC_ID 0xFFFFFFFFFFFFFFFFULL\r
151\r
152typedef UINT32 SMM_CPU_ARRIVAL_EXCEPTIONS;\r
153#define ARRIVAL_EXCEPTION_BLOCKED 0x1\r
154#define ARRIVAL_EXCEPTION_DELAYED 0x2\r
155#define ARRIVAL_EXCEPTION_SMI_DISABLED 0x4\r
156\r
157//\r
158// Private structure for the SMM CPU module that is stored in DXE Runtime memory\r
159// Contains the SMM Configuration Protocols that is produced.\r
160// Contains a mix of DXE and SMM contents. All the fields must be used properly.\r
161//\r
162#define SMM_CPU_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('s', 'c', 'p', 'u')\r
163\r
164typedef struct {\r
165 UINTN Signature;\r
166\r
167 EFI_HANDLE SmmCpuHandle;\r
168\r
169 EFI_PROCESSOR_INFORMATION *ProcessorInfo;\r
170 SMM_CPU_OPERATION *Operation;\r
171 UINTN *CpuSaveStateSize;\r
172 VOID **CpuSaveState;\r
173\r
174 EFI_SMM_RESERVED_SMRAM_REGION SmmReservedSmramRegion[1];\r
175 EFI_SMM_ENTRY_CONTEXT SmmCoreEntryContext;\r
176 EFI_SMM_ENTRY_POINT SmmCoreEntry;\r
177\r
178 EFI_SMM_CONFIGURATION_PROTOCOL SmmConfiguration;\r
179} SMM_CPU_PRIVATE_DATA;\r
180\r
181extern SMM_CPU_PRIVATE_DATA *gSmmCpuPrivate;\r
182extern CPU_HOT_PLUG_DATA mCpuHotPlugData;\r
183extern UINTN mMaxNumberOfCpus;\r
184extern UINTN mNumberOfCpus;\r
529a5a86
MK		 185extern EFI_SMM_CPU_PROTOCOL mSmmCpu;\r
186\r
187///\r
188/// The mode of the CPU at the time an SMI occurs\r
189///\r
190extern UINT8 mSmmSaveStateRegisterLma;\r
191\r
529a5a86
MK		 192//\r
193// SMM CPU Protocol function prototypes.\r
194//\r
195\r
196/**\r
197 Read information from the CPU save state.\r
198\r
199 @param This EFI_SMM_CPU_PROTOCOL instance\r
200 @param Width The number of bytes to read from the CPU save state.\r
201 @param Register Specifies the CPU register to read form the save state.\r
202 @param CpuIndex Specifies the zero-based index of the CPU save state\r
203 @param Buffer Upon return, this holds the CPU register value read from the save state.\r
204\r
205 @retval EFI_SUCCESS The register was read from Save State\r
206 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor\r
207 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.\r
208\r
209**/\r
210EFI_STATUS\r
211EFIAPI\r
212SmmReadSaveState (\r
213 IN CONST EFI_SMM_CPU_PROTOCOL *This,\r
214 IN UINTN Width,\r
215 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
216 IN UINTN CpuIndex,\r
217 OUT VOID *Buffer\r
218 );\r
219\r
220/**\r
221 Write data to the CPU save state.\r
222\r
223 @param This EFI_SMM_CPU_PROTOCOL instance\r
224 @param Width The number of bytes to read from the CPU save state.\r
225 @param Register Specifies the CPU register to write to the save state.\r
226 @param CpuIndex Specifies the zero-based index of the CPU save state\r
227 @param Buffer Upon entry, this holds the new CPU register value.\r
228\r
229 @retval EFI_SUCCESS The register was written from Save State\r
230 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor\r
231 @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct\r
232\r
233**/\r
234EFI_STATUS\r
235EFIAPI\r
236SmmWriteSaveState (\r
237 IN CONST EFI_SMM_CPU_PROTOCOL *This,\r
238 IN UINTN Width,\r
239 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
240 IN UINTN CpuIndex,\r
241 IN CONST VOID *Buffer\r
242 );\r
243\r
244/**\r
245Read a CPU Save State register on the target processor.\r
246\r
247This function abstracts the differences that whether the CPU Save State register is in the\r
248IA32 CPU Save State Map or X64 CPU Save State Map.\r
249\r
250This function supports reading a CPU Save State register in SMBase relocation handler.\r
251\r
252@param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r
253@param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r
254@param[in] Width The number of bytes to read from the CPU save state.\r
255@param[out] Buffer Upon return, this holds the CPU register value read from the save state.\r
256\r
257@retval EFI_SUCCESS The register was read from Save State.\r
258@retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r
259@retval EFI_INVALID_PARAMTER This or Buffer is NULL.\r
260\r
261**/\r
262EFI_STATUS\r
263EFIAPI\r
264ReadSaveStateRegister (\r
265 IN UINTN CpuIndex,\r
266 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
267 IN UINTN Width,\r
268 OUT VOID *Buffer\r
269 );\r
270\r
271/**\r
272Write value to a CPU Save State register on the target processor.\r
273\r
274This function abstracts the differences that whether the CPU Save State register is in the\r
275IA32 CPU Save State Map or X64 CPU Save State Map.\r
276\r
277This function supports writing a CPU Save State register in SMBase relocation handler.\r
278\r
279@param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r
280@param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r
281@param[in] Width The number of bytes to read from the CPU save state.\r
282@param[in] Buffer Upon entry, this holds the new CPU register value.\r
283\r
284@retval EFI_SUCCESS The register was written to Save State.\r
285@retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r
286@retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct.\r
287\r
288**/\r
289EFI_STATUS\r
290EFIAPI\r
291WriteSaveStateRegister (\r
292 IN UINTN CpuIndex,\r
293 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
294 IN UINTN Width,\r
295 IN CONST VOID *Buffer\r
296 );\r
297\r
298//\r
299//\r
300//\r
301typedef struct {\r
302 UINT32 Offset;\r
303 UINT16 Segment;\r
304 UINT16 Reserved;\r
305} IA32_FAR_ADDRESS;\r
306\r
307extern IA32_FAR_ADDRESS gSmmJmpAddr;\r
308\r
309extern CONST UINT8 gcSmmInitTemplate[];\r
310extern CONST UINT16 gcSmmInitSize;\r
311extern UINT32 gSmmCr0;\r
6b0841c1 312X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr3;\r
529a5a86
MK		 313extern UINT32 gSmmCr4;\r
314extern UINTN gSmmInitStack;\r
315\r
316/**\r
317 Semaphore operation for all processor relocate SMMBase.\r
318**/\r
319VOID\r
320EFIAPI\r
321SmmRelocationSemaphoreComplete (\r
322 VOID\r
323 );\r
324\r
325///\r
326/// The type of SMM CPU Information\r
327///\r
328typedef struct {\r
ed3d5ecb 329 SPIN_LOCK *Busy;\r
529a5a86
MK		 330 volatile EFI_AP_PROCEDURE Procedure;\r
331 volatile VOID *Parameter;\r
ed3d5ecb
JF		 332 volatile UINT32 *Run;\r
333 volatile BOOLEAN *Present;\r
529a5a86
MK		 334} SMM_CPU_DATA_BLOCK;\r
335\r
336typedef enum {\r
337 SmmCpuSyncModeTradition,\r
338 SmmCpuSyncModeRelaxedAp,\r
339 SmmCpuSyncModeMax\r
340} SMM_CPU_SYNC_MODE;\r
341\r
342typedef struct {\r
343 //\r
344 // Pointer to an array. The array should be located immediately after this structure\r
345 // so that UC cache-ability can be set together.\r
346 //\r
347 SMM_CPU_DATA_BLOCK *CpuData;\r
fe3a75bc 348 volatile UINT32 *Counter;\r
529a5a86 349 volatile UINT32 BspIndex;\r
fe3a75bc
JF		 350 volatile BOOLEAN *InsideSmm;\r
351 volatile BOOLEAN *AllCpusInSync;\r
529a5a86
MK		 352 volatile SMM_CPU_SYNC_MODE EffectiveSyncMode;\r
353 volatile BOOLEAN SwitchBsp;\r
354 volatile BOOLEAN *CandidateBsp;\r
355} SMM_DISPATCHER_MP_SYNC_DATA;\r
356\r
695e62d1
JF		 357#define MSR_SPIN_LOCK_INIT_NUM 15\r
358\r
529a5a86 359typedef struct {\r
dc99315b 360 SPIN_LOCK *SpinLock;\r
529a5a86
MK		 361 UINT32 MsrIndex;\r
362} MP_MSR_LOCK;\r
363\r
364#define SMM_PSD_OFFSET 0xfb00\r
365\r
1d648531
JF		 366///\r
367/// All global semaphores' pointer\r
368///\r
369typedef struct {\r
370 volatile UINT32 *Counter;\r
371 volatile BOOLEAN *InsideSmm;\r
372 volatile BOOLEAN *AllCpusInSync;\r
373 SPIN_LOCK *PFLock;\r
374 SPIN_LOCK *CodeAccessCheckLock;\r
6c4c15fa 375 SPIN_LOCK *MemoryMappedLock;\r
1d648531
JF		 376} SMM_CPU_SEMAPHORE_GLOBAL;\r
377\r
4e920581
JF		 378///\r
379/// All semaphores for each processor\r
380///\r
381typedef struct {\r
382 SPIN_LOCK *Busy;\r
383 volatile UINT32 *Run;\r
384 volatile BOOLEAN *Present;\r
385} SMM_CPU_SEMAPHORE_CPU;\r
386\r
695e62d1
JF		 387///\r
388/// All MSRs semaphores' pointer and counter\r
389///\r
390typedef struct {\r
391 SPIN_LOCK *Msr;\r
392 UINTN AvailableCounter;\r
393} SMM_CPU_SEMAPHORE_MSR;\r
4e920581 394\r
1d648531
JF		 395///\r
396/// All semaphores' information\r
397///\r
398typedef struct {\r
399 SMM_CPU_SEMAPHORE_GLOBAL SemaphoreGlobal;\r
4e920581 400 SMM_CPU_SEMAPHORE_CPU SemaphoreCpu;\r
695e62d1 401 SMM_CPU_SEMAPHORE_MSR SemaphoreMsr;\r
1d648531
JF		 402} SMM_CPU_SEMAPHORES;\r
403\r
529a5a86 404extern IA32_DESCRIPTOR gcSmiGdtr;\r
717fb604
JY		 405extern EFI_PHYSICAL_ADDRESS mGdtBuffer;\r
406extern UINTN mGdtBufferSize;\r
529a5a86
MK		 407extern IA32_DESCRIPTOR gcSmiIdtr;\r
408extern VOID *gcSmiIdtrPtr;\r
529a5a86 409extern UINT64 gPhyMask;\r
529a5a86 410extern SMM_DISPATCHER_MP_SYNC_DATA *mSmmMpSyncData;\r
529a5a86
MK		 411extern UINTN mSmmStackArrayBase;\r
412extern UINTN mSmmStackArrayEnd;\r
413extern UINTN mSmmStackSize;\r
414extern EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService;\r
415extern IA32_DESCRIPTOR gcSmiInitGdtr;\r
dc99315b
JF		 416extern SMM_CPU_SEMAPHORES mSmmCpuSemaphores;\r
417extern UINTN mSemaphoreSize;\r
fe3a75bc
JF		 418extern SPIN_LOCK *mPFLock;\r
419extern SPIN_LOCK *mConfigSmmCodeAccessCheckLock;\r
6c4c15fa 420extern SPIN_LOCK *mMemoryMappedLock;\r
7ed6f781
JF		 421extern EFI_SMRAM_DESCRIPTOR *mSmmCpuSmramRanges;\r
422extern UINTN mSmmCpuSmramRangeCount;\r
714c2603 423extern UINT8 mPhysicalAddressBits;\r
529a5a86 424\r
241f9149
LD		 425//\r
426// Copy of the PcdPteMemoryEncryptionAddressOrMask\r
427//\r
428extern UINT64 mAddressEncMask;\r
429\r
529a5a86
MK		 430/**\r
431 Create 4G PageTable in SMRAM.\r
432\r
717fb604 433 @param[in] Is32BitPageTable Whether the page table is 32-bit PAE\r
529a5a86
MK		 434 @return PageTable Address\r
435\r
436**/\r
437UINT32\r
438Gen4GPageTable (\r
881520ea 439 IN BOOLEAN Is32BitPageTable\r
529a5a86
MK		 440 );\r
441\r
442\r
443/**\r
444 Initialize global data for MP synchronization.\r
445\r
446 @param Stacks Base address of SMI stack buffer for all processors.\r
447 @param StackSize Stack size for each processor in SMM.\r
448\r
449**/\r
450UINT32\r
451InitializeMpServiceData (\r
452 IN VOID *Stacks,\r
453 IN UINTN StackSize\r
454 );\r
455\r
456/**\r
457 Initialize Timer for SMM AP Sync.\r
458\r
459**/\r
460VOID\r
461InitializeSmmTimer (\r
462 VOID\r
463 );\r
464\r
465/**\r
466 Start Timer for SMM AP Sync.\r
467\r
468**/\r
469UINT64\r
470EFIAPI\r
471StartSyncTimer (\r
472 VOID\r
473 );\r
474\r
475/**\r
476 Check if the SMM AP Sync timer is timeout.\r
477\r
478 @param Timer The start timer from the begin.\r
479\r
480**/\r
481BOOLEAN\r
482EFIAPI\r
483IsSyncTimerTimeout (\r
484 IN UINT64 Timer\r
485 );\r
486\r
487/**\r
488 Initialize IDT for SMM Stack Guard.\r
489\r
490**/\r
491VOID\r
492EFIAPI\r
493InitializeIDTSmmStackGuard (\r
494 VOID\r
495 );\r
496\r
fe5f1949
JY		 497/**\r
498 Initialize Gdt for all processors.\r
717fb604 499\r
fe5f1949
JY		 500 @param[in] Cr3 CR3 value.\r
501 @param[out] GdtStepSize The step size for GDT table.\r
502\r
503 @return GdtBase for processor 0.\r
504 GdtBase for processor X is: GdtBase + (GdtStepSize * X)\r
505**/\r
506VOID *\r
507InitGdt (\r
508 IN UINTN Cr3,\r
509 OUT UINTN *GdtStepSize\r
510 );\r
511\r
529a5a86
MK		 512/**\r
513\r
514 Register the SMM Foundation entry point.\r
515\r
516 @param This Pointer to EFI_SMM_CONFIGURATION_PROTOCOL instance\r
517 @param SmmEntryPoint SMM Foundation EntryPoint\r
518\r
519 @retval EFI_SUCCESS Successfully to register SMM foundation entry point\r
520\r
521**/\r
522EFI_STATUS\r
523EFIAPI\r
524RegisterSmmEntry (\r
525 IN CONST EFI_SMM_CONFIGURATION_PROTOCOL *This,\r
526 IN EFI_SMM_ENTRY_POINT SmmEntryPoint\r
527 );\r
528\r
529/**\r
530 Create PageTable for SMM use.\r
531\r
532 @return PageTable Address\r
533\r
534**/\r
535UINT32\r
536SmmInitPageTable (\r
537 VOID\r
538 );\r
539\r
540/**\r
541 Schedule a procedure to run on the specified CPU.\r
542\r
543 @param Procedure The address of the procedure to run\r
544 @param CpuIndex Target CPU number\r
545 @param ProcArguments The parameter to pass to the procedure\r
546\r
547 @retval EFI_INVALID_PARAMETER CpuNumber not valid\r
548 @retval EFI_INVALID_PARAMETER CpuNumber specifying BSP\r
549 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM\r
550 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy\r
551 @retval EFI_SUCCESS - The procedure has been successfully scheduled\r
552\r
553**/\r
554EFI_STATUS\r
555EFIAPI\r
556SmmStartupThisAp (\r
557 IN EFI_AP_PROCEDURE Procedure,\r
558 IN UINTN CpuIndex,\r
559 IN OUT VOID *ProcArguments OPTIONAL\r
560 );\r
561\r
562/**\r
563 Schedule a procedure to run on the specified CPU in a blocking fashion.\r
564\r
565 @param Procedure The address of the procedure to run\r
566 @param CpuIndex Target CPU Index\r
567 @param ProcArguments The parameter to pass to the procedure\r
568\r
569 @retval EFI_INVALID_PARAMETER CpuNumber not valid\r
570 @retval EFI_INVALID_PARAMETER CpuNumber specifying BSP\r
571 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM\r
572 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy\r
573 @retval EFI_SUCCESS The procedure has been successfully scheduled\r
574\r
575**/\r
576EFI_STATUS\r
577EFIAPI\r
578SmmBlockingStartupThisAp (\r
579 IN EFI_AP_PROCEDURE Procedure,\r
580 IN UINTN CpuIndex,\r
581 IN OUT VOID *ProcArguments OPTIONAL\r
582 );\r
583\r
e4435f71
JY		 584/**\r
585 This function sets the attributes for the memory region specified by BaseAddress and\r
586 Length from their current attributes to the attributes specified by Attributes.\r
587\r
588 @param[in] BaseAddress The physical address that is the start address of a memory region.\r
589 @param[in] Length The size in bytes of the memory region.\r
590 @param[in] Attributes The bit mask of attributes to set for the memory region.\r
591\r
592 @retval EFI_SUCCESS The attributes were set for the memory region.\r
593 @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r
594 BaseAddress and Length cannot be modified.\r
595 @retval EFI_INVALID_PARAMETER Length is zero.\r
596 Attributes specified an illegal combination of attributes that\r
597 cannot be set together.\r
598 @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r
599 the memory resource range.\r
600 @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r
601 resource range specified by BaseAddress and Length.\r
602 The bit mask of attributes is not support for the memory resource\r
603 range specified by BaseAddress and Length.\r
604\r
605**/\r
606EFI_STATUS\r
607EFIAPI\r
608SmmSetMemoryAttributes (\r
609 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
610 IN UINT64 Length,\r
611 IN UINT64 Attributes\r
612 );\r
613\r
614/**\r
615 This function clears the attributes for the memory region specified by BaseAddress and\r
616 Length from their current attributes to the attributes specified by Attributes.\r
617\r
618 @param[in] BaseAddress The physical address that is the start address of a memory region.\r
619 @param[in] Length The size in bytes of the memory region.\r
620 @param[in] Attributes The bit mask of attributes to clear for the memory region.\r
621\r
622 @retval EFI_SUCCESS The attributes were cleared for the memory region.\r
623 @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r
624 BaseAddress and Length cannot be modified.\r
625 @retval EFI_INVALID_PARAMETER Length is zero.\r
626 Attributes specified an illegal combination of attributes that\r
627 cannot be set together.\r
628 @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r
629 the memory resource range.\r
630 @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r
631 resource range specified by BaseAddress and Length.\r
632 The bit mask of attributes is not support for the memory resource\r
633 range specified by BaseAddress and Length.\r
634\r
635**/\r
636EFI_STATUS\r
637EFIAPI\r
638SmmClearMemoryAttributes (\r
639 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
640 IN UINT64 Length,\r
641 IN UINT64 Attributes\r
642 );\r
643\r
529a5a86
MK		 644/**\r
645 Initialize MP synchronization data.\r
646\r
647**/\r
648VOID\r
649EFIAPI\r
650InitializeMpSyncData (\r
651 VOID\r
652 );\r
653\r
654/**\r
655\r
656 Find out SMRAM information including SMRR base and SMRR size.\r
657\r
658 @param SmrrBase SMRR base\r
659 @param SmrrSize SMRR size\r
660\r
661**/\r
662VOID\r
663FindSmramInfo (\r
664 OUT UINT32 *SmrrBase,\r
665 OUT UINT32 *SmrrSize\r
666 );\r
667\r
668/**\r
0bdc9e75 669 Relocate SmmBases for each processor.\r
529a5a86 670\r
0bdc9e75 671 Execute on first boot and all S3 resumes\r
529a5a86
MK		 672\r
673**/\r
674VOID\r
0bdc9e75
SZ		 675EFIAPI\r
676SmmRelocateBases (\r
529a5a86
MK		 677 VOID\r
678 );\r
679\r
680/**\r
681 Page Fault handler for SMM use.\r
682\r
683 @param InterruptType Defines the type of interrupt or exception that\r
684 occurred on the processor.This parameter is processor architecture specific.\r
685 @param SystemContext A pointer to the processor context when\r
686 the interrupt occurred on the processor.\r
687**/\r
688VOID\r
689EFIAPI\r
690SmiPFHandler (\r
b8caae19
JF		 691 IN EFI_EXCEPTION_TYPE InterruptType,\r
692 IN EFI_SYSTEM_CONTEXT SystemContext\r
529a5a86
MK		 693 );\r
694\r
695/**\r
696 Perform the remaining tasks.\r
697\r
698**/\r
699VOID\r
700PerformRemainingTasks (\r
701 VOID\r
702 );\r
703\r
9f419739
JY		 704/**\r
705 Perform the pre tasks.\r
706\r
707**/\r
708VOID\r
709PerformPreTasks (\r
710 VOID\r
711 );\r
712\r
529a5a86
MK		 713/**\r
714 Initialize MSR spin lock by MSR index.\r
715\r
716 @param MsrIndex MSR index value.\r
717\r
718**/\r
719VOID\r
720InitMsrSpinLockByIndex (\r
721 IN UINT32 MsrIndex\r
722 );\r
723\r
724/**\r
725 Hook return address of SMM Save State so that semaphore code\r
726 can be executed immediately after AP exits SMM to indicate to\r
727 the BSP that an AP has exited SMM after SMBASE relocation.\r
728\r
729 @param[in] CpuIndex The processor index.\r
730 @param[in] RebasedFlag A pointer to a flag that is set to TRUE\r
731 immediately after AP exits SMM.\r
732\r
733**/\r
734VOID\r
735SemaphoreHook (\r
736 IN UINTN CpuIndex,\r
737 IN volatile BOOLEAN *RebasedFlag\r
738 );\r
739\r
740/**\r
741Configure SMM Code Access Check feature for all processors.\r
742SMM Feature Control MSR will be locked after configuration.\r
743**/\r
744VOID\r
745ConfigSmmCodeAccessCheck (\r
746 VOID\r
747 );\r
748\r
749/**\r
750 Hook the code executed immediately after an RSM instruction on the currently\r
751 executing CPU. The mode of code executed immediately after RSM must be\r
752 detected, and the appropriate hook must be selected. Always clear the auto\r
753 HALT restart flag if it is set.\r
754\r
755 @param[in] CpuIndex The processor index for the currently\r
756 executing CPU.\r
757 @param[in] CpuState Pointer to SMRAM Save State Map for the\r
758 currently executing CPU.\r
759 @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to\r
760 32-bit mode from 64-bit SMM.\r
761 @param[in] NewInstructionPointer Instruction pointer to use if resuming to\r
762 same mode as SMM.\r
763\r
764 @retval The value of the original instruction pointer before it was hooked.\r
765\r
766**/\r
767UINT64\r
768EFIAPI\r
769HookReturnFromSmm (\r
770 IN UINTN CpuIndex,\r
771 SMRAM_SAVE_STATE_MAP *CpuState,\r
772 UINT64 NewInstructionPointer32,\r
773 UINT64 NewInstructionPointer\r
774 );\r
775\r
776/**\r
777 Get the size of the SMI Handler in bytes.\r
778\r
779 @retval The size, in bytes, of the SMI Handler.\r
780\r
781**/\r
782UINTN\r
783EFIAPI\r
784GetSmiHandlerSize (\r
785 VOID\r
786 );\r
787\r
788/**\r
789 Install the SMI handler for the CPU specified by CpuIndex. This function\r
790 is called by the CPU that was elected as monarch during System Management\r
791 Mode initialization.\r
792\r
793 @param[in] CpuIndex The index of the CPU to install the custom SMI handler.\r
794 The value must be between 0 and the NumberOfCpus field\r
795 in the System Management System Table (SMST).\r
796 @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.\r
797 @param[in] SmiStack The stack to use when an SMI is processed by the\r
798 the CPU specified by CpuIndex.\r
799 @param[in] StackSize The size, in bytes, if the stack used when an SMI is\r
800 processed by the CPU specified by CpuIndex.\r
801 @param[in] GdtBase The base address of the GDT to use when an SMI is\r
802 processed by the CPU specified by CpuIndex.\r
803 @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is\r
804 processed by the CPU specified by CpuIndex.\r
805 @param[in] IdtBase The base address of the IDT to use when an SMI is\r
806 processed by the CPU specified by CpuIndex.\r
807 @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is\r
808 processed by the CPU specified by CpuIndex.\r
809 @param[in] Cr3 The base address of the page tables to use when an SMI\r
810 is processed by the CPU specified by CpuIndex.\r
811**/\r
812VOID\r
813EFIAPI\r
814InstallSmiHandler (\r
815 IN UINTN CpuIndex,\r
816 IN UINT32 SmBase,\r
817 IN VOID *SmiStack,\r
818 IN UINTN StackSize,\r
819 IN UINTN GdtBase,\r
820 IN UINTN GdtSize,\r
821 IN UINTN IdtBase,\r
822 IN UINTN IdtSize,\r
823 IN UINT32 Cr3\r
824 );\r
825\r
826/**\r
827 Search module name by input IP address and output it.\r
828\r
829 @param CallerIpAddress Caller instruction pointer.\r
830\r
831**/\r
832VOID\r
833DumpModuleInfoByIp (\r
834 IN UINTN CallerIpAddress\r
835 );\r
21c17193 836\r
717fb604
JY		 837/**\r
838 This function sets memory attribute according to MemoryAttributesTable.\r
839**/\r
840VOID\r
841SetMemMapAttributes (\r
842 VOID\r
843 );\r
844\r
d2fc7711
JY		 845/**\r
846 This function sets UEFI memory attribute according to UEFI memory map.\r
847**/\r
848VOID\r
849SetUefiMemMapAttributes (\r
850 VOID\r
851 );\r
852\r
853/**\r
854 Return if the Address is forbidden as SMM communication buffer.\r
855\r
856 @param[in] Address the address to be checked\r
857\r
858 @return TRUE The address is forbidden as SMM communication buffer.\r
859 @return FALSE The address is allowed as SMM communication buffer.\r
860**/\r
861BOOLEAN\r
862IsSmmCommBufferForbiddenAddress (\r
863 IN UINT64 Address\r
864 );\r
865\r
866/**\r
867 This function caches the UEFI memory map information.\r
868**/\r
869VOID\r
870GetUefiMemoryMap (\r
871 VOID\r
872 );\r
873\r
717fb604
JY		 874/**\r
875 This function sets memory attribute for page table.\r
876**/\r
877VOID\r
878SetPageTableAttributes (\r
879 VOID\r
880 );\r
881\r
882/**\r
883 Return page table base.\r
884\r
885 @return page table base.\r
886**/\r
887UINTN\r
888GetPageTableBase (\r
889 VOID\r
890 );\r
891\r
892/**\r
893 This function sets the attributes for the memory region specified by BaseAddress and\r
894 Length from their current attributes to the attributes specified by Attributes.\r
895\r
896 @param[in] BaseAddress The physical address that is the start address of a memory region.\r
897 @param[in] Length The size in bytes of the memory region.\r
898 @param[in] Attributes The bit mask of attributes to set for the memory region.\r
899 @param[out] IsSplitted TRUE means page table splitted. FALSE means page table not splitted.\r
900\r
901 @retval EFI_SUCCESS The attributes were set for the memory region.\r
902 @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r
903 BaseAddress and Length cannot be modified.\r
904 @retval EFI_INVALID_PARAMETER Length is zero.\r
905 Attributes specified an illegal combination of attributes that\r
906 cannot be set together.\r
907 @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r
908 the memory resource range.\r
909 @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r
910 resource range specified by BaseAddress and Length.\r
911 The bit mask of attributes is not support for the memory resource\r
912 range specified by BaseAddress and Length.\r
913\r
914**/\r
915EFI_STATUS\r
916EFIAPI\r
917SmmSetMemoryAttributesEx (\r
918 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
919 IN UINT64 Length,\r
920 IN UINT64 Attributes,\r
921 OUT BOOLEAN *IsSplitted OPTIONAL\r
922 );\r
923\r
924/**\r
925 This function clears the attributes for the memory region specified by BaseAddress and\r
926 Length from their current attributes to the attributes specified by Attributes.\r
927\r
928 @param[in] BaseAddress The physical address that is the start address of a memory region.\r
929 @param[in] Length The size in bytes of the memory region.\r
930 @param[in] Attributes The bit mask of attributes to clear for the memory region.\r
931 @param[out] IsSplitted TRUE means page table splitted. FALSE means page table not splitted.\r
932\r
933 @retval EFI_SUCCESS The attributes were cleared for the memory region.\r
934 @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r
935 BaseAddress and Length cannot be modified.\r
936 @retval EFI_INVALID_PARAMETER Length is zero.\r
937 Attributes specified an illegal combination of attributes that\r
938 cannot be set together.\r
939 @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r
940 the memory resource range.\r
941 @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r
942 resource range specified by BaseAddress and Length.\r
943 The bit mask of attributes is not support for the memory resource\r
944 range specified by BaseAddress and Length.\r
945\r
946**/\r
947EFI_STATUS\r
948EFIAPI\r
949SmmClearMemoryAttributesEx (\r
950 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
951 IN UINT64 Length,\r
952 IN UINT64 Attributes,\r
953 OUT BOOLEAN *IsSplitted OPTIONAL\r
954 );\r
955\r
21c17193
JY		 956/**\r
957 This API provides a way to allocate memory for page table.\r
958\r
959 This API can be called more once to allocate memory for page tables.\r
960\r
961 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the\r
962 allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL\r
963 is returned. If there is not enough memory remaining to satisfy the request, then NULL is\r
964 returned.\r
965\r
966 @param Pages The number of 4 KB pages to allocate.\r
967\r
968 @return A pointer to the allocated buffer or NULL if allocation fails.\r
969\r
970**/\r
971VOID *\r
972AllocatePageTableMemory (\r
973 IN UINTN Pages\r
974 );\r
975\r
717fb604
JY		 976/**\r
977 Allocate pages for code.\r
978\r
979 @param[in] Pages Number of pages to be allocated.\r
980\r
981 @return Allocated memory.\r
982**/\r
983VOID *\r
984AllocateCodePages (\r
985 IN UINTN Pages\r
986 );\r
987\r
988/**\r
989 Allocate aligned pages for code.\r
990\r
991 @param[in] Pages Number of pages to be allocated.\r
992 @param[in] Alignment The requested alignment of the allocation.\r
993 Must be a power of two.\r
994 If Alignment is zero, then byte alignment is used.\r
995\r
996 @return Allocated memory.\r
997**/\r
998VOID *\r
999AllocateAlignedCodePages (\r
1000 IN UINTN Pages,\r
1001 IN UINTN Alignment\r
1002 );\r
1003\r
0bdc9e75
SZ		 1004\r
1005//\r
1006// S3 related global variable and function prototype.\r
1007//\r
1008\r
1009extern BOOLEAN mSmmS3Flag;\r
1010\r
1011/**\r
1012 Initialize SMM S3 resume state structure used during S3 Resume.\r
1013\r
1014 @param[in] Cr3 The base address of the page tables to use in SMM.\r
1015\r
1016**/\r
1017VOID\r
1018InitSmmS3ResumeState (\r
1019 IN UINT32 Cr3\r
1020 );\r
1021\r
1022/**\r
1023 Get ACPI CPU data.\r
1024\r
1025**/\r
1026VOID\r
1027GetAcpiCpuData (\r
1028 VOID\r
1029 );\r
1030\r
1031/**\r
1032 Restore SMM Configuration in S3 boot path.\r
1033\r
1034**/\r
1035VOID\r
1036RestoreSmmConfigurationInS3 (\r
1037 VOID\r
1038 );\r
1039\r
b10d5ddc
SZ		 1040/**\r
1041 Get ACPI S3 enable flag.\r
1042\r
1043**/\r
1044VOID\r
1045GetAcpiS3EnableFlag (\r
1046 VOID\r
1047 );\r
1048\r
4a0f88dd
JF		 1049/**\r
1050 Transfer AP to safe hlt-loop after it finished restore CPU features on S3 patch.\r
1051\r
672b80c8
MK		 1052 @param[in] ApHltLoopCode The address of the safe hlt-loop function.\r
1053 @param[in] TopOfStack A pointer to the new stack to use for the ApHltLoopCode.\r
1054 @param[in] NumberToFinishAddress Address of Semaphore of APs finish count.\r
4a0f88dd
JF		 1055\r
1056**/\r
1057VOID\r
1058TransferApToSafeState (\r
672b80c8
MK		 1059 IN UINTN ApHltLoopCode,\r
1060 IN UINTN TopOfStack,\r
1061 IN UINTN NumberToFinishAddress\r
4a0f88dd
JF		 1062 );\r
1063\r
827330cc
JW		 1064/**\r
1065 This function set given attributes of the memory region specified by\r
1066 BaseAddress and Length.\r
1067\r
1068 @param This The EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL instance.\r
1069 @param BaseAddress The physical address that is the start address of\r
1070 a memory region.\r
1071 @param Length The size in bytes of the memory region.\r
1072 @param Attributes The bit mask of attributes to set for the memory\r
1073 region.\r
1074\r
1075 @retval EFI_SUCCESS The attributes were set for the memory region.\r
1076 @retval EFI_INVALID_PARAMETER Length is zero.\r
1077 Attributes specified an illegal combination of\r
1078 attributes that cannot be set together.\r
1079 @retval EFI_UNSUPPORTED The processor does not support one or more\r
1080 bytes of the memory resource range specified\r
1081 by BaseAddress and Length.\r
aae02dcc 1082 The bit mask of attributes is not supported for\r
827330cc
JW		 1083 the memory resource range specified by\r
1084 BaseAddress and Length.\r
1085\r
1086**/\r
1087EFI_STATUS\r
1088EFIAPI\r
1089EdkiiSmmSetMemoryAttributes (\r
1090 IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This,\r
1091 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
1092 IN UINT64 Length,\r
1093 IN UINT64 Attributes\r
1094 );\r
1095\r
1096/**\r
1097 This function clears given attributes of the memory region specified by\r
1098 BaseAddress and Length.\r
1099\r
1100 @param This The EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL instance.\r
1101 @param BaseAddress The physical address that is the start address of\r
1102 a memory region.\r
1103 @param Length The size in bytes of the memory region.\r
aae02dcc 1104 @param Attributes The bit mask of attributes to clear for the memory\r
827330cc
JW		 1105 region.\r
1106\r
aae02dcc 1107 @retval EFI_SUCCESS The attributes were cleared for the memory region.\r
827330cc
JW		 1108 @retval EFI_INVALID_PARAMETER Length is zero.\r
1109 Attributes specified an illegal combination of\r
aae02dcc 1110 attributes that cannot be cleared together.\r
827330cc
JW		 1111 @retval EFI_UNSUPPORTED The processor does not support one or more\r
1112 bytes of the memory resource range specified\r
1113 by BaseAddress and Length.\r
aae02dcc 1114 The bit mask of attributes is not supported for\r
827330cc
JW		 1115 the memory resource range specified by\r
1116 BaseAddress and Length.\r
1117\r
1118**/\r
1119EFI_STATUS\r
1120EFIAPI\r
1121EdkiiSmmClearMemoryAttributes (\r
1122 IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This,\r
1123 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
1124 IN UINT64 Length,\r
1125 IN UINT64 Attributes\r
1126 );\r
1127\r
1128/**\r
aae02dcc 1129 This function retrieves the attributes of the memory region specified by\r
827330cc
JW		 1130 BaseAddress and Length. If different attributes are got from different part\r
1131 of the memory region, EFI_NO_MAPPING will be returned.\r
1132\r
1133 @param This The EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL instance.\r
1134 @param BaseAddress The physical address that is the start address of\r
1135 a memory region.\r
1136 @param Length The size in bytes of the memory region.\r
1137 @param Attributes Pointer to attributes returned.\r
1138\r
1139 @retval EFI_SUCCESS The attributes got for the memory region.\r
1140 @retval EFI_INVALID_PARAMETER Length is zero.\r
1141 Attributes is NULL.\r
1142 @retval EFI_NO_MAPPING Attributes are not consistent cross the memory\r
1143 region.\r
1144 @retval EFI_UNSUPPORTED The processor does not support one or more\r
1145 bytes of the memory resource range specified\r
1146 by BaseAddress and Length.\r
827330cc
JW		 1147\r
1148**/\r
1149EFI_STATUS\r
1150EFIAPI\r
1151EdkiiSmmGetMemoryAttributes (\r
1152 IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This,\r
1153 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
1154 IN UINT64 Length,\r
1155 IN UINT64 *Attributes\r
1156 );\r
1157\r
e21e355e
LG		 1158/**\r
1159 This function fixes up the address of the global variable or function\r
1160 referred in SmmInit assembly files to be the absoute address.\r
1161**/\r
1162VOID\r
1163EFIAPI\r
1164PiSmmCpuSmmInitFixupAddress (\r
1165 );\r
1166\r
1167/**\r
1168 This function fixes up the address of the global variable or function\r
1169 referred in SmiEntry assembly files to be the absoute address.\r
1170**/\r
1171VOID\r
1172EFIAPI\r
1173PiSmmCpuSmiEntryFixupAddress (\r
1174 );\r
1175\r
529a5a86 1176#endif\r
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