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UefiCpuPkg/PiSmmCpu: Always set RW+P bit for page table by default
[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / PiSmmCpuDxeSmm.h
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529a5a86
MK		 1/** @file\r
2Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.\r
3\r
4Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>\r
5This program and the accompanying materials\r
6are licensed and made available under the terms and conditions of the BSD License\r
7which accompanies this distribution. The full text of the license may be found at\r
8http://opensource.org/licenses/bsd-license.php\r
9\r
10THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/\r
14\r
15#ifndef _CPU_PISMMCPUDXESMM_H_\r
16#define _CPU_PISMMCPUDXESMM_H_\r
17\r
18#include <PiSmm.h>\r
19\r
20#include <Protocol/MpService.h>\r
21#include <Protocol/SmmConfiguration.h>\r
22#include <Protocol/SmmCpu.h>\r
23#include <Protocol/SmmAccess2.h>\r
529a5a86
MK		 24#include <Protocol/SmmReadyToLock.h>\r
25#include <Protocol/SmmCpuService.h>\r
26\r
27#include <Guid/AcpiS3Context.h>\r
28\r
29#include <Library/BaseLib.h>\r
30#include <Library/IoLib.h>\r
31#include <Library/TimerLib.h>\r
529a5a86
MK		 32#include <Library/SynchronizationLib.h>\r
33#include <Library/DebugLib.h>\r
34#include <Library/BaseMemoryLib.h>\r
35#include <Library/PcdLib.h>\r
36#include <Library/CacheMaintenanceLib.h>\r
37#include <Library/MtrrLib.h>\r
38#include <Library/SmmCpuPlatformHookLib.h>\r
39#include <Library/SmmServicesTableLib.h>\r
40#include <Library/MemoryAllocationLib.h>\r
41#include <Library/UefiBootServicesTableLib.h>\r
42#include <Library/UefiRuntimeServicesTableLib.h>\r
43#include <Library/DebugAgentLib.h>\r
44#include <Library/HobLib.h>\r
45#include <Library/LocalApicLib.h>\r
46#include <Library/UefiCpuLib.h>\r
47#include <Library/CpuExceptionHandlerLib.h>\r
48#include <Library/ReportStatusCodeLib.h>\r
49#include <Library/SmmCpuFeaturesLib.h>\r
50#include <Library/PeCoffGetEntryPointLib.h>\r
51\r
52#include <AcpiCpuData.h>\r
53#include <CpuHotPlugData.h>\r
54\r
55#include <Register/Cpuid.h>\r
56\r
57#include "CpuService.h"\r
58#include "SmmProfile.h"\r
59\r
60//\r
61// MSRs required for configuration of SMM Code Access Check\r
62//\r
63#define EFI_MSR_SMM_MCA_CAP 0x17D\r
64#define SMM_CODE_ACCESS_CHK_BIT BIT58\r
65\r
66#define SMM_FEATURE_CONTROL_LOCK_BIT BIT0\r
67#define SMM_CODE_CHK_EN_BIT BIT2\r
68\r
69///\r
70/// Page Table Entry\r
71///\r
72#define IA32_PG_P BIT0\r
73#define IA32_PG_RW BIT1\r
881520ea 74#define IA32_PG_U BIT2\r
529a5a86
MK		 75#define IA32_PG_WT BIT3\r
76#define IA32_PG_CD BIT4\r
77#define IA32_PG_A BIT5\r
881520ea 78#define IA32_PG_D BIT6\r
529a5a86
MK		 79#define IA32_PG_PS BIT7\r
80#define IA32_PG_PAT_2M BIT12\r
81#define IA32_PG_PAT_4K IA32_PG_PS\r
82#define IA32_PG_PMNT BIT62\r
83#define IA32_PG_NX BIT63\r
84\r
881520ea
JY		 85#define PAGE_ATTRIBUTE_BITS (IA32_PG_RW | IA32_PG_P)\r
86//\r
87// Bits 1, 2, 5, 6 are reserved in the IA32 PAE PDPTE\r
88// X64 PAE PDPTE does not have such restriction\r
89//\r
90#define IA32_PAE_PDPTE_ATTRIBUTE_BITS (IA32_PG_P)\r
91\r
529a5a86
MK		 92//\r
93// Size of Task-State Segment defined in IA32 Manual\r
94//\r
95#define TSS_SIZE 104\r
96#define TSS_X64_IST1_OFFSET 36\r
97#define TSS_IA32_CR3_OFFSET 28\r
98#define TSS_IA32_ESP_OFFSET 56\r
99\r
100//\r
101// Code select value\r
102//\r
103#define PROTECT_MODE_CODE_SEGMENT 0x08\r
104#define LONG_MODE_CODE_SEGMENT 0x38\r
105\r
106//\r
107// The size 0x20 must be bigger than\r
108// the size of template code of SmmInit. Currently,\r
109// the size of SmmInit requires the 0x16 Bytes buffer\r
110// at least.\r
111//\r
112#define BACK_BUF_SIZE 0x20\r
113\r
114#define EXCEPTION_VECTOR_NUMBER 0x20\r
115\r
116#define INVALID_APIC_ID 0xFFFFFFFFFFFFFFFFULL\r
117\r
118typedef UINT32 SMM_CPU_ARRIVAL_EXCEPTIONS;\r
119#define ARRIVAL_EXCEPTION_BLOCKED 0x1\r
120#define ARRIVAL_EXCEPTION_DELAYED 0x2\r
121#define ARRIVAL_EXCEPTION_SMI_DISABLED 0x4\r
122\r
123//\r
124// Private structure for the SMM CPU module that is stored in DXE Runtime memory\r
125// Contains the SMM Configuration Protocols that is produced.\r
126// Contains a mix of DXE and SMM contents. All the fields must be used properly.\r
127//\r
128#define SMM_CPU_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('s', 'c', 'p', 'u')\r
129\r
130typedef struct {\r
131 UINTN Signature;\r
132\r
133 EFI_HANDLE SmmCpuHandle;\r
134\r
135 EFI_PROCESSOR_INFORMATION *ProcessorInfo;\r
136 SMM_CPU_OPERATION *Operation;\r
137 UINTN *CpuSaveStateSize;\r
138 VOID **CpuSaveState;\r
139\r
140 EFI_SMM_RESERVED_SMRAM_REGION SmmReservedSmramRegion[1];\r
141 EFI_SMM_ENTRY_CONTEXT SmmCoreEntryContext;\r
142 EFI_SMM_ENTRY_POINT SmmCoreEntry;\r
143\r
144 EFI_SMM_CONFIGURATION_PROTOCOL SmmConfiguration;\r
145} SMM_CPU_PRIVATE_DATA;\r
146\r
147extern SMM_CPU_PRIVATE_DATA *gSmmCpuPrivate;\r
148extern CPU_HOT_PLUG_DATA mCpuHotPlugData;\r
149extern UINTN mMaxNumberOfCpus;\r
150extern UINTN mNumberOfCpus;\r
151extern BOOLEAN mRestoreSmmConfigurationInS3;\r
152extern EFI_SMM_CPU_PROTOCOL mSmmCpu;\r
153\r
154///\r
155/// The mode of the CPU at the time an SMI occurs\r
156///\r
157extern UINT8 mSmmSaveStateRegisterLma;\r
158\r
159\r
160//\r
161// SMM CPU Protocol function prototypes.\r
162//\r
163\r
164/**\r
165 Read information from the CPU save state.\r
166\r
167 @param This EFI_SMM_CPU_PROTOCOL instance\r
168 @param Width The number of bytes to read from the CPU save state.\r
169 @param Register Specifies the CPU register to read form the save state.\r
170 @param CpuIndex Specifies the zero-based index of the CPU save state\r
171 @param Buffer Upon return, this holds the CPU register value read from the save state.\r
172\r
173 @retval EFI_SUCCESS The register was read from Save State\r
174 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor\r
175 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.\r
176\r
177**/\r
178EFI_STATUS\r
179EFIAPI\r
180SmmReadSaveState (\r
181 IN CONST EFI_SMM_CPU_PROTOCOL *This,\r
182 IN UINTN Width,\r
183 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
184 IN UINTN CpuIndex,\r
185 OUT VOID *Buffer\r
186 );\r
187\r
188/**\r
189 Write data to the CPU save state.\r
190\r
191 @param This EFI_SMM_CPU_PROTOCOL instance\r
192 @param Width The number of bytes to read from the CPU save state.\r
193 @param Register Specifies the CPU register to write to the save state.\r
194 @param CpuIndex Specifies the zero-based index of the CPU save state\r
195 @param Buffer Upon entry, this holds the new CPU register value.\r
196\r
197 @retval EFI_SUCCESS The register was written from Save State\r
198 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor\r
199 @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct\r
200\r
201**/\r
202EFI_STATUS\r
203EFIAPI\r
204SmmWriteSaveState (\r
205 IN CONST EFI_SMM_CPU_PROTOCOL *This,\r
206 IN UINTN Width,\r
207 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
208 IN UINTN CpuIndex,\r
209 IN CONST VOID *Buffer\r
210 );\r
211\r
212/**\r
213Read a CPU Save State register on the target processor.\r
214\r
215This function abstracts the differences that whether the CPU Save State register is in the\r
216IA32 CPU Save State Map or X64 CPU Save State Map.\r
217\r
218This function supports reading a CPU Save State register in SMBase relocation handler.\r
219\r
220@param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r
221@param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r
222@param[in] Width The number of bytes to read from the CPU save state.\r
223@param[out] Buffer Upon return, this holds the CPU register value read from the save state.\r
224\r
225@retval EFI_SUCCESS The register was read from Save State.\r
226@retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r
227@retval EFI_INVALID_PARAMTER This or Buffer is NULL.\r
228\r
229**/\r
230EFI_STATUS\r
231EFIAPI\r
232ReadSaveStateRegister (\r
233 IN UINTN CpuIndex,\r
234 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
235 IN UINTN Width,\r
236 OUT VOID *Buffer\r
237 );\r
238\r
239/**\r
240Write value to a CPU Save State register on the target processor.\r
241\r
242This function abstracts the differences that whether the CPU Save State register is in the\r
243IA32 CPU Save State Map or X64 CPU Save State Map.\r
244\r
245This function supports writing a CPU Save State register in SMBase relocation handler.\r
246\r
247@param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r
248@param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r
249@param[in] Width The number of bytes to read from the CPU save state.\r
250@param[in] Buffer Upon entry, this holds the new CPU register value.\r
251\r
252@retval EFI_SUCCESS The register was written to Save State.\r
253@retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r
254@retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct.\r
255\r
256**/\r
257EFI_STATUS\r
258EFIAPI\r
259WriteSaveStateRegister (\r
260 IN UINTN CpuIndex,\r
261 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
262 IN UINTN Width,\r
263 IN CONST VOID *Buffer\r
264 );\r
265\r
266//\r
267//\r
268//\r
269typedef struct {\r
270 UINT32 Offset;\r
271 UINT16 Segment;\r
272 UINT16 Reserved;\r
273} IA32_FAR_ADDRESS;\r
274\r
275extern IA32_FAR_ADDRESS gSmmJmpAddr;\r
276\r
277extern CONST UINT8 gcSmmInitTemplate[];\r
278extern CONST UINT16 gcSmmInitSize;\r
279extern UINT32 gSmmCr0;\r
280extern UINT32 gSmmCr3;\r
281extern UINT32 gSmmCr4;\r
282extern UINTN gSmmInitStack;\r
283\r
284/**\r
285 Semaphore operation for all processor relocate SMMBase.\r
286**/\r
287VOID\r
288EFIAPI\r
289SmmRelocationSemaphoreComplete (\r
290 VOID\r
291 );\r
292\r
293///\r
294/// The type of SMM CPU Information\r
295///\r
296typedef struct {\r
297 SPIN_LOCK Busy;\r
298 volatile EFI_AP_PROCEDURE Procedure;\r
299 volatile VOID *Parameter;\r
300 volatile UINT32 Run;\r
301 volatile BOOLEAN Present;\r
302} SMM_CPU_DATA_BLOCK;\r
303\r
304typedef enum {\r
305 SmmCpuSyncModeTradition,\r
306 SmmCpuSyncModeRelaxedAp,\r
307 SmmCpuSyncModeMax\r
308} SMM_CPU_SYNC_MODE;\r
309\r
310typedef struct {\r
311 //\r
312 // Pointer to an array. The array should be located immediately after this structure\r
313 // so that UC cache-ability can be set together.\r
314 //\r
315 SMM_CPU_DATA_BLOCK *CpuData;\r
316 volatile UINT32 Counter;\r
317 volatile UINT32 BspIndex;\r
318 volatile BOOLEAN InsideSmm;\r
319 volatile BOOLEAN AllCpusInSync;\r
320 volatile SMM_CPU_SYNC_MODE EffectiveSyncMode;\r
321 volatile BOOLEAN SwitchBsp;\r
322 volatile BOOLEAN *CandidateBsp;\r
323} SMM_DISPATCHER_MP_SYNC_DATA;\r
324\r
325typedef struct {\r
326 SPIN_LOCK SpinLock;\r
327 UINT32 MsrIndex;\r
328} MP_MSR_LOCK;\r
329\r
330#define SMM_PSD_OFFSET 0xfb00\r
331\r
332typedef struct {\r
333 UINT64 Signature; // Offset 0x00\r
334 UINT16 Reserved1; // Offset 0x08\r
335 UINT16 Reserved2; // Offset 0x0A\r
336 UINT16 Reserved3; // Offset 0x0C\r
337 UINT16 SmmCs; // Offset 0x0E\r
338 UINT16 SmmDs; // Offset 0x10\r
339 UINT16 SmmSs; // Offset 0x12\r
340 UINT16 SmmOtherSegment; // Offset 0x14\r
341 UINT16 Reserved4; // Offset 0x16\r
342 UINT64 Reserved5; // Offset 0x18\r
343 UINT64 Reserved6; // Offset 0x20\r
344 UINT64 Reserved7; // Offset 0x28\r
345 UINT64 SmmGdtPtr; // Offset 0x30\r
346 UINT32 SmmGdtSize; // Offset 0x38\r
347 UINT32 Reserved8; // Offset 0x3C\r
348 UINT64 Reserved9; // Offset 0x40\r
349 UINT64 Reserved10; // Offset 0x48\r
350 UINT16 Reserved11; // Offset 0x50\r
351 UINT16 Reserved12; // Offset 0x52\r
352 UINT32 Reserved13; // Offset 0x54\r
353 UINT64 MtrrBaseMaskPtr; // Offset 0x58\r
354} PROCESSOR_SMM_DESCRIPTOR;\r
355\r
356extern IA32_DESCRIPTOR gcSmiGdtr;\r
357extern IA32_DESCRIPTOR gcSmiIdtr;\r
358extern VOID *gcSmiIdtrPtr;\r
359extern CONST PROCESSOR_SMM_DESCRIPTOR gcPsd;\r
360extern UINT64 gPhyMask;\r
361extern ACPI_CPU_DATA mAcpiCpuData;\r
362extern SMM_DISPATCHER_MP_SYNC_DATA *mSmmMpSyncData;\r
363extern VOID *mGdtForAp;\r
364extern VOID *mIdtForAp;\r
365extern VOID *mMachineCheckHandlerForAp;\r
366extern UINTN mSmmStackArrayBase;\r
367extern UINTN mSmmStackArrayEnd;\r
368extern UINTN mSmmStackSize;\r
369extern EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService;\r
370extern IA32_DESCRIPTOR gcSmiInitGdtr;\r
371\r
372/**\r
373 Create 4G PageTable in SMRAM.\r
374\r
375 @param ExtraPages Additional page numbers besides for 4G memory\r
881520ea 376 @param Is32BitPageTable Whether the page table is 32-bit PAE\r
529a5a86
MK		 377 @return PageTable Address\r
378\r
379**/\r
380UINT32\r
381Gen4GPageTable (\r
881520ea
JY		 382 IN UINTN ExtraPages,\r
383 IN BOOLEAN Is32BitPageTable\r
529a5a86
MK		 384 );\r
385\r
386\r
387/**\r
388 Initialize global data for MP synchronization.\r
389\r
390 @param Stacks Base address of SMI stack buffer for all processors.\r
391 @param StackSize Stack size for each processor in SMM.\r
392\r
393**/\r
394UINT32\r
395InitializeMpServiceData (\r
396 IN VOID *Stacks,\r
397 IN UINTN StackSize\r
398 );\r
399\r
400/**\r
401 Initialize Timer for SMM AP Sync.\r
402\r
403**/\r
404VOID\r
405InitializeSmmTimer (\r
406 VOID\r
407 );\r
408\r
409/**\r
410 Start Timer for SMM AP Sync.\r
411\r
412**/\r
413UINT64\r
414EFIAPI\r
415StartSyncTimer (\r
416 VOID\r
417 );\r
418\r
419/**\r
420 Check if the SMM AP Sync timer is timeout.\r
421\r
422 @param Timer The start timer from the begin.\r
423\r
424**/\r
425BOOLEAN\r
426EFIAPI\r
427IsSyncTimerTimeout (\r
428 IN UINT64 Timer\r
429 );\r
430\r
431/**\r
432 Initialize IDT for SMM Stack Guard.\r
433\r
434**/\r
435VOID\r
436EFIAPI\r
437InitializeIDTSmmStackGuard (\r
438 VOID\r
439 );\r
440\r
fe5f1949
JY		 441/**\r
442 Initialize Gdt for all processors.\r
443 \r
444 @param[in] Cr3 CR3 value.\r
445 @param[out] GdtStepSize The step size for GDT table.\r
446\r
447 @return GdtBase for processor 0.\r
448 GdtBase for processor X is: GdtBase + (GdtStepSize * X)\r
449**/\r
450VOID *\r
451InitGdt (\r
452 IN UINTN Cr3,\r
453 OUT UINTN *GdtStepSize\r
454 );\r
455\r
529a5a86
MK		 456/**\r
457\r
458 Register the SMM Foundation entry point.\r
459\r
460 @param This Pointer to EFI_SMM_CONFIGURATION_PROTOCOL instance\r
461 @param SmmEntryPoint SMM Foundation EntryPoint\r
462\r
463 @retval EFI_SUCCESS Successfully to register SMM foundation entry point\r
464\r
465**/\r
466EFI_STATUS\r
467EFIAPI\r
468RegisterSmmEntry (\r
469 IN CONST EFI_SMM_CONFIGURATION_PROTOCOL *This,\r
470 IN EFI_SMM_ENTRY_POINT SmmEntryPoint\r
471 );\r
472\r
473/**\r
474 Create PageTable for SMM use.\r
475\r
476 @return PageTable Address\r
477\r
478**/\r
479UINT32\r
480SmmInitPageTable (\r
481 VOID\r
482 );\r
483\r
484/**\r
485 Schedule a procedure to run on the specified CPU.\r
486\r
487 @param Procedure The address of the procedure to run\r
488 @param CpuIndex Target CPU number\r
489 @param ProcArguments The parameter to pass to the procedure\r
490\r
491 @retval EFI_INVALID_PARAMETER CpuNumber not valid\r
492 @retval EFI_INVALID_PARAMETER CpuNumber specifying BSP\r
493 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM\r
494 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy\r
495 @retval EFI_SUCCESS - The procedure has been successfully scheduled\r
496\r
497**/\r
498EFI_STATUS\r
499EFIAPI\r
500SmmStartupThisAp (\r
501 IN EFI_AP_PROCEDURE Procedure,\r
502 IN UINTN CpuIndex,\r
503 IN OUT VOID *ProcArguments OPTIONAL\r
504 );\r
505\r
506/**\r
507 Schedule a procedure to run on the specified CPU in a blocking fashion.\r
508\r
509 @param Procedure The address of the procedure to run\r
510 @param CpuIndex Target CPU Index\r
511 @param ProcArguments The parameter to pass to the procedure\r
512\r
513 @retval EFI_INVALID_PARAMETER CpuNumber not valid\r
514 @retval EFI_INVALID_PARAMETER CpuNumber specifying BSP\r
515 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM\r
516 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy\r
517 @retval EFI_SUCCESS The procedure has been successfully scheduled\r
518\r
519**/\r
520EFI_STATUS\r
521EFIAPI\r
522SmmBlockingStartupThisAp (\r
523 IN EFI_AP_PROCEDURE Procedure,\r
524 IN UINTN CpuIndex,\r
525 IN OUT VOID *ProcArguments OPTIONAL\r
526 );\r
527\r
528/**\r
529 Initialize MP synchronization data.\r
530\r
531**/\r
532VOID\r
533EFIAPI\r
534InitializeMpSyncData (\r
535 VOID\r
536 );\r
537\r
538/**\r
539\r
540 Find out SMRAM information including SMRR base and SMRR size.\r
541\r
542 @param SmrrBase SMRR base\r
543 @param SmrrSize SMRR size\r
544\r
545**/\r
546VOID\r
547FindSmramInfo (\r
548 OUT UINT32 *SmrrBase,\r
549 OUT UINT32 *SmrrSize\r
550 );\r
551\r
552/**\r
553 The function is invoked before SMBASE relocation in S3 path to restores CPU status.\r
554\r
555 The function is invoked before SMBASE relocation in S3 path. It does first time microcode load\r
556 and restores MTRRs for both BSP and APs.\r
557\r
558**/\r
559VOID\r
560EarlyInitializeCpu (\r
561 VOID\r
562 );\r
563\r
564/**\r
565 The function is invoked after SMBASE relocation in S3 path to restores CPU status.\r
566\r
567 The function is invoked after SMBASE relocation in S3 path. It restores configuration according to\r
568 data saved by normal boot path for both BSP and APs.\r
569\r
570**/\r
571VOID\r
572InitializeCpu (\r
573 VOID\r
574 );\r
575\r
576/**\r
577 Page Fault handler for SMM use.\r
578\r
579 @param InterruptType Defines the type of interrupt or exception that\r
580 occurred on the processor.This parameter is processor architecture specific.\r
581 @param SystemContext A pointer to the processor context when\r
582 the interrupt occurred on the processor.\r
583**/\r
584VOID\r
585EFIAPI\r
586SmiPFHandler (\r
587 IN EFI_EXCEPTION_TYPE InterruptType,\r
588 IN EFI_SYSTEM_CONTEXT SystemContext\r
589 );\r
590\r
591/**\r
592 Perform the remaining tasks.\r
593\r
594**/\r
595VOID\r
596PerformRemainingTasks (\r
597 VOID\r
598 );\r
599\r
9f419739
JY		 600/**\r
601 Perform the pre tasks.\r
602\r
603**/\r
604VOID\r
605PerformPreTasks (\r
606 VOID\r
607 );\r
608\r
529a5a86
MK		 609/**\r
610 Initialize MSR spin lock by MSR index.\r
611\r
612 @param MsrIndex MSR index value.\r
613\r
614**/\r
615VOID\r
616InitMsrSpinLockByIndex (\r
617 IN UINT32 MsrIndex\r
618 );\r
619\r
620/**\r
621 Hook return address of SMM Save State so that semaphore code\r
622 can be executed immediately after AP exits SMM to indicate to\r
623 the BSP that an AP has exited SMM after SMBASE relocation.\r
624\r
625 @param[in] CpuIndex The processor index.\r
626 @param[in] RebasedFlag A pointer to a flag that is set to TRUE\r
627 immediately after AP exits SMM.\r
628\r
629**/\r
630VOID\r
631SemaphoreHook (\r
632 IN UINTN CpuIndex,\r
633 IN volatile BOOLEAN *RebasedFlag\r
634 );\r
635\r
636/**\r
637Configure SMM Code Access Check feature for all processors.\r
638SMM Feature Control MSR will be locked after configuration.\r
639**/\r
640VOID\r
641ConfigSmmCodeAccessCheck (\r
642 VOID\r
643 );\r
644\r
645/**\r
646 Hook the code executed immediately after an RSM instruction on the currently\r
647 executing CPU. The mode of code executed immediately after RSM must be\r
648 detected, and the appropriate hook must be selected. Always clear the auto\r
649 HALT restart flag if it is set.\r
650\r
651 @param[in] CpuIndex The processor index for the currently\r
652 executing CPU.\r
653 @param[in] CpuState Pointer to SMRAM Save State Map for the\r
654 currently executing CPU.\r
655 @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to\r
656 32-bit mode from 64-bit SMM.\r
657 @param[in] NewInstructionPointer Instruction pointer to use if resuming to\r
658 same mode as SMM.\r
659\r
660 @retval The value of the original instruction pointer before it was hooked.\r
661\r
662**/\r
663UINT64\r
664EFIAPI\r
665HookReturnFromSmm (\r
666 IN UINTN CpuIndex,\r
667 SMRAM_SAVE_STATE_MAP *CpuState,\r
668 UINT64 NewInstructionPointer32,\r
669 UINT64 NewInstructionPointer\r
670 );\r
671\r
672/**\r
673 Get the size of the SMI Handler in bytes.\r
674\r
675 @retval The size, in bytes, of the SMI Handler.\r
676\r
677**/\r
678UINTN\r
679EFIAPI\r
680GetSmiHandlerSize (\r
681 VOID\r
682 );\r
683\r
684/**\r
685 Install the SMI handler for the CPU specified by CpuIndex. This function\r
686 is called by the CPU that was elected as monarch during System Management\r
687 Mode initialization.\r
688\r
689 @param[in] CpuIndex The index of the CPU to install the custom SMI handler.\r
690 The value must be between 0 and the NumberOfCpus field\r
691 in the System Management System Table (SMST).\r
692 @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.\r
693 @param[in] SmiStack The stack to use when an SMI is processed by the\r
694 the CPU specified by CpuIndex.\r
695 @param[in] StackSize The size, in bytes, if the stack used when an SMI is\r
696 processed by the CPU specified by CpuIndex.\r
697 @param[in] GdtBase The base address of the GDT to use when an SMI is\r
698 processed by the CPU specified by CpuIndex.\r
699 @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is\r
700 processed by the CPU specified by CpuIndex.\r
701 @param[in] IdtBase The base address of the IDT to use when an SMI is\r
702 processed by the CPU specified by CpuIndex.\r
703 @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is\r
704 processed by the CPU specified by CpuIndex.\r
705 @param[in] Cr3 The base address of the page tables to use when an SMI\r
706 is processed by the CPU specified by CpuIndex.\r
707**/\r
708VOID\r
709EFIAPI\r
710InstallSmiHandler (\r
711 IN UINTN CpuIndex,\r
712 IN UINT32 SmBase,\r
713 IN VOID *SmiStack,\r
714 IN UINTN StackSize,\r
715 IN UINTN GdtBase,\r
716 IN UINTN GdtSize,\r
717 IN UINTN IdtBase,\r
718 IN UINTN IdtSize,\r
719 IN UINT32 Cr3\r
720 );\r
721\r
722/**\r
723 Search module name by input IP address and output it.\r
724\r
725 @param CallerIpAddress Caller instruction pointer.\r
726\r
727**/\r
728VOID\r
729DumpModuleInfoByIp (\r
730 IN UINTN CallerIpAddress\r
731 );\r
21c17193
JY		 732\r
733/**\r
734 This API provides a way to allocate memory for page table.\r
735\r
736 This API can be called more once to allocate memory for page tables.\r
737\r
738 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the\r
739 allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL\r
740 is returned. If there is not enough memory remaining to satisfy the request, then NULL is\r
741 returned.\r
742\r
743 @param Pages The number of 4 KB pages to allocate.\r
744\r
745 @return A pointer to the allocated buffer or NULL if allocation fails.\r
746\r
747**/\r
748VOID *\r
749AllocatePageTableMemory (\r
750 IN UINTN Pages\r
751 );\r
752\r
529a5a86 753#endif\r
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