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UefiCpuPkg/PiSmmCpu: Add NULL func for 2 new APIs in SmmCpuFeaturesLib.
[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / PiSmmCpuDxeSmm.h
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529a5a86
MK		 1/** @file\r
2Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.\r
3\r
4Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>\r
5This program and the accompanying materials\r
6are licensed and made available under the terms and conditions of the BSD License\r
7which accompanies this distribution. The full text of the license may be found at\r
8http://opensource.org/licenses/bsd-license.php\r
9\r
10THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/\r
14\r
15#ifndef _CPU_PISMMCPUDXESMM_H_\r
16#define _CPU_PISMMCPUDXESMM_H_\r
17\r
18#include <PiSmm.h>\r
19\r
20#include <Protocol/MpService.h>\r
21#include <Protocol/SmmConfiguration.h>\r
22#include <Protocol/SmmCpu.h>\r
23#include <Protocol/SmmAccess2.h>\r
529a5a86
MK		 24#include <Protocol/SmmReadyToLock.h>\r
25#include <Protocol/SmmCpuService.h>\r
26\r
27#include <Guid/AcpiS3Context.h>\r
28\r
29#include <Library/BaseLib.h>\r
30#include <Library/IoLib.h>\r
31#include <Library/TimerLib.h>\r
529a5a86
MK		 32#include <Library/SynchronizationLib.h>\r
33#include <Library/DebugLib.h>\r
34#include <Library/BaseMemoryLib.h>\r
35#include <Library/PcdLib.h>\r
36#include <Library/CacheMaintenanceLib.h>\r
37#include <Library/MtrrLib.h>\r
38#include <Library/SmmCpuPlatformHookLib.h>\r
39#include <Library/SmmServicesTableLib.h>\r
40#include <Library/MemoryAllocationLib.h>\r
41#include <Library/UefiBootServicesTableLib.h>\r
42#include <Library/UefiRuntimeServicesTableLib.h>\r
43#include <Library/DebugAgentLib.h>\r
44#include <Library/HobLib.h>\r
45#include <Library/LocalApicLib.h>\r
46#include <Library/UefiCpuLib.h>\r
47#include <Library/CpuExceptionHandlerLib.h>\r
48#include <Library/ReportStatusCodeLib.h>\r
49#include <Library/SmmCpuFeaturesLib.h>\r
50#include <Library/PeCoffGetEntryPointLib.h>\r
51\r
52#include <AcpiCpuData.h>\r
53#include <CpuHotPlugData.h>\r
54\r
55#include <Register/Cpuid.h>\r
56\r
57#include "CpuService.h"\r
58#include "SmmProfile.h"\r
59\r
60//\r
61// MSRs required for configuration of SMM Code Access Check\r
62//\r
63#define EFI_MSR_SMM_MCA_CAP 0x17D\r
64#define SMM_CODE_ACCESS_CHK_BIT BIT58\r
65\r
66#define SMM_FEATURE_CONTROL_LOCK_BIT BIT0\r
67#define SMM_CODE_CHK_EN_BIT BIT2\r
68\r
69///\r
70/// Page Table Entry\r
71///\r
72#define IA32_PG_P BIT0\r
73#define IA32_PG_RW BIT1\r
74#define IA32_PG_WT BIT3\r
75#define IA32_PG_CD BIT4\r
76#define IA32_PG_A BIT5\r
77#define IA32_PG_PS BIT7\r
78#define IA32_PG_PAT_2M BIT12\r
79#define IA32_PG_PAT_4K IA32_PG_PS\r
80#define IA32_PG_PMNT BIT62\r
81#define IA32_PG_NX BIT63\r
82\r
83//\r
84// Size of Task-State Segment defined in IA32 Manual\r
85//\r
86#define TSS_SIZE 104\r
87#define TSS_X64_IST1_OFFSET 36\r
88#define TSS_IA32_CR3_OFFSET 28\r
89#define TSS_IA32_ESP_OFFSET 56\r
90\r
91//\r
92// Code select value\r
93//\r
94#define PROTECT_MODE_CODE_SEGMENT 0x08\r
95#define LONG_MODE_CODE_SEGMENT 0x38\r
96\r
97//\r
98// The size 0x20 must be bigger than\r
99// the size of template code of SmmInit. Currently,\r
100// the size of SmmInit requires the 0x16 Bytes buffer\r
101// at least.\r
102//\r
103#define BACK_BUF_SIZE 0x20\r
104\r
105#define EXCEPTION_VECTOR_NUMBER 0x20\r
106\r
107#define INVALID_APIC_ID 0xFFFFFFFFFFFFFFFFULL\r
108\r
109typedef UINT32 SMM_CPU_ARRIVAL_EXCEPTIONS;\r
110#define ARRIVAL_EXCEPTION_BLOCKED 0x1\r
111#define ARRIVAL_EXCEPTION_DELAYED 0x2\r
112#define ARRIVAL_EXCEPTION_SMI_DISABLED 0x4\r
113\r
114//\r
115// Private structure for the SMM CPU module that is stored in DXE Runtime memory\r
116// Contains the SMM Configuration Protocols that is produced.\r
117// Contains a mix of DXE and SMM contents. All the fields must be used properly.\r
118//\r
119#define SMM_CPU_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('s', 'c', 'p', 'u')\r
120\r
121typedef struct {\r
122 UINTN Signature;\r
123\r
124 EFI_HANDLE SmmCpuHandle;\r
125\r
126 EFI_PROCESSOR_INFORMATION *ProcessorInfo;\r
127 SMM_CPU_OPERATION *Operation;\r
128 UINTN *CpuSaveStateSize;\r
129 VOID **CpuSaveState;\r
130\r
131 EFI_SMM_RESERVED_SMRAM_REGION SmmReservedSmramRegion[1];\r
132 EFI_SMM_ENTRY_CONTEXT SmmCoreEntryContext;\r
133 EFI_SMM_ENTRY_POINT SmmCoreEntry;\r
134\r
135 EFI_SMM_CONFIGURATION_PROTOCOL SmmConfiguration;\r
136} SMM_CPU_PRIVATE_DATA;\r
137\r
138extern SMM_CPU_PRIVATE_DATA *gSmmCpuPrivate;\r
139extern CPU_HOT_PLUG_DATA mCpuHotPlugData;\r
140extern UINTN mMaxNumberOfCpus;\r
141extern UINTN mNumberOfCpus;\r
142extern BOOLEAN mRestoreSmmConfigurationInS3;\r
143extern EFI_SMM_CPU_PROTOCOL mSmmCpu;\r
144\r
145///\r
146/// The mode of the CPU at the time an SMI occurs\r
147///\r
148extern UINT8 mSmmSaveStateRegisterLma;\r
149\r
150\r
151//\r
152// SMM CPU Protocol function prototypes.\r
153//\r
154\r
155/**\r
156 Read information from the CPU save state.\r
157\r
158 @param This EFI_SMM_CPU_PROTOCOL instance\r
159 @param Width The number of bytes to read from the CPU save state.\r
160 @param Register Specifies the CPU register to read form the save state.\r
161 @param CpuIndex Specifies the zero-based index of the CPU save state\r
162 @param Buffer Upon return, this holds the CPU register value read from the save state.\r
163\r
164 @retval EFI_SUCCESS The register was read from Save State\r
165 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor\r
166 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.\r
167\r
168**/\r
169EFI_STATUS\r
170EFIAPI\r
171SmmReadSaveState (\r
172 IN CONST EFI_SMM_CPU_PROTOCOL *This,\r
173 IN UINTN Width,\r
174 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
175 IN UINTN CpuIndex,\r
176 OUT VOID *Buffer\r
177 );\r
178\r
179/**\r
180 Write data to the CPU save state.\r
181\r
182 @param This EFI_SMM_CPU_PROTOCOL instance\r
183 @param Width The number of bytes to read from the CPU save state.\r
184 @param Register Specifies the CPU register to write to the save state.\r
185 @param CpuIndex Specifies the zero-based index of the CPU save state\r
186 @param Buffer Upon entry, this holds the new CPU register value.\r
187\r
188 @retval EFI_SUCCESS The register was written from Save State\r
189 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor\r
190 @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct\r
191\r
192**/\r
193EFI_STATUS\r
194EFIAPI\r
195SmmWriteSaveState (\r
196 IN CONST EFI_SMM_CPU_PROTOCOL *This,\r
197 IN UINTN Width,\r
198 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
199 IN UINTN CpuIndex,\r
200 IN CONST VOID *Buffer\r
201 );\r
202\r
203/**\r
204Read a CPU Save State register on the target processor.\r
205\r
206This function abstracts the differences that whether the CPU Save State register is in the\r
207IA32 CPU Save State Map or X64 CPU Save State Map.\r
208\r
209This function supports reading a CPU Save State register in SMBase relocation handler.\r
210\r
211@param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r
212@param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r
213@param[in] Width The number of bytes to read from the CPU save state.\r
214@param[out] Buffer Upon return, this holds the CPU register value read from the save state.\r
215\r
216@retval EFI_SUCCESS The register was read from Save State.\r
217@retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r
218@retval EFI_INVALID_PARAMTER This or Buffer is NULL.\r
219\r
220**/\r
221EFI_STATUS\r
222EFIAPI\r
223ReadSaveStateRegister (\r
224 IN UINTN CpuIndex,\r
225 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
226 IN UINTN Width,\r
227 OUT VOID *Buffer\r
228 );\r
229\r
230/**\r
231Write value to a CPU Save State register on the target processor.\r
232\r
233This function abstracts the differences that whether the CPU Save State register is in the\r
234IA32 CPU Save State Map or X64 CPU Save State Map.\r
235\r
236This function supports writing a CPU Save State register in SMBase relocation handler.\r
237\r
238@param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r
239@param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r
240@param[in] Width The number of bytes to read from the CPU save state.\r
241@param[in] Buffer Upon entry, this holds the new CPU register value.\r
242\r
243@retval EFI_SUCCESS The register was written to Save State.\r
244@retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r
245@retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct.\r
246\r
247**/\r
248EFI_STATUS\r
249EFIAPI\r
250WriteSaveStateRegister (\r
251 IN UINTN CpuIndex,\r
252 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
253 IN UINTN Width,\r
254 IN CONST VOID *Buffer\r
255 );\r
256\r
257//\r
258//\r
259//\r
260typedef struct {\r
261 UINT32 Offset;\r
262 UINT16 Segment;\r
263 UINT16 Reserved;\r
264} IA32_FAR_ADDRESS;\r
265\r
266extern IA32_FAR_ADDRESS gSmmJmpAddr;\r
267\r
268extern CONST UINT8 gcSmmInitTemplate[];\r
269extern CONST UINT16 gcSmmInitSize;\r
270extern UINT32 gSmmCr0;\r
271extern UINT32 gSmmCr3;\r
272extern UINT32 gSmmCr4;\r
273extern UINTN gSmmInitStack;\r
274\r
275/**\r
276 Semaphore operation for all processor relocate SMMBase.\r
277**/\r
278VOID\r
279EFIAPI\r
280SmmRelocationSemaphoreComplete (\r
281 VOID\r
282 );\r
283\r
284///\r
285/// The type of SMM CPU Information\r
286///\r
287typedef struct {\r
288 SPIN_LOCK Busy;\r
289 volatile EFI_AP_PROCEDURE Procedure;\r
290 volatile VOID *Parameter;\r
291 volatile UINT32 Run;\r
292 volatile BOOLEAN Present;\r
293} SMM_CPU_DATA_BLOCK;\r
294\r
295typedef enum {\r
296 SmmCpuSyncModeTradition,\r
297 SmmCpuSyncModeRelaxedAp,\r
298 SmmCpuSyncModeMax\r
299} SMM_CPU_SYNC_MODE;\r
300\r
301typedef struct {\r
302 //\r
303 // Pointer to an array. The array should be located immediately after this structure\r
304 // so that UC cache-ability can be set together.\r
305 //\r
306 SMM_CPU_DATA_BLOCK *CpuData;\r
307 volatile UINT32 Counter;\r
308 volatile UINT32 BspIndex;\r
309 volatile BOOLEAN InsideSmm;\r
310 volatile BOOLEAN AllCpusInSync;\r
311 volatile SMM_CPU_SYNC_MODE EffectiveSyncMode;\r
312 volatile BOOLEAN SwitchBsp;\r
313 volatile BOOLEAN *CandidateBsp;\r
314} SMM_DISPATCHER_MP_SYNC_DATA;\r
315\r
316typedef struct {\r
317 SPIN_LOCK SpinLock;\r
318 UINT32 MsrIndex;\r
319} MP_MSR_LOCK;\r
320\r
321#define SMM_PSD_OFFSET 0xfb00\r
322\r
323typedef struct {\r
324 UINT64 Signature; // Offset 0x00\r
325 UINT16 Reserved1; // Offset 0x08\r
326 UINT16 Reserved2; // Offset 0x0A\r
327 UINT16 Reserved3; // Offset 0x0C\r
328 UINT16 SmmCs; // Offset 0x0E\r
329 UINT16 SmmDs; // Offset 0x10\r
330 UINT16 SmmSs; // Offset 0x12\r
331 UINT16 SmmOtherSegment; // Offset 0x14\r
332 UINT16 Reserved4; // Offset 0x16\r
333 UINT64 Reserved5; // Offset 0x18\r
334 UINT64 Reserved6; // Offset 0x20\r
335 UINT64 Reserved7; // Offset 0x28\r
336 UINT64 SmmGdtPtr; // Offset 0x30\r
337 UINT32 SmmGdtSize; // Offset 0x38\r
338 UINT32 Reserved8; // Offset 0x3C\r
339 UINT64 Reserved9; // Offset 0x40\r
340 UINT64 Reserved10; // Offset 0x48\r
341 UINT16 Reserved11; // Offset 0x50\r
342 UINT16 Reserved12; // Offset 0x52\r
343 UINT32 Reserved13; // Offset 0x54\r
344 UINT64 MtrrBaseMaskPtr; // Offset 0x58\r
345} PROCESSOR_SMM_DESCRIPTOR;\r
346\r
347extern IA32_DESCRIPTOR gcSmiGdtr;\r
348extern IA32_DESCRIPTOR gcSmiIdtr;\r
349extern VOID *gcSmiIdtrPtr;\r
350extern CONST PROCESSOR_SMM_DESCRIPTOR gcPsd;\r
351extern UINT64 gPhyMask;\r
352extern ACPI_CPU_DATA mAcpiCpuData;\r
353extern SMM_DISPATCHER_MP_SYNC_DATA *mSmmMpSyncData;\r
354extern VOID *mGdtForAp;\r
355extern VOID *mIdtForAp;\r
356extern VOID *mMachineCheckHandlerForAp;\r
357extern UINTN mSmmStackArrayBase;\r
358extern UINTN mSmmStackArrayEnd;\r
359extern UINTN mSmmStackSize;\r
360extern EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService;\r
361extern IA32_DESCRIPTOR gcSmiInitGdtr;\r
362\r
363/**\r
364 Create 4G PageTable in SMRAM.\r
365\r
366 @param ExtraPages Additional page numbers besides for 4G memory\r
367 @return PageTable Address\r
368\r
369**/\r
370UINT32\r
371Gen4GPageTable (\r
372 IN UINTN ExtraPages\r
373 );\r
374\r
375\r
376/**\r
377 Initialize global data for MP synchronization.\r
378\r
379 @param Stacks Base address of SMI stack buffer for all processors.\r
380 @param StackSize Stack size for each processor in SMM.\r
381\r
382**/\r
383UINT32\r
384InitializeMpServiceData (\r
385 IN VOID *Stacks,\r
386 IN UINTN StackSize\r
387 );\r
388\r
389/**\r
390 Initialize Timer for SMM AP Sync.\r
391\r
392**/\r
393VOID\r
394InitializeSmmTimer (\r
395 VOID\r
396 );\r
397\r
398/**\r
399 Start Timer for SMM AP Sync.\r
400\r
401**/\r
402UINT64\r
403EFIAPI\r
404StartSyncTimer (\r
405 VOID\r
406 );\r
407\r
408/**\r
409 Check if the SMM AP Sync timer is timeout.\r
410\r
411 @param Timer The start timer from the begin.\r
412\r
413**/\r
414BOOLEAN\r
415EFIAPI\r
416IsSyncTimerTimeout (\r
417 IN UINT64 Timer\r
418 );\r
419\r
420/**\r
421 Initialize IDT for SMM Stack Guard.\r
422\r
423**/\r
424VOID\r
425EFIAPI\r
426InitializeIDTSmmStackGuard (\r
427 VOID\r
428 );\r
429\r
fe5f1949
JY		 430/**\r
431 Initialize Gdt for all processors.\r
432 \r
433 @param[in] Cr3 CR3 value.\r
434 @param[out] GdtStepSize The step size for GDT table.\r
435\r
436 @return GdtBase for processor 0.\r
437 GdtBase for processor X is: GdtBase + (GdtStepSize * X)\r
438**/\r
439VOID *\r
440InitGdt (\r
441 IN UINTN Cr3,\r
442 OUT UINTN *GdtStepSize\r
443 );\r
444\r
529a5a86
MK		 445/**\r
446\r
447 Register the SMM Foundation entry point.\r
448\r
449 @param This Pointer to EFI_SMM_CONFIGURATION_PROTOCOL instance\r
450 @param SmmEntryPoint SMM Foundation EntryPoint\r
451\r
452 @retval EFI_SUCCESS Successfully to register SMM foundation entry point\r
453\r
454**/\r
455EFI_STATUS\r
456EFIAPI\r
457RegisterSmmEntry (\r
458 IN CONST EFI_SMM_CONFIGURATION_PROTOCOL *This,\r
459 IN EFI_SMM_ENTRY_POINT SmmEntryPoint\r
460 );\r
461\r
462/**\r
463 Create PageTable for SMM use.\r
464\r
465 @return PageTable Address\r
466\r
467**/\r
468UINT32\r
469SmmInitPageTable (\r
470 VOID\r
471 );\r
472\r
473/**\r
474 Schedule a procedure to run on the specified CPU.\r
475\r
476 @param Procedure The address of the procedure to run\r
477 @param CpuIndex Target CPU number\r
478 @param ProcArguments The parameter to pass to the procedure\r
479\r
480 @retval EFI_INVALID_PARAMETER CpuNumber not valid\r
481 @retval EFI_INVALID_PARAMETER CpuNumber specifying BSP\r
482 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM\r
483 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy\r
484 @retval EFI_SUCCESS - The procedure has been successfully scheduled\r
485\r
486**/\r
487EFI_STATUS\r
488EFIAPI\r
489SmmStartupThisAp (\r
490 IN EFI_AP_PROCEDURE Procedure,\r
491 IN UINTN CpuIndex,\r
492 IN OUT VOID *ProcArguments OPTIONAL\r
493 );\r
494\r
495/**\r
496 Schedule a procedure to run on the specified CPU in a blocking fashion.\r
497\r
498 @param Procedure The address of the procedure to run\r
499 @param CpuIndex Target CPU Index\r
500 @param ProcArguments The parameter to pass to the procedure\r
501\r
502 @retval EFI_INVALID_PARAMETER CpuNumber not valid\r
503 @retval EFI_INVALID_PARAMETER CpuNumber specifying BSP\r
504 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM\r
505 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy\r
506 @retval EFI_SUCCESS The procedure has been successfully scheduled\r
507\r
508**/\r
509EFI_STATUS\r
510EFIAPI\r
511SmmBlockingStartupThisAp (\r
512 IN EFI_AP_PROCEDURE Procedure,\r
513 IN UINTN CpuIndex,\r
514 IN OUT VOID *ProcArguments OPTIONAL\r
515 );\r
516\r
517/**\r
518 Initialize MP synchronization data.\r
519\r
520**/\r
521VOID\r
522EFIAPI\r
523InitializeMpSyncData (\r
524 VOID\r
525 );\r
526\r
527/**\r
528\r
529 Find out SMRAM information including SMRR base and SMRR size.\r
530\r
531 @param SmrrBase SMRR base\r
532 @param SmrrSize SMRR size\r
533\r
534**/\r
535VOID\r
536FindSmramInfo (\r
537 OUT UINT32 *SmrrBase,\r
538 OUT UINT32 *SmrrSize\r
539 );\r
540\r
541/**\r
542 The function is invoked before SMBASE relocation in S3 path to restores CPU status.\r
543\r
544 The function is invoked before SMBASE relocation in S3 path. It does first time microcode load\r
545 and restores MTRRs for both BSP and APs.\r
546\r
547**/\r
548VOID\r
549EarlyInitializeCpu (\r
550 VOID\r
551 );\r
552\r
553/**\r
554 The function is invoked after SMBASE relocation in S3 path to restores CPU status.\r
555\r
556 The function is invoked after SMBASE relocation in S3 path. It restores configuration according to\r
557 data saved by normal boot path for both BSP and APs.\r
558\r
559**/\r
560VOID\r
561InitializeCpu (\r
562 VOID\r
563 );\r
564\r
565/**\r
566 Page Fault handler for SMM use.\r
567\r
568 @param InterruptType Defines the type of interrupt or exception that\r
569 occurred on the processor.This parameter is processor architecture specific.\r
570 @param SystemContext A pointer to the processor context when\r
571 the interrupt occurred on the processor.\r
572**/\r
573VOID\r
574EFIAPI\r
575SmiPFHandler (\r
576 IN EFI_EXCEPTION_TYPE InterruptType,\r
577 IN EFI_SYSTEM_CONTEXT SystemContext\r
578 );\r
579\r
580/**\r
581 Perform the remaining tasks.\r
582\r
583**/\r
584VOID\r
585PerformRemainingTasks (\r
586 VOID\r
587 );\r
588\r
9f419739
JY		 589/**\r
590 Perform the pre tasks.\r
591\r
592**/\r
593VOID\r
594PerformPreTasks (\r
595 VOID\r
596 );\r
597\r
529a5a86
MK		 598/**\r
599 Initialize MSR spin lock by MSR index.\r
600\r
601 @param MsrIndex MSR index value.\r
602\r
603**/\r
604VOID\r
605InitMsrSpinLockByIndex (\r
606 IN UINT32 MsrIndex\r
607 );\r
608\r
609/**\r
610 Hook return address of SMM Save State so that semaphore code\r
611 can be executed immediately after AP exits SMM to indicate to\r
612 the BSP that an AP has exited SMM after SMBASE relocation.\r
613\r
614 @param[in] CpuIndex The processor index.\r
615 @param[in] RebasedFlag A pointer to a flag that is set to TRUE\r
616 immediately after AP exits SMM.\r
617\r
618**/\r
619VOID\r
620SemaphoreHook (\r
621 IN UINTN CpuIndex,\r
622 IN volatile BOOLEAN *RebasedFlag\r
623 );\r
624\r
625/**\r
626Configure SMM Code Access Check feature for all processors.\r
627SMM Feature Control MSR will be locked after configuration.\r
628**/\r
629VOID\r
630ConfigSmmCodeAccessCheck (\r
631 VOID\r
632 );\r
633\r
634/**\r
635 Hook the code executed immediately after an RSM instruction on the currently\r
636 executing CPU. The mode of code executed immediately after RSM must be\r
637 detected, and the appropriate hook must be selected. Always clear the auto\r
638 HALT restart flag if it is set.\r
639\r
640 @param[in] CpuIndex The processor index for the currently\r
641 executing CPU.\r
642 @param[in] CpuState Pointer to SMRAM Save State Map for the\r
643 currently executing CPU.\r
644 @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to\r
645 32-bit mode from 64-bit SMM.\r
646 @param[in] NewInstructionPointer Instruction pointer to use if resuming to\r
647 same mode as SMM.\r
648\r
649 @retval The value of the original instruction pointer before it was hooked.\r
650\r
651**/\r
652UINT64\r
653EFIAPI\r
654HookReturnFromSmm (\r
655 IN UINTN CpuIndex,\r
656 SMRAM_SAVE_STATE_MAP *CpuState,\r
657 UINT64 NewInstructionPointer32,\r
658 UINT64 NewInstructionPointer\r
659 );\r
660\r
661/**\r
662 Get the size of the SMI Handler in bytes.\r
663\r
664 @retval The size, in bytes, of the SMI Handler.\r
665\r
666**/\r
667UINTN\r
668EFIAPI\r
669GetSmiHandlerSize (\r
670 VOID\r
671 );\r
672\r
673/**\r
674 Install the SMI handler for the CPU specified by CpuIndex. This function\r
675 is called by the CPU that was elected as monarch during System Management\r
676 Mode initialization.\r
677\r
678 @param[in] CpuIndex The index of the CPU to install the custom SMI handler.\r
679 The value must be between 0 and the NumberOfCpus field\r
680 in the System Management System Table (SMST).\r
681 @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.\r
682 @param[in] SmiStack The stack to use when an SMI is processed by the\r
683 the CPU specified by CpuIndex.\r
684 @param[in] StackSize The size, in bytes, if the stack used when an SMI is\r
685 processed by the CPU specified by CpuIndex.\r
686 @param[in] GdtBase The base address of the GDT to use when an SMI is\r
687 processed by the CPU specified by CpuIndex.\r
688 @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is\r
689 processed by the CPU specified by CpuIndex.\r
690 @param[in] IdtBase The base address of the IDT to use when an SMI is\r
691 processed by the CPU specified by CpuIndex.\r
692 @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is\r
693 processed by the CPU specified by CpuIndex.\r
694 @param[in] Cr3 The base address of the page tables to use when an SMI\r
695 is processed by the CPU specified by CpuIndex.\r
696**/\r
697VOID\r
698EFIAPI\r
699InstallSmiHandler (\r
700 IN UINTN CpuIndex,\r
701 IN UINT32 SmBase,\r
702 IN VOID *SmiStack,\r
703 IN UINTN StackSize,\r
704 IN UINTN GdtBase,\r
705 IN UINTN GdtSize,\r
706 IN UINTN IdtBase,\r
707 IN UINTN IdtSize,\r
708 IN UINT32 Cr3\r
709 );\r
710\r
711/**\r
712 Search module name by input IP address and output it.\r
713\r
714 @param CallerIpAddress Caller instruction pointer.\r
715\r
716**/\r
717VOID\r
718DumpModuleInfoByIp (\r
719 IN UINTN CallerIpAddress\r
720 );\r
721#endif\r
EFI Development Kit II mirror for PVE