projects / mirror_edk2.git / blame
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| 529a5a86 MK |
1 | /** @file\r |
| 2 | Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.\r | |
| 3 | \r | |
| f85d3ce2 | 4 | Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r |
| 529a5a86 MK |
5 | This program and the accompanying materials\r |
| 6 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 7 | which accompanies this distribution. The full text of the license may be found at\r | |
| 8 | http://opensource.org/licenses/bsd-license.php\r | |
| 9 | \r | |
| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 12 | \r | |
| 13 | **/\r | |
| 14 | \r | |
| 15 | #ifndef _CPU_PISMMCPUDXESMM_H_\r | |
| 16 | #define _CPU_PISMMCPUDXESMM_H_\r | |
| 17 | \r | |
| 18 | #include <PiSmm.h>\r | |
| 19 | \r | |
| 20 | #include <Protocol/MpService.h>\r | |
| 21 | #include <Protocol/SmmConfiguration.h>\r | |
| 22 | #include <Protocol/SmmCpu.h>\r | |
| 23 | #include <Protocol/SmmAccess2.h>\r | |
| 529a5a86 MK |
24 | #include <Protocol/SmmReadyToLock.h>\r |
| 25 | #include <Protocol/SmmCpuService.h>\r | |
| 26 | \r | |
| 27 | #include <Guid/AcpiS3Context.h>\r | |
| 28 | \r | |
| 29 | #include <Library/BaseLib.h>\r | |
| 30 | #include <Library/IoLib.h>\r | |
| 31 | #include <Library/TimerLib.h>\r | |
| 529a5a86 MK |
32 | #include <Library/SynchronizationLib.h>\r |
| 33 | #include <Library/DebugLib.h>\r | |
| 34 | #include <Library/BaseMemoryLib.h>\r | |
| 35 | #include <Library/PcdLib.h>\r | |
| 36 | #include <Library/CacheMaintenanceLib.h>\r | |
| 37 | #include <Library/MtrrLib.h>\r | |
| 38 | #include <Library/SmmCpuPlatformHookLib.h>\r | |
| 39 | #include <Library/SmmServicesTableLib.h>\r | |
| 40 | #include <Library/MemoryAllocationLib.h>\r | |
| 41 | #include <Library/UefiBootServicesTableLib.h>\r | |
| 42 | #include <Library/UefiRuntimeServicesTableLib.h>\r | |
| 43 | #include <Library/DebugAgentLib.h>\r | |
| 44 | #include <Library/HobLib.h>\r | |
| 45 | #include <Library/LocalApicLib.h>\r | |
| 46 | #include <Library/UefiCpuLib.h>\r | |
| 47 | #include <Library/CpuExceptionHandlerLib.h>\r | |
| 48 | #include <Library/ReportStatusCodeLib.h>\r | |
| 49 | #include <Library/SmmCpuFeaturesLib.h>\r | |
| 50 | #include <Library/PeCoffGetEntryPointLib.h>\r | |
| 51 | \r | |
| 52 | #include <AcpiCpuData.h>\r | |
| 53 | #include <CpuHotPlugData.h>\r | |
| 54 | \r | |
| 55 | #include <Register/Cpuid.h>\r | |
| f85d3ce2 | 56 | #include <Register/Msr.h>\r |
| 529a5a86 MK |
57 | \r |
| 58 | #include "CpuService.h"\r | |
| 59 | #include "SmmProfile.h"\r | |
| 60 | \r | |
| 61 | //\r | |
| 62 | // MSRs required for configuration of SMM Code Access Check\r | |
| 63 | //\r | |
| 64 | #define EFI_MSR_SMM_MCA_CAP 0x17D\r | |
| 65 | #define SMM_CODE_ACCESS_CHK_BIT BIT58\r | |
| 66 | \r | |
| 67 | #define SMM_FEATURE_CONTROL_LOCK_BIT BIT0\r | |
| 68 | #define SMM_CODE_CHK_EN_BIT BIT2\r | |
| 69 | \r | |
| 70 | ///\r | |
| 71 | /// Page Table Entry\r | |
| 72 | ///\r | |
| 73 | #define IA32_PG_P BIT0\r | |
| 74 | #define IA32_PG_RW BIT1\r | |
| 881520ea | 75 | #define IA32_PG_U BIT2\r |
| 529a5a86 MK |
76 | #define IA32_PG_WT BIT3\r |
| 77 | #define IA32_PG_CD BIT4\r | |
| 78 | #define IA32_PG_A BIT5\r | |
| 881520ea | 79 | #define IA32_PG_D BIT6\r |
| 529a5a86 MK |
80 | #define IA32_PG_PS BIT7\r |
| 81 | #define IA32_PG_PAT_2M BIT12\r | |
| 82 | #define IA32_PG_PAT_4K IA32_PG_PS\r | |
| 83 | #define IA32_PG_PMNT BIT62\r | |
| 84 | #define IA32_PG_NX BIT63\r | |
| 85 | \r | |
| 881520ea JY |
86 | #define PAGE_ATTRIBUTE_BITS (IA32_PG_RW | IA32_PG_P)\r |
| 87 | //\r | |
| 88 | // Bits 1, 2, 5, 6 are reserved in the IA32 PAE PDPTE\r | |
| 89 | // X64 PAE PDPTE does not have such restriction\r | |
| 90 | //\r | |
| 91 | #define IA32_PAE_PDPTE_ATTRIBUTE_BITS (IA32_PG_P)\r | |
| 92 | \r | |
| 529a5a86 MK |
93 | //\r |
| 94 | // Size of Task-State Segment defined in IA32 Manual\r | |
| 95 | //\r | |
| 96 | #define TSS_SIZE 104\r | |
| 97 | #define TSS_X64_IST1_OFFSET 36\r | |
| 98 | #define TSS_IA32_CR3_OFFSET 28\r | |
| 99 | #define TSS_IA32_ESP_OFFSET 56\r | |
| 100 | \r | |
| 101 | //\r | |
| 102 | // Code select value\r | |
| 103 | //\r | |
| 104 | #define PROTECT_MODE_CODE_SEGMENT 0x08\r | |
| 105 | #define LONG_MODE_CODE_SEGMENT 0x38\r | |
| 106 | \r | |
| 107 | //\r | |
| 108 | // The size 0x20 must be bigger than\r | |
| 109 | // the size of template code of SmmInit. Currently,\r | |
| 110 | // the size of SmmInit requires the 0x16 Bytes buffer\r | |
| 111 | // at least.\r | |
| 112 | //\r | |
| 113 | #define BACK_BUF_SIZE 0x20\r | |
| 114 | \r | |
| 115 | #define EXCEPTION_VECTOR_NUMBER 0x20\r | |
| 116 | \r | |
| 117 | #define INVALID_APIC_ID 0xFFFFFFFFFFFFFFFFULL\r | |
| 118 | \r | |
| 119 | typedef UINT32 SMM_CPU_ARRIVAL_EXCEPTIONS;\r | |
| 120 | #define ARRIVAL_EXCEPTION_BLOCKED 0x1\r | |
| 121 | #define ARRIVAL_EXCEPTION_DELAYED 0x2\r | |
| 122 | #define ARRIVAL_EXCEPTION_SMI_DISABLED 0x4\r | |
| 123 | \r | |
| 124 | //\r | |
| 125 | // Private structure for the SMM CPU module that is stored in DXE Runtime memory\r | |
| 126 | // Contains the SMM Configuration Protocols that is produced.\r | |
| 127 | // Contains a mix of DXE and SMM contents. All the fields must be used properly.\r | |
| 128 | //\r | |
| 129 | #define SMM_CPU_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('s', 'c', 'p', 'u')\r | |
| 130 | \r | |
| 131 | typedef struct {\r | |
| 132 | UINTN Signature;\r | |
| 133 | \r | |
| 134 | EFI_HANDLE SmmCpuHandle;\r | |
| 135 | \r | |
| 136 | EFI_PROCESSOR_INFORMATION *ProcessorInfo;\r | |
| 137 | SMM_CPU_OPERATION *Operation;\r | |
| 138 | UINTN *CpuSaveStateSize;\r | |
| 139 | VOID **CpuSaveState;\r | |
| 140 | \r | |
| 141 | EFI_SMM_RESERVED_SMRAM_REGION SmmReservedSmramRegion[1];\r | |
| 142 | EFI_SMM_ENTRY_CONTEXT SmmCoreEntryContext;\r | |
| 143 | EFI_SMM_ENTRY_POINT SmmCoreEntry;\r | |
| 144 | \r | |
| 145 | EFI_SMM_CONFIGURATION_PROTOCOL SmmConfiguration;\r | |
| 146 | } SMM_CPU_PRIVATE_DATA;\r | |
| 147 | \r | |
| 148 | extern SMM_CPU_PRIVATE_DATA *gSmmCpuPrivate;\r | |
| 149 | extern CPU_HOT_PLUG_DATA mCpuHotPlugData;\r | |
| 150 | extern UINTN mMaxNumberOfCpus;\r | |
| 151 | extern UINTN mNumberOfCpus;\r | |
| 152 | extern BOOLEAN mRestoreSmmConfigurationInS3;\r | |
| 153 | extern EFI_SMM_CPU_PROTOCOL mSmmCpu;\r | |
| 154 | \r | |
| 155 | ///\r | |
| 156 | /// The mode of the CPU at the time an SMI occurs\r | |
| 157 | ///\r | |
| 158 | extern UINT8 mSmmSaveStateRegisterLma;\r | |
| 159 | \r | |
| 160 | \r | |
| 161 | //\r | |
| 162 | // SMM CPU Protocol function prototypes.\r | |
| 163 | //\r | |
| 164 | \r | |
| 165 | /**\r | |
| 166 | Read information from the CPU save state.\r | |
| 167 | \r | |
| 168 | @param This EFI_SMM_CPU_PROTOCOL instance\r | |
| 169 | @param Width The number of bytes to read from the CPU save state.\r | |
| 170 | @param Register Specifies the CPU register to read form the save state.\r | |
| 171 | @param CpuIndex Specifies the zero-based index of the CPU save state\r | |
| 172 | @param Buffer Upon return, this holds the CPU register value read from the save state.\r | |
| 173 | \r | |
| 174 | @retval EFI_SUCCESS The register was read from Save State\r | |
| 175 | @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor\r | |
| 176 | @retval EFI_INVALID_PARAMTER This or Buffer is NULL.\r | |
| 177 | \r | |
| 178 | **/\r | |
| 179 | EFI_STATUS\r | |
| 180 | EFIAPI\r | |
| 181 | SmmReadSaveState (\r | |
| 182 | IN CONST EFI_SMM_CPU_PROTOCOL *This,\r | |
| 183 | IN UINTN Width,\r | |
| 184 | IN EFI_SMM_SAVE_STATE_REGISTER Register,\r | |
| 185 | IN UINTN CpuIndex,\r | |
| 186 | OUT VOID *Buffer\r | |
| 187 | );\r | |
| 188 | \r | |
| 189 | /**\r | |
| 190 | Write data to the CPU save state.\r | |
| 191 | \r | |
| 192 | @param This EFI_SMM_CPU_PROTOCOL instance\r | |
| 193 | @param Width The number of bytes to read from the CPU save state.\r | |
| 194 | @param Register Specifies the CPU register to write to the save state.\r | |
| 195 | @param CpuIndex Specifies the zero-based index of the CPU save state\r | |
| 196 | @param Buffer Upon entry, this holds the new CPU register value.\r | |
| 197 | \r | |
| 198 | @retval EFI_SUCCESS The register was written from Save State\r | |
| 199 | @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor\r | |
| 200 | @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct\r | |
| 201 | \r | |
| 202 | **/\r | |
| 203 | EFI_STATUS\r | |
| 204 | EFIAPI\r | |
| 205 | SmmWriteSaveState (\r | |
| 206 | IN CONST EFI_SMM_CPU_PROTOCOL *This,\r | |
| 207 | IN UINTN Width,\r | |
| 208 | IN EFI_SMM_SAVE_STATE_REGISTER Register,\r | |
| 209 | IN UINTN CpuIndex,\r | |
| 210 | IN CONST VOID *Buffer\r | |
| 211 | );\r | |
| 212 | \r | |
| 213 | /**\r | |
| 214 | Read a CPU Save State register on the target processor.\r | |
| 215 | \r | |
| 216 | This function abstracts the differences that whether the CPU Save State register is in the\r | |
| 217 | IA32 CPU Save State Map or X64 CPU Save State Map.\r | |
| 218 | \r | |
| 219 | This function supports reading a CPU Save State register in SMBase relocation handler.\r | |
| 220 | \r | |
| 221 | @param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r | |
| 222 | @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r | |
| 223 | @param[in] Width The number of bytes to read from the CPU save state.\r | |
| 224 | @param[out] Buffer Upon return, this holds the CPU register value read from the save state.\r | |
| 225 | \r | |
| 226 | @retval EFI_SUCCESS The register was read from Save State.\r | |
| 227 | @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r | |
| 228 | @retval EFI_INVALID_PARAMTER This or Buffer is NULL.\r | |
| 229 | \r | |
| 230 | **/\r | |
| 231 | EFI_STATUS\r | |
| 232 | EFIAPI\r | |
| 233 | ReadSaveStateRegister (\r | |
| 234 | IN UINTN CpuIndex,\r | |
| 235 | IN EFI_SMM_SAVE_STATE_REGISTER Register,\r | |
| 236 | IN UINTN Width,\r | |
| 237 | OUT VOID *Buffer\r | |
| 238 | );\r | |
| 239 | \r | |
| 240 | /**\r | |
| 241 | Write value to a CPU Save State register on the target processor.\r | |
| 242 | \r | |
| 243 | This function abstracts the differences that whether the CPU Save State register is in the\r | |
| 244 | IA32 CPU Save State Map or X64 CPU Save State Map.\r | |
| 245 | \r | |
| 246 | This function supports writing a CPU Save State register in SMBase relocation handler.\r | |
| 247 | \r | |
| 248 | @param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r | |
| 249 | @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r | |
| 250 | @param[in] Width The number of bytes to read from the CPU save state.\r | |
| 251 | @param[in] Buffer Upon entry, this holds the new CPU register value.\r | |
| 252 | \r | |
| 253 | @retval EFI_SUCCESS The register was written to Save State.\r | |
| 254 | @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r | |
| 255 | @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct.\r | |
| 256 | \r | |
| 257 | **/\r | |
| 258 | EFI_STATUS\r | |
| 259 | EFIAPI\r | |
| 260 | WriteSaveStateRegister (\r | |
| 261 | IN UINTN CpuIndex,\r | |
| 262 | IN EFI_SMM_SAVE_STATE_REGISTER Register,\r | |
| 263 | IN UINTN Width,\r | |
| 264 | IN CONST VOID *Buffer\r | |
| 265 | );\r | |
| 266 | \r | |
| 267 | //\r | |
| 268 | //\r | |
| 269 | //\r | |
| 270 | typedef struct {\r | |
| 271 | UINT32 Offset;\r | |
| 272 | UINT16 Segment;\r | |
| 273 | UINT16 Reserved;\r | |
| 274 | } IA32_FAR_ADDRESS;\r | |
| 275 | \r | |
| 276 | extern IA32_FAR_ADDRESS gSmmJmpAddr;\r | |
| 277 | \r | |
| 278 | extern CONST UINT8 gcSmmInitTemplate[];\r | |
| 279 | extern CONST UINT16 gcSmmInitSize;\r | |
| 280 | extern UINT32 gSmmCr0;\r | |
| 281 | extern UINT32 gSmmCr3;\r | |
| 282 | extern UINT32 gSmmCr4;\r | |
| 283 | extern UINTN gSmmInitStack;\r | |
| 284 | \r | |
| 285 | /**\r | |
| 286 | Semaphore operation for all processor relocate SMMBase.\r | |
| 287 | **/\r | |
| 288 | VOID\r | |
| 289 | EFIAPI\r | |
| 290 | SmmRelocationSemaphoreComplete (\r | |
| 291 | VOID\r | |
| 292 | );\r | |
| 293 | \r | |
| 294 | ///\r | |
| 295 | /// The type of SMM CPU Information\r | |
| 296 | ///\r | |
| 297 | typedef struct {\r | |
| ed3d5ecb | 298 | SPIN_LOCK *Busy;\r |
| 529a5a86 MK |
299 | volatile EFI_AP_PROCEDURE Procedure;\r |
| 300 | volatile VOID *Parameter;\r | |
| ed3d5ecb JF |
301 | volatile UINT32 *Run;\r |
| 302 | volatile BOOLEAN *Present;\r | |
| 529a5a86 MK |
303 | } SMM_CPU_DATA_BLOCK;\r |
| 304 | \r | |
| 305 | typedef enum {\r | |
| 306 | SmmCpuSyncModeTradition,\r | |
| 307 | SmmCpuSyncModeRelaxedAp,\r | |
| 308 | SmmCpuSyncModeMax\r | |
| 309 | } SMM_CPU_SYNC_MODE;\r | |
| 310 | \r | |
| 311 | typedef struct {\r | |
| 312 | //\r | |
| 313 | // Pointer to an array. The array should be located immediately after this structure\r | |
| 314 | // so that UC cache-ability can be set together.\r | |
| 315 | //\r | |
| 316 | SMM_CPU_DATA_BLOCK *CpuData;\r | |
| fe3a75bc | 317 | volatile UINT32 *Counter;\r |
| 529a5a86 | 318 | volatile UINT32 BspIndex;\r |
| fe3a75bc JF |
319 | volatile BOOLEAN *InsideSmm;\r |
| 320 | volatile BOOLEAN *AllCpusInSync;\r | |
| 529a5a86 MK |
321 | volatile SMM_CPU_SYNC_MODE EffectiveSyncMode;\r |
| 322 | volatile BOOLEAN SwitchBsp;\r | |
| 323 | volatile BOOLEAN *CandidateBsp;\r | |
| 324 | } SMM_DISPATCHER_MP_SYNC_DATA;\r | |
| 325 | \r | |
| 326 | typedef struct {\r | |
| 327 | SPIN_LOCK SpinLock;\r | |
| 328 | UINT32 MsrIndex;\r | |
| 329 | } MP_MSR_LOCK;\r | |
| 330 | \r | |
| 331 | #define SMM_PSD_OFFSET 0xfb00\r | |
| 332 | \r | |
| 333 | typedef struct {\r | |
| 334 | UINT64 Signature; // Offset 0x00\r | |
| 335 | UINT16 Reserved1; // Offset 0x08\r | |
| 336 | UINT16 Reserved2; // Offset 0x0A\r | |
| 337 | UINT16 Reserved3; // Offset 0x0C\r | |
| 338 | UINT16 SmmCs; // Offset 0x0E\r | |
| 339 | UINT16 SmmDs; // Offset 0x10\r | |
| 340 | UINT16 SmmSs; // Offset 0x12\r | |
| 341 | UINT16 SmmOtherSegment; // Offset 0x14\r | |
| 342 | UINT16 Reserved4; // Offset 0x16\r | |
| 343 | UINT64 Reserved5; // Offset 0x18\r | |
| 344 | UINT64 Reserved6; // Offset 0x20\r | |
| 345 | UINT64 Reserved7; // Offset 0x28\r | |
| 346 | UINT64 SmmGdtPtr; // Offset 0x30\r | |
| 347 | UINT32 SmmGdtSize; // Offset 0x38\r | |
| 348 | UINT32 Reserved8; // Offset 0x3C\r | |
| 349 | UINT64 Reserved9; // Offset 0x40\r | |
| 350 | UINT64 Reserved10; // Offset 0x48\r | |
| 351 | UINT16 Reserved11; // Offset 0x50\r | |
| 352 | UINT16 Reserved12; // Offset 0x52\r | |
| 353 | UINT32 Reserved13; // Offset 0x54\r | |
| 354 | UINT64 MtrrBaseMaskPtr; // Offset 0x58\r | |
| 355 | } PROCESSOR_SMM_DESCRIPTOR;\r | |
| 356 | \r | |
| 1d648531 JF |
357 | \r |
| 358 | ///\r | |
| 359 | /// All global semaphores' pointer\r | |
| 360 | ///\r | |
| 361 | typedef struct {\r | |
| 362 | volatile UINT32 *Counter;\r | |
| 363 | volatile BOOLEAN *InsideSmm;\r | |
| 364 | volatile BOOLEAN *AllCpusInSync;\r | |
| 365 | SPIN_LOCK *PFLock;\r | |
| 366 | SPIN_LOCK *CodeAccessCheckLock;\r | |
| 367 | } SMM_CPU_SEMAPHORE_GLOBAL;\r | |
| 368 | \r | |
| 4e920581 JF |
369 | ///\r |
| 370 | /// All semaphores for each processor\r | |
| 371 | ///\r | |
| 372 | typedef struct {\r | |
| 373 | SPIN_LOCK *Busy;\r | |
| 374 | volatile UINT32 *Run;\r | |
| 375 | volatile BOOLEAN *Present;\r | |
| 376 | } SMM_CPU_SEMAPHORE_CPU;\r | |
| 377 | \r | |
| 378 | \r | |
| 1d648531 JF |
379 | ///\r |
| 380 | /// All semaphores' information\r | |
| 381 | ///\r | |
| 382 | typedef struct {\r | |
| 383 | SMM_CPU_SEMAPHORE_GLOBAL SemaphoreGlobal;\r | |
| 4e920581 | 384 | SMM_CPU_SEMAPHORE_CPU SemaphoreCpu;\r |
| 1d648531 JF |
385 | } SMM_CPU_SEMAPHORES;\r |
| 386 | \r | |
| 529a5a86 MK |
387 | extern IA32_DESCRIPTOR gcSmiGdtr;\r |
| 388 | extern IA32_DESCRIPTOR gcSmiIdtr;\r | |
| 389 | extern VOID *gcSmiIdtrPtr;\r | |
| 390 | extern CONST PROCESSOR_SMM_DESCRIPTOR gcPsd;\r | |
| 391 | extern UINT64 gPhyMask;\r | |
| 392 | extern ACPI_CPU_DATA mAcpiCpuData;\r | |
| 393 | extern SMM_DISPATCHER_MP_SYNC_DATA *mSmmMpSyncData;\r | |
| 394 | extern VOID *mGdtForAp;\r | |
| 395 | extern VOID *mIdtForAp;\r | |
| 396 | extern VOID *mMachineCheckHandlerForAp;\r | |
| 397 | extern UINTN mSmmStackArrayBase;\r | |
| 398 | extern UINTN mSmmStackArrayEnd;\r | |
| 399 | extern UINTN mSmmStackSize;\r | |
| 400 | extern EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService;\r | |
| 401 | extern IA32_DESCRIPTOR gcSmiInitGdtr;\r | |
| fe3a75bc JF |
402 | extern SPIN_LOCK *mPFLock;\r |
| 403 | extern SPIN_LOCK *mConfigSmmCodeAccessCheckLock;\r | |
| 529a5a86 MK |
404 | \r |
| 405 | /**\r | |
| 406 | Create 4G PageTable in SMRAM.\r | |
| 407 | \r | |
| 408 | @param ExtraPages Additional page numbers besides for 4G memory\r | |
| 881520ea | 409 | @param Is32BitPageTable Whether the page table is 32-bit PAE\r |
| 529a5a86 MK |
410 | @return PageTable Address\r |
| 411 | \r | |
| 412 | **/\r | |
| 413 | UINT32\r | |
| 414 | Gen4GPageTable (\r | |
| 881520ea JY |
415 | IN UINTN ExtraPages,\r |
| 416 | IN BOOLEAN Is32BitPageTable\r | |
| 529a5a86 MK |
417 | );\r |
| 418 | \r | |
| 419 | \r | |
| 420 | /**\r | |
| 421 | Initialize global data for MP synchronization.\r | |
| 422 | \r | |
| 423 | @param Stacks Base address of SMI stack buffer for all processors.\r | |
| 424 | @param StackSize Stack size for each processor in SMM.\r | |
| 425 | \r | |
| 426 | **/\r | |
| 427 | UINT32\r | |
| 428 | InitializeMpServiceData (\r | |
| 429 | IN VOID *Stacks,\r | |
| 430 | IN UINTN StackSize\r | |
| 431 | );\r | |
| 432 | \r | |
| 433 | /**\r | |
| 434 | Initialize Timer for SMM AP Sync.\r | |
| 435 | \r | |
| 436 | **/\r | |
| 437 | VOID\r | |
| 438 | InitializeSmmTimer (\r | |
| 439 | VOID\r | |
| 440 | );\r | |
| 441 | \r | |
| 442 | /**\r | |
| 443 | Start Timer for SMM AP Sync.\r | |
| 444 | \r | |
| 445 | **/\r | |
| 446 | UINT64\r | |
| 447 | EFIAPI\r | |
| 448 | StartSyncTimer (\r | |
| 449 | VOID\r | |
| 450 | );\r | |
| 451 | \r | |
| 452 | /**\r | |
| 453 | Check if the SMM AP Sync timer is timeout.\r | |
| 454 | \r | |
| 455 | @param Timer The start timer from the begin.\r | |
| 456 | \r | |
| 457 | **/\r | |
| 458 | BOOLEAN\r | |
| 459 | EFIAPI\r | |
| 460 | IsSyncTimerTimeout (\r | |
| 461 | IN UINT64 Timer\r | |
| 462 | );\r | |
| 463 | \r | |
| 464 | /**\r | |
| 465 | Initialize IDT for SMM Stack Guard.\r | |
| 466 | \r | |
| 467 | **/\r | |
| 468 | VOID\r | |
| 469 | EFIAPI\r | |
| 470 | InitializeIDTSmmStackGuard (\r | |
| 471 | VOID\r | |
| 472 | );\r | |
| 473 | \r | |
| fe5f1949 JY |
474 | /**\r |
| 475 | Initialize Gdt for all processors.\r | |
| 476 | \r | |
| 477 | @param[in] Cr3 CR3 value.\r | |
| 478 | @param[out] GdtStepSize The step size for GDT table.\r | |
| 479 | \r | |
| 480 | @return GdtBase for processor 0.\r | |
| 481 | GdtBase for processor X is: GdtBase + (GdtStepSize * X)\r | |
| 482 | **/\r | |
| 483 | VOID *\r | |
| 484 | InitGdt (\r | |
| 485 | IN UINTN Cr3,\r | |
| 486 | OUT UINTN *GdtStepSize\r | |
| 487 | );\r | |
| 488 | \r | |
| 529a5a86 MK |
489 | /**\r |
| 490 | \r | |
| 491 | Register the SMM Foundation entry point.\r | |
| 492 | \r | |
| 493 | @param This Pointer to EFI_SMM_CONFIGURATION_PROTOCOL instance\r | |
| 494 | @param SmmEntryPoint SMM Foundation EntryPoint\r | |
| 495 | \r | |
| 496 | @retval EFI_SUCCESS Successfully to register SMM foundation entry point\r | |
| 497 | \r | |
| 498 | **/\r | |
| 499 | EFI_STATUS\r | |
| 500 | EFIAPI\r | |
| 501 | RegisterSmmEntry (\r | |
| 502 | IN CONST EFI_SMM_CONFIGURATION_PROTOCOL *This,\r | |
| 503 | IN EFI_SMM_ENTRY_POINT SmmEntryPoint\r | |
| 504 | );\r | |
| 505 | \r | |
| 506 | /**\r | |
| 507 | Create PageTable for SMM use.\r | |
| 508 | \r | |
| 509 | @return PageTable Address\r | |
| 510 | \r | |
| 511 | **/\r | |
| 512 | UINT32\r | |
| 513 | SmmInitPageTable (\r | |
| 514 | VOID\r | |
| 515 | );\r | |
| 516 | \r | |
| 517 | /**\r | |
| 518 | Schedule a procedure to run on the specified CPU.\r | |
| 519 | \r | |
| 520 | @param Procedure The address of the procedure to run\r | |
| 521 | @param CpuIndex Target CPU number\r | |
| 522 | @param ProcArguments The parameter to pass to the procedure\r | |
| 523 | \r | |
| 524 | @retval EFI_INVALID_PARAMETER CpuNumber not valid\r | |
| 525 | @retval EFI_INVALID_PARAMETER CpuNumber specifying BSP\r | |
| 526 | @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM\r | |
| 527 | @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy\r | |
| 528 | @retval EFI_SUCCESS - The procedure has been successfully scheduled\r | |
| 529 | \r | |
| 530 | **/\r | |
| 531 | EFI_STATUS\r | |
| 532 | EFIAPI\r | |
| 533 | SmmStartupThisAp (\r | |
| 534 | IN EFI_AP_PROCEDURE Procedure,\r | |
| 535 | IN UINTN CpuIndex,\r | |
| 536 | IN OUT VOID *ProcArguments OPTIONAL\r | |
| 537 | );\r | |
| 538 | \r | |
| 539 | /**\r | |
| 540 | Schedule a procedure to run on the specified CPU in a blocking fashion.\r | |
| 541 | \r | |
| 542 | @param Procedure The address of the procedure to run\r | |
| 543 | @param CpuIndex Target CPU Index\r | |
| 544 | @param ProcArguments The parameter to pass to the procedure\r | |
| 545 | \r | |
| 546 | @retval EFI_INVALID_PARAMETER CpuNumber not valid\r | |
| 547 | @retval EFI_INVALID_PARAMETER CpuNumber specifying BSP\r | |
| 548 | @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM\r | |
| 549 | @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy\r | |
| 550 | @retval EFI_SUCCESS The procedure has been successfully scheduled\r | |
| 551 | \r | |
| 552 | **/\r | |
| 553 | EFI_STATUS\r | |
| 554 | EFIAPI\r | |
| 555 | SmmBlockingStartupThisAp (\r | |
| 556 | IN EFI_AP_PROCEDURE Procedure,\r | |
| 557 | IN UINTN CpuIndex,\r | |
| 558 | IN OUT VOID *ProcArguments OPTIONAL\r | |
| 559 | );\r | |
| 560 | \r | |
| 561 | /**\r | |
| 562 | Initialize MP synchronization data.\r | |
| 563 | \r | |
| 564 | **/\r | |
| 565 | VOID\r | |
| 566 | EFIAPI\r | |
| 567 | InitializeMpSyncData (\r | |
| 568 | VOID\r | |
| 569 | );\r | |
| 570 | \r | |
| 571 | /**\r | |
| 572 | \r | |
| 573 | Find out SMRAM information including SMRR base and SMRR size.\r | |
| 574 | \r | |
| 575 | @param SmrrBase SMRR base\r | |
| 576 | @param SmrrSize SMRR size\r | |
| 577 | \r | |
| 578 | **/\r | |
| 579 | VOID\r | |
| 580 | FindSmramInfo (\r | |
| 581 | OUT UINT32 *SmrrBase,\r | |
| 582 | OUT UINT32 *SmrrSize\r | |
| 583 | );\r | |
| 584 | \r | |
| 585 | /**\r | |
| 586 | The function is invoked before SMBASE relocation in S3 path to restores CPU status.\r | |
| 587 | \r | |
| 588 | The function is invoked before SMBASE relocation in S3 path. It does first time microcode load\r | |
| 589 | and restores MTRRs for both BSP and APs.\r | |
| 590 | \r | |
| 591 | **/\r | |
| 592 | VOID\r | |
| 593 | EarlyInitializeCpu (\r | |
| 594 | VOID\r | |
| 595 | );\r | |
| 596 | \r | |
| 597 | /**\r | |
| 598 | The function is invoked after SMBASE relocation in S3 path to restores CPU status.\r | |
| 599 | \r | |
| 600 | The function is invoked after SMBASE relocation in S3 path. It restores configuration according to\r | |
| 601 | data saved by normal boot path for both BSP and APs.\r | |
| 602 | \r | |
| 603 | **/\r | |
| 604 | VOID\r | |
| 605 | InitializeCpu (\r | |
| 606 | VOID\r | |
| 607 | );\r | |
| 608 | \r | |
| 609 | /**\r | |
| 610 | Page Fault handler for SMM use.\r | |
| 611 | \r | |
| 612 | @param InterruptType Defines the type of interrupt or exception that\r | |
| 613 | occurred on the processor.This parameter is processor architecture specific.\r | |
| 614 | @param SystemContext A pointer to the processor context when\r | |
| 615 | the interrupt occurred on the processor.\r | |
| 616 | **/\r | |
| 617 | VOID\r | |
| 618 | EFIAPI\r | |
| 619 | SmiPFHandler (\r | |
| 620 | IN EFI_EXCEPTION_TYPE InterruptType,\r | |
| 621 | IN EFI_SYSTEM_CONTEXT SystemContext\r | |
| 622 | );\r | |
| 623 | \r | |
| 624 | /**\r | |
| 625 | Perform the remaining tasks.\r | |
| 626 | \r | |
| 627 | **/\r | |
| 628 | VOID\r | |
| 629 | PerformRemainingTasks (\r | |
| 630 | VOID\r | |
| 631 | );\r | |
| 632 | \r | |
| 9f419739 JY |
633 | /**\r |
| 634 | Perform the pre tasks.\r | |
| 635 | \r | |
| 636 | **/\r | |
| 637 | VOID\r | |
| 638 | PerformPreTasks (\r | |
| 639 | VOID\r | |
| 640 | );\r | |
| 641 | \r | |
| 529a5a86 MK |
642 | /**\r |
| 643 | Initialize MSR spin lock by MSR index.\r | |
| 644 | \r | |
| 645 | @param MsrIndex MSR index value.\r | |
| 646 | \r | |
| 647 | **/\r | |
| 648 | VOID\r | |
| 649 | InitMsrSpinLockByIndex (\r | |
| 650 | IN UINT32 MsrIndex\r | |
| 651 | );\r | |
| 652 | \r | |
| 653 | /**\r | |
| 654 | Hook return address of SMM Save State so that semaphore code\r | |
| 655 | can be executed immediately after AP exits SMM to indicate to\r | |
| 656 | the BSP that an AP has exited SMM after SMBASE relocation.\r | |
| 657 | \r | |
| 658 | @param[in] CpuIndex The processor index.\r | |
| 659 | @param[in] RebasedFlag A pointer to a flag that is set to TRUE\r | |
| 660 | immediately after AP exits SMM.\r | |
| 661 | \r | |
| 662 | **/\r | |
| 663 | VOID\r | |
| 664 | SemaphoreHook (\r | |
| 665 | IN UINTN CpuIndex,\r | |
| 666 | IN volatile BOOLEAN *RebasedFlag\r | |
| 667 | );\r | |
| 668 | \r | |
| 669 | /**\r | |
| 670 | Configure SMM Code Access Check feature for all processors.\r | |
| 671 | SMM Feature Control MSR will be locked after configuration.\r | |
| 672 | **/\r | |
| 673 | VOID\r | |
| 674 | ConfigSmmCodeAccessCheck (\r | |
| 675 | VOID\r | |
| 676 | );\r | |
| 677 | \r | |
| 678 | /**\r | |
| 679 | Hook the code executed immediately after an RSM instruction on the currently\r | |
| 680 | executing CPU. The mode of code executed immediately after RSM must be\r | |
| 681 | detected, and the appropriate hook must be selected. Always clear the auto\r | |
| 682 | HALT restart flag if it is set.\r | |
| 683 | \r | |
| 684 | @param[in] CpuIndex The processor index for the currently\r | |
| 685 | executing CPU.\r | |
| 686 | @param[in] CpuState Pointer to SMRAM Save State Map for the\r | |
| 687 | currently executing CPU.\r | |
| 688 | @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to\r | |
| 689 | 32-bit mode from 64-bit SMM.\r | |
| 690 | @param[in] NewInstructionPointer Instruction pointer to use if resuming to\r | |
| 691 | same mode as SMM.\r | |
| 692 | \r | |
| 693 | @retval The value of the original instruction pointer before it was hooked.\r | |
| 694 | \r | |
| 695 | **/\r | |
| 696 | UINT64\r | |
| 697 | EFIAPI\r | |
| 698 | HookReturnFromSmm (\r | |
| 699 | IN UINTN CpuIndex,\r | |
| 700 | SMRAM_SAVE_STATE_MAP *CpuState,\r | |
| 701 | UINT64 NewInstructionPointer32,\r | |
| 702 | UINT64 NewInstructionPointer\r | |
| 703 | );\r | |
| 704 | \r | |
| 705 | /**\r | |
| 706 | Get the size of the SMI Handler in bytes.\r | |
| 707 | \r | |
| 708 | @retval The size, in bytes, of the SMI Handler.\r | |
| 709 | \r | |
| 710 | **/\r | |
| 711 | UINTN\r | |
| 712 | EFIAPI\r | |
| 713 | GetSmiHandlerSize (\r | |
| 714 | VOID\r | |
| 715 | );\r | |
| 716 | \r | |
| 717 | /**\r | |
| 718 | Install the SMI handler for the CPU specified by CpuIndex. This function\r | |
| 719 | is called by the CPU that was elected as monarch during System Management\r | |
| 720 | Mode initialization.\r | |
| 721 | \r | |
| 722 | @param[in] CpuIndex The index of the CPU to install the custom SMI handler.\r | |
| 723 | The value must be between 0 and the NumberOfCpus field\r | |
| 724 | in the System Management System Table (SMST).\r | |
| 725 | @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.\r | |
| 726 | @param[in] SmiStack The stack to use when an SMI is processed by the\r | |
| 727 | the CPU specified by CpuIndex.\r | |
| 728 | @param[in] StackSize The size, in bytes, if the stack used when an SMI is\r | |
| 729 | processed by the CPU specified by CpuIndex.\r | |
| 730 | @param[in] GdtBase The base address of the GDT to use when an SMI is\r | |
| 731 | processed by the CPU specified by CpuIndex.\r | |
| 732 | @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is\r | |
| 733 | processed by the CPU specified by CpuIndex.\r | |
| 734 | @param[in] IdtBase The base address of the IDT to use when an SMI is\r | |
| 735 | processed by the CPU specified by CpuIndex.\r | |
| 736 | @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is\r | |
| 737 | processed by the CPU specified by CpuIndex.\r | |
| 738 | @param[in] Cr3 The base address of the page tables to use when an SMI\r | |
| 739 | is processed by the CPU specified by CpuIndex.\r | |
| 740 | **/\r | |
| 741 | VOID\r | |
| 742 | EFIAPI\r | |
| 743 | InstallSmiHandler (\r | |
| 744 | IN UINTN CpuIndex,\r | |
| 745 | IN UINT32 SmBase,\r | |
| 746 | IN VOID *SmiStack,\r | |
| 747 | IN UINTN StackSize,\r | |
| 748 | IN UINTN GdtBase,\r | |
| 749 | IN UINTN GdtSize,\r | |
| 750 | IN UINTN IdtBase,\r | |
| 751 | IN UINTN IdtSize,\r | |
| 752 | IN UINT32 Cr3\r | |
| 753 | );\r | |
| 754 | \r | |
| 755 | /**\r | |
| 756 | Search module name by input IP address and output it.\r | |
| 757 | \r | |
| 758 | @param CallerIpAddress Caller instruction pointer.\r | |
| 759 | \r | |
| 760 | **/\r | |
| 761 | VOID\r | |
| 762 | DumpModuleInfoByIp (\r | |
| 763 | IN UINTN CallerIpAddress\r | |
| 764 | );\r | |
| 21c17193 JY |
765 | \r |
| 766 | /**\r | |
| 767 | This API provides a way to allocate memory for page table.\r | |
| 768 | \r | |
| 769 | This API can be called more once to allocate memory for page tables.\r | |
| 770 | \r | |
| 771 | Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the\r | |
| 772 | allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL\r | |
| 773 | is returned. If there is not enough memory remaining to satisfy the request, then NULL is\r | |
| 774 | returned.\r | |
| 775 | \r | |
| 776 | @param Pages The number of 4 KB pages to allocate.\r | |
| 777 | \r | |
| 778 | @return A pointer to the allocated buffer or NULL if allocation fails.\r | |
| 779 | \r | |
| 780 | **/\r | |
| 781 | VOID *\r | |
| 782 | AllocatePageTableMemory (\r | |
| 783 | IN UINTN Pages\r | |
| 784 | );\r | |
| 785 | \r | |
| 529a5a86 | 786 | #endif\r |