UefiCpuPkg/PiSmmCpu: Always set RW+P bit for page table by default

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / X64 / PageTbl.c

/** @file\r
Page Fault (#PF) handler for X64 processors\r
\r
Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include "PiSmmCpuDxeSmm.h"\r
\r
#define PAGE_TABLE_PAGES            8\r
#define ACC_MAX_BIT                 BIT3\r
LIST_ENTRY                          mPagePool = INITIALIZE_LIST_HEAD_VARIABLE (mPagePool);\r
SPIN_LOCK                           mPFLock;\r
BOOLEAN                             m1GPageTableSupport = FALSE;\r
\r
/**\r
  Check if 1-GByte pages is supported by processor or not.\r
\r
  @retval TRUE   1-GByte pages is supported.\r
  @retval FALSE  1-GByte pages is not supported.\r
\r
**/\r
BOOLEAN\r
Is1GPageSupport (\r
  VOID\r
  )\r
{\r
  UINT32         RegEax;\r
  UINT32         RegEdx;\r
\r
  AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
  if (RegEax >= 0x80000001) {\r
    AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);\r
    if ((RegEdx & BIT26) != 0) {\r
      return TRUE;\r
    }\r
  }\r
  return FALSE;\r
}\r
\r
/**\r
  Set sub-entries number in entry.\r
\r
  @param[in, out] Entry        Pointer to entry\r
  @param[in]      SubEntryNum  Sub-entries number based on 0:\r
                               0 means there is 1 sub-entry under this entry\r
                               0x1ff means there is 512 sub-entries under this entry\r
\r
**/\r
VOID\r
SetSubEntriesNum (\r
  IN OUT UINT64               *Entry,\r
  IN     UINT64               SubEntryNum\r
  )\r
{\r
  //\r
  // Sub-entries number is saved in BIT52 to BIT60 (reserved field) in Entry\r
  //\r
  *Entry = BitFieldWrite64 (*Entry, 52, 60, SubEntryNum);\r
}\r
\r
/**\r
  Return sub-entries number in entry.\r
\r
  @param[in] Entry        Pointer to entry\r
\r
  @return Sub-entries number based on 0:\r
          0 means there is 1 sub-entry under this entry\r
          0x1ff means there is 512 sub-entries under this entry\r
**/\r
UINT64\r
GetSubEntriesNum (\r
  IN UINT64            *Entry\r
  )\r
{\r
  //\r
  // Sub-entries number is saved in BIT52 to BIT60 (reserved field) in Entry\r
  //\r
  return BitFieldRead64 (*Entry, 52, 60);\r
}\r
\r
/**\r
  Create PageTable for SMM use.\r
\r
  @return The address of PML4 (to set CR3).\r
\r
**/\r
UINT32\r
SmmInitPageTable (\r
  VOID\r
  )\r
{\r
  EFI_PHYSICAL_ADDRESS              Pages;\r
  UINT64                            *PTEntry;\r
  LIST_ENTRY                        *FreePage;\r
  UINTN                             Index;\r
  UINTN                             PageFaultHandlerHookAddress;\r
  IA32_IDT_GATE_DESCRIPTOR          *IdtEntry;\r
\r
  //\r
  // Initialize spin lock\r
  //\r
  InitializeSpinLock (&mPFLock);\r
\r
  m1GPageTableSupport = Is1GPageSupport ();\r
  //\r
  // Generate PAE page table for the first 4GB memory space\r
  //\r
  Pages = Gen4GPageTable (PAGE_TABLE_PAGES + 1, FALSE);\r
\r
  //\r
  // Set IA32_PG_PMNT bit to mask this entry\r
  //\r
  PTEntry = (UINT64*)(UINTN)Pages;\r
  for (Index = 0; Index < 4; Index++) {\r
    PTEntry[Index] |= IA32_PG_PMNT;\r
  }\r
\r
  //\r
  // Fill Page-Table-Level4 (PML4) entry\r
  //\r
  PTEntry = (UINT64*)(UINTN)(Pages - EFI_PAGES_TO_SIZE (PAGE_TABLE_PAGES + 1));\r
  *PTEntry = Pages + PAGE_ATTRIBUTE_BITS;\r
  ZeroMem (PTEntry + 1, EFI_PAGE_SIZE - sizeof (*PTEntry));\r
  //\r
  // Set sub-entries number\r
  //\r
  SetSubEntriesNum (PTEntry, 3);\r
\r
  //\r
  // Add remaining pages to page pool\r
  //\r
  FreePage = (LIST_ENTRY*)(PTEntry + EFI_PAGE_SIZE / sizeof (*PTEntry));\r
  while ((UINTN)FreePage < Pages) {\r
    InsertTailList (&mPagePool, FreePage);\r
    FreePage += EFI_PAGE_SIZE / sizeof (*FreePage);\r
  }\r
\r
  if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {\r
    //\r
    // Set own Page Fault entry instead of the default one, because SMM Profile\r
    // feature depends on IRET instruction to do Single Step\r
    //\r
    PageFaultHandlerHookAddress = (UINTN)PageFaultIdtHandlerSmmProfile;\r
    IdtEntry  = (IA32_IDT_GATE_DESCRIPTOR *) gcSmiIdtr.Base;\r
    IdtEntry += EXCEPT_IA32_PAGE_FAULT;\r
    IdtEntry->Bits.OffsetLow      = (UINT16)PageFaultHandlerHookAddress;\r
    IdtEntry->Bits.Reserved_0     = 0;\r
    IdtEntry->Bits.GateType       = IA32_IDT_GATE_TYPE_INTERRUPT_32;\r
    IdtEntry->Bits.OffsetHigh     = (UINT16)(PageFaultHandlerHookAddress >> 16);\r
    IdtEntry->Bits.OffsetUpper    = (UINT32)(PageFaultHandlerHookAddress >> 32);\r
    IdtEntry->Bits.Reserved_1     = 0;\r
  } else {\r
    //\r
    // Register Smm Page Fault Handler\r
    //\r
    SmmRegisterExceptionHandler (&mSmmCpuService, EXCEPT_IA32_PAGE_FAULT, SmiPFHandler);\r
  }\r
\r
  //\r
  // Additional SMM IDT initialization for SMM stack guard\r
  //\r
  if (FeaturePcdGet (PcdCpuSmmStackGuard)) {\r
    InitializeIDTSmmStackGuard ();\r
  }\r
\r
  //\r
  // Return the address of PML4 (to set CR3)\r
  //\r
  return (UINT32)(UINTN)PTEntry;\r
}\r
\r
/**\r
  Set access record in entry.\r
\r
  @param[in, out] Entry        Pointer to entry\r
  @param[in]      Acc          Access record value\r
\r
**/\r
VOID\r
SetAccNum (\r
  IN OUT UINT64               *Entry,\r
  IN     UINT64               Acc\r
  )\r
{\r
  //\r
  // Access record is saved in BIT9 to BIT11 (reserved field) in Entry\r
  //\r
  *Entry = BitFieldWrite64 (*Entry, 9, 11, Acc);\r
}\r
\r
/**\r
  Return access record in entry.\r
\r
  @param[in] Entry        Pointer to entry\r
\r
  @return Access record value.\r
\r
**/\r
UINT64\r
GetAccNum (\r
  IN UINT64            *Entry\r
  )\r
{\r
  //\r
  // Access record is saved in BIT9 to BIT11 (reserved field) in Entry\r
  //\r
  return BitFieldRead64 (*Entry, 9, 11);\r
}\r
\r
/**\r
  Return and update the access record in entry.\r
\r
  @param[in, out]  Entry    Pointer to entry\r
\r
  @return Access record value.\r
\r
**/\r
UINT64\r
GetAndUpdateAccNum (\r
  IN OUT UINT64      *Entry\r
  )\r
{\r
  UINT64         Acc;\r
\r
  Acc = GetAccNum (Entry);\r
  if ((*Entry & IA32_PG_A) != 0) {\r
    //\r
    // If this entry has been accessed, clear access flag in Entry and update access record\r
    // to the initial value 7, adding ACC_MAX_BIT is to make it larger than others\r
    //\r
    *Entry &= ~(UINT64)(UINTN)IA32_PG_A;\r
    SetAccNum (Entry, 0x7);\r
    return (0x7 + ACC_MAX_BIT);\r
  } else {\r
    if (Acc != 0) {\r
      //\r
      // If the access record is not the smallest value 0, minus 1 and update the access record field\r
      //\r
      SetAccNum (Entry, Acc - 1);\r
    }\r
  }\r
  return Acc;\r
}\r
\r
/**\r
  Reclaim free pages for PageFault handler.\r
\r
  Search the whole entries tree to find the leaf entry that has the smallest\r
  access record value. Insert the page pointed by this leaf entry into the\r
  page pool. And check its upper entries if need to be inserted into the page\r
  pool or not.\r
\r
**/\r
VOID\r
ReclaimPages (\r
  VOID\r
  )\r
{\r
  UINT64                       *Pml4;\r
  UINT64                       *Pdpt;\r
  UINT64                       *Pdt;\r
  UINTN                        Pml4Index;\r
  UINTN                        PdptIndex;\r
  UINTN                        PdtIndex;\r
  UINTN                        MinPml4;\r
  UINTN                        MinPdpt;\r
  UINTN                        MinPdt;\r
  UINT64                       MinAcc;\r
  UINT64                       Acc;\r
  UINT64                       SubEntriesNum;\r
  BOOLEAN                      PML4EIgnore;\r
  BOOLEAN                      PDPTEIgnore;\r
  UINT64                       *ReleasePageAddress;\r
\r
  Pml4 = NULL;\r
  Pdpt = NULL;\r
  Pdt  = NULL;\r
  MinAcc  = (UINT64)-1;\r
  MinPml4 = (UINTN)-1;\r
  MinPdpt = (UINTN)-1;\r
  MinPdt  = (UINTN)-1;\r
  Acc     = 0;\r
  ReleasePageAddress = 0;\r
\r
  //\r
  // First, find the leaf entry has the smallest access record value\r
  //\r
  Pml4 = (UINT64*)(UINTN)(AsmReadCr3 () & gPhyMask);\r
  for (Pml4Index = 0; Pml4Index < EFI_PAGE_SIZE / sizeof (*Pml4); Pml4Index++) {\r
    if ((Pml4[Pml4Index] & IA32_PG_P) == 0 || (Pml4[Pml4Index] & IA32_PG_PMNT) != 0) {\r
      //\r
      // If the PML4 entry is not present or is masked, skip it\r
      //\r
      continue;\r
    }\r
    Pdpt = (UINT64*)(UINTN)(Pml4[Pml4Index] & gPhyMask);\r
    PML4EIgnore = FALSE;\r
    for (PdptIndex = 0; PdptIndex < EFI_PAGE_SIZE / sizeof (*Pdpt); PdptIndex++) {\r
      if ((Pdpt[PdptIndex] & IA32_PG_P) == 0 || (Pdpt[PdptIndex] & IA32_PG_PMNT) != 0) {\r
        //\r
        // If the PDPT entry is not present or is masked, skip it\r
        //\r
        if ((Pdpt[PdptIndex] & IA32_PG_PMNT) != 0) {\r
          //\r
          // If the PDPT entry is masked, we will ignore checking the PML4 entry\r
          //\r
          PML4EIgnore = TRUE;\r
        }\r
        continue;\r
      }\r
      if ((Pdpt[PdptIndex] & IA32_PG_PS) == 0) {\r
        //\r
        // It's not 1-GByte pages entry, it should be a PDPT entry,\r
        // we will not check PML4 entry more\r
        //\r
        PML4EIgnore = TRUE;\r
        Pdt =  (UINT64*)(UINTN)(Pdpt[PdptIndex] & gPhyMask);\r
        PDPTEIgnore = FALSE;\r
        for (PdtIndex = 0; PdtIndex < EFI_PAGE_SIZE / sizeof(*Pdt); PdtIndex++) {\r
          if ((Pdt[PdtIndex] & IA32_PG_P) == 0 || (Pdt[PdtIndex] & IA32_PG_PMNT) != 0) {\r
            //\r
            // If the PD entry is not present or is masked, skip it\r
            //\r
            if ((Pdt[PdtIndex] & IA32_PG_PMNT) != 0) {\r
              //\r
              // If the PD entry is masked, we will not PDPT entry more\r
              //\r
              PDPTEIgnore = TRUE;\r
            }\r
            continue;\r
          }\r
          if ((Pdt[PdtIndex] & IA32_PG_PS) == 0) {\r
            //\r
            // It's not 2 MByte page table entry, it should be PD entry\r
            // we will find the entry has the smallest access record value\r
            //\r
            PDPTEIgnore = TRUE;\r
            Acc = GetAndUpdateAccNum (Pdt + PdtIndex);\r
            if (Acc < MinAcc) {\r
              //\r
              // If the PD entry has the smallest access record value,\r
              // save the Page address to be released\r
              //\r
              MinAcc  = Acc;\r
              MinPml4 = Pml4Index;\r
              MinPdpt = PdptIndex;\r
              MinPdt  = PdtIndex;\r
              ReleasePageAddress = Pdt + PdtIndex;\r
            }\r
          }\r
        }\r
        if (!PDPTEIgnore) {\r
          //\r
          // If this PDPT entry has no PDT entries pointer to 4 KByte pages,\r
          // it should only has the entries point to 2 MByte Pages\r
          //\r
          Acc = GetAndUpdateAccNum (Pdpt + PdptIndex);\r
          if (Acc < MinAcc) {\r
            //\r
            // If the PDPT entry has the smallest access record value,\r
            // save the Page address to be released\r
            //\r
            MinAcc  = Acc;\r
            MinPml4 = Pml4Index;\r
            MinPdpt = PdptIndex;\r
            MinPdt  = (UINTN)-1;\r
            ReleasePageAddress = Pdpt + PdptIndex;\r
          }\r
        }\r
      }\r
    }\r
    if (!PML4EIgnore) {\r
      //\r
      // If PML4 entry has no the PDPT entry pointer to 2 MByte pages,\r
      // it should only has the entries point to 1 GByte Pages\r
      //\r
      Acc = GetAndUpdateAccNum (Pml4 + Pml4Index);\r
      if (Acc < MinAcc) {\r
        //\r
        // If the PML4 entry has the smallest access record value,\r
        // save the Page address to be released\r
        //\r
        MinAcc  = Acc;\r
        MinPml4 = Pml4Index;\r
        MinPdpt = (UINTN)-1;\r
        MinPdt  = (UINTN)-1;\r
        ReleasePageAddress = Pml4 + Pml4Index;\r
      }\r
    }\r
  }\r
  //\r
  // Make sure one PML4/PDPT/PD entry is selected\r
  //\r
  ASSERT (MinAcc != (UINT64)-1);\r
\r
  //\r
  // Secondly, insert the page pointed by this entry into page pool and clear this entry\r
  //\r
  InsertTailList (&mPagePool, (LIST_ENTRY*)(UINTN)(*ReleasePageAddress & gPhyMask));\r
  *ReleasePageAddress = 0;\r
\r
  //\r
  // Lastly, check this entry's upper entries if need to be inserted into page pool\r
  // or not\r
  //\r
  while (TRUE) {\r
    if (MinPdt != (UINTN)-1) {\r
      //\r
      // If 4 KByte Page Table is released, check the PDPT entry\r
      //\r
      Pdpt = (UINT64*)(UINTN)(Pml4[MinPml4] & gPhyMask);\r
      SubEntriesNum = GetSubEntriesNum(Pdpt + MinPdpt);\r
      if (SubEntriesNum == 0) {\r
        //\r
        // Release the empty Page Directory table if there was no more 4 KByte Page Table entry\r
        // clear the Page directory entry\r
        //\r
        InsertTailList (&mPagePool, (LIST_ENTRY*)(UINTN)(Pdpt[MinPdpt] & gPhyMask));\r
        Pdpt[MinPdpt] = 0;\r
        //\r
        // Go on checking the PML4 table\r
        //\r
        MinPdt = (UINTN)-1;\r
        continue;\r
      }\r
      //\r
      // Update the sub-entries filed in PDPT entry and exit\r
      //\r
      SetSubEntriesNum (Pdpt + MinPdpt, SubEntriesNum - 1);\r
      break;\r
    }\r
    if (MinPdpt != (UINTN)-1) {\r
      //\r
      // One 2MB Page Table is released or Page Directory table is released, check the PML4 entry\r
      //\r
      SubEntriesNum = GetSubEntriesNum (Pml4 + MinPml4);\r
      if (SubEntriesNum == 0) {\r
        //\r
        // Release the empty PML4 table if there was no more 1G KByte Page Table entry\r
        // clear the Page directory entry\r
        //\r
        InsertTailList (&mPagePool, (LIST_ENTRY*)(UINTN)(Pml4[MinPml4] & gPhyMask));\r
        Pml4[MinPml4] = 0;\r
        MinPdpt = (UINTN)-1;\r
        continue;\r
      }\r
      //\r
      // Update the sub-entries filed in PML4 entry and exit\r
      //\r
      SetSubEntriesNum (Pml4 + MinPml4, SubEntriesNum - 1);\r
      break;\r
    }\r
    //\r
    // PLM4 table has been released before, exit it\r
    //\r
    break;\r
  }\r
}\r
\r
/**\r
  Allocate free Page for PageFault handler use.\r
\r
  @return Page address.\r
\r
**/\r
UINT64\r
AllocPage (\r
  VOID\r
  )\r
{\r
  UINT64                            RetVal;\r
\r
  if (IsListEmpty (&mPagePool)) {\r
    //\r
    // If page pool is empty, reclaim the used pages and insert one into page pool\r
    //\r
    ReclaimPages ();\r
  }\r
\r
  //\r
  // Get one free page and remove it from page pool\r
  //\r
  RetVal = (UINT64)(UINTN)mPagePool.ForwardLink;\r
  RemoveEntryList (mPagePool.ForwardLink);\r
  //\r
  // Clean this page and return\r
  //\r
  ZeroMem ((VOID*)(UINTN)RetVal, EFI_PAGE_SIZE);\r
  return RetVal;\r
}\r
\r
/**\r
  Page Fault handler for SMM use.\r
\r
**/\r
VOID\r
SmiDefaultPFHandler (\r
  VOID\r
  )\r
{\r
  UINT64                            *PageTable;\r
  UINT64                            *Pml4;\r
  UINT64                            PFAddress;\r
  UINTN                             StartBit;\r
  UINTN                             EndBit;\r
  UINT64                            PTIndex;\r
  UINTN                             Index;\r
  SMM_PAGE_SIZE_TYPE                PageSize;\r
  UINTN                             NumOfPages;\r
  UINTN                             PageAttribute;\r
  EFI_STATUS                        Status;\r
  UINT64                            *UpperEntry;\r
\r
  //\r
  // Set default SMM page attribute\r
  //\r
  PageSize = SmmPageSize2M;\r
  NumOfPages = 1;\r
  PageAttribute = 0;\r
\r
  EndBit = 0;\r
  Pml4 = (UINT64*)(AsmReadCr3 () & gPhyMask);\r
  PFAddress = AsmReadCr2 ();\r
\r
  Status = GetPlatformPageTableAttribute (PFAddress, &PageSize, &NumOfPages, &PageAttribute);\r
  //\r
  // If platform not support page table attribute, set default SMM page attribute\r
  //\r
  if (Status != EFI_SUCCESS) {\r
    PageSize = SmmPageSize2M;\r
    NumOfPages = 1;\r
    PageAttribute = 0;\r
  }\r
  if (PageSize >= MaxSmmPageSizeType) {\r
    PageSize = SmmPageSize2M;\r
  }\r
  if (NumOfPages > 512) {\r
    NumOfPages = 512;\r
  }\r
\r
  switch (PageSize) {\r
  case SmmPageSize4K:\r
    //\r
    // BIT12 to BIT20 is Page Table index\r
    //\r
    EndBit = 12;\r
    break;\r
  case SmmPageSize2M:\r
    //\r
    // BIT21 to BIT29 is Page Directory index\r
    //\r
    EndBit = 21;\r
    PageAttribute |= (UINTN)IA32_PG_PS;\r
    break;\r
  case SmmPageSize1G:\r
    if (!m1GPageTableSupport) {\r
      DEBUG ((EFI_D_ERROR, "1-GByte pages is not supported!"));\r
      ASSERT (FALSE);\r
    }\r
    //\r
    // BIT30 to BIT38 is Page Directory Pointer Table index\r
    //\r
    EndBit = 30;\r
    PageAttribute |= (UINTN)IA32_PG_PS;\r
    break;\r
  default:\r
    ASSERT (FALSE);\r
  }\r
\r
  //\r
  // If execute-disable is enabled, set NX bit\r
  //\r
  if (mXdEnabled) {\r
    PageAttribute |= IA32_PG_NX;\r
  }\r
\r
  for (Index = 0; Index < NumOfPages; Index++) {\r
    PageTable  = Pml4;\r
    UpperEntry = NULL;\r
    for (StartBit = 39; StartBit > EndBit; StartBit -= 9) {\r
      PTIndex = BitFieldRead64 (PFAddress, StartBit, StartBit + 8);\r
      if ((PageTable[PTIndex] & IA32_PG_P) == 0) {\r
        //\r
        // If the entry is not present, allocate one page from page pool for it\r
        //\r
        PageTable[PTIndex] = AllocPage () | PAGE_ATTRIBUTE_BITS;\r
      } else {\r
        //\r
        // Save the upper entry address\r
        //\r
        UpperEntry = PageTable + PTIndex;\r
      }\r
      //\r
      // BIT9 to BIT11 of entry is used to save access record,\r
      // initialize value is 7\r
      //\r
      PageTable[PTIndex] |= (UINT64)IA32_PG_A;\r
      SetAccNum (PageTable + PTIndex, 7);\r
      PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & gPhyMask);\r
    }\r
\r
    PTIndex = BitFieldRead64 (PFAddress, StartBit, StartBit + 8);\r
    if ((PageTable[PTIndex] & IA32_PG_P) != 0) {\r
      //\r
      // Check if the entry has already existed, this issue may occur when the different\r
      // size page entries created under the same entry\r
      //\r
      DEBUG ((EFI_D_ERROR, "PageTable = %lx, PTIndex = %x, PageTable[PTIndex] = %lx\n", PageTable, PTIndex, PageTable[PTIndex]));\r
      DEBUG ((EFI_D_ERROR, "New page table overlapped with old page table!\n"));\r
      ASSERT (FALSE);\r
    }\r
    //\r
    // Fill the new entry\r
    //\r
    PageTable[PTIndex] = (PFAddress & gPhyMask & ~((1ull << EndBit) - 1)) |\r
                         PageAttribute | IA32_PG_A | PAGE_ATTRIBUTE_BITS;\r
    if (UpperEntry != NULL) {\r
      SetSubEntriesNum (UpperEntry, GetSubEntriesNum (UpperEntry) + 1);\r
    }\r
    //\r
    // Get the next page address if we need to create more page tables\r
    //\r
    PFAddress += (1ull << EndBit);\r
  }\r
}\r
\r
/**\r
  ThePage Fault handler wrapper for SMM use.\r
\r
  @param  InterruptType    Defines the type of interrupt or exception that\r
                           occurred on the processor.This parameter is processor architecture specific.\r
  @param  SystemContext    A pointer to the processor context when\r
                           the interrupt occurred on the processor.\r
**/\r
VOID\r
EFIAPI\r
SmiPFHandler (\r
    IN EFI_EXCEPTION_TYPE   InterruptType,\r
    IN EFI_SYSTEM_CONTEXT   SystemContext\r
  )\r
{\r
  UINTN             PFAddress;\r
\r
  ASSERT (InterruptType == EXCEPT_IA32_PAGE_FAULT);\r
\r
  AcquireSpinLock (&mPFLock);\r
\r
  PFAddress = AsmReadCr2 ();\r
\r
  //\r
  // If a page fault occurs in SMRAM range, it should be in a SMM stack guard page.\r
  //\r
  if ((FeaturePcdGet (PcdCpuSmmStackGuard)) &&\r
      (PFAddress >= mCpuHotPlugData.SmrrBase) &&\r
      (PFAddress < (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize))) {\r
    DEBUG ((EFI_D_ERROR, "SMM stack overflow!\n"));\r
    CpuDeadLoop ();\r
  }\r
\r
  //\r
  // If a page fault occurs in SMM range\r
  //\r
  if ((PFAddress < mCpuHotPlugData.SmrrBase) ||\r
      (PFAddress >= mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) {\r
    if ((SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_ID) != 0) {\r
      DEBUG ((EFI_D_ERROR, "Code executed on IP(0x%lx) out of SMM range after SMM is locked!\n", PFAddress));\r
      DEBUG_CODE (\r
        DumpModuleInfoByIp (*(UINTN *)(UINTN)SystemContext.SystemContextX64->Rsp);\r
      );\r
      CpuDeadLoop ();\r
    }\r
  }\r
\r
  if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {\r
    SmmProfilePFHandler (\r
      SystemContext.SystemContextX64->Rip,\r
      SystemContext.SystemContextX64->ExceptionData\r
      );\r
  } else {\r
    SmiDefaultPFHandler ();\r
  }\r
\r
  ReleaseSpinLock (&mPFLock);\r
}\r