projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 427e3573 MK |
1 | #------------------------------------------------------------------------------\r |
| 2 | #\r | |
| 3 | # Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>\r | |
| 4 | # This program and the accompanying materials\r | |
| 5 | # are licensed and made available under the terms and conditions of the BSD License\r | |
| 6 | # which accompanies this distribution. The full text of the license may be found at\r | |
| 7 | # http://opensource.org/licenses/bsd-license.php.\r | |
| 8 | #\r | |
| 9 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 10 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 11 | #\r | |
| 12 | # Module Name:\r | |
| 13 | #\r | |
| 14 | # SmiEntry.S\r | |
| 15 | #\r | |
| 16 | # Abstract:\r | |
| 17 | #\r | |
| 18 | # Code template of the SMI handler for a particular processor\r | |
| 19 | #\r | |
| 20 | #------------------------------------------------------------------------------\r | |
| 21 | \r | |
| 22 | ASM_GLOBAL ASM_PFX(gcSmiHandlerTemplate)\r | |
| 23 | ASM_GLOBAL ASM_PFX(gcSmiHandlerSize)\r | |
| 24 | ASM_GLOBAL ASM_PFX(gSmiCr3)\r | |
| 25 | ASM_GLOBAL ASM_PFX(gSmiStack)\r | |
| 26 | ASM_GLOBAL ASM_PFX(gSmbase)\r | |
| 27 | ASM_GLOBAL ASM_PFX(FeaturePcdGet (PcdCpuSmmDebug))\r | |
| 28 | ASM_GLOBAL ASM_PFX(gSmiHandlerIdtr)\r | |
| 29 | \r | |
| 30 | #\r | |
| 31 | # Constants relating to PROCESSOR_SMM_DESCRIPTOR\r | |
| 32 | #\r | |
| 33 | .equ DSC_OFFSET, 0xfb00\r | |
| 34 | .equ DSC_GDTPTR, 0x30\r | |
| 35 | .equ DSC_GDTSIZ, 0x38\r | |
| 36 | .equ DSC_CS, 14\r | |
| 37 | .equ DSC_DS, 16\r | |
| 38 | .equ DSC_SS, 18\r | |
| 39 | .equ DSC_OTHERSEG, 20\r | |
| 40 | #\r | |
| 41 | # Constants relating to CPU State Save Area\r | |
| 42 | #\r | |
| 43 | .equ SSM_DR6, 0xffd0\r | |
| 44 | .equ SSM_DR7, 0xffc8\r | |
| 45 | \r | |
| 46 | .equ PROTECT_MODE_CS, 0x08\r | |
| 47 | .equ PROTECT_MODE_DS, 0x20\r | |
| 48 | .equ LONG_MODE_CS, 0x38\r | |
| 49 | .equ TSS_SEGMENT, 0x40\r | |
| 50 | .equ GDT_SIZE, 0x50\r | |
| 51 | \r | |
| 52 | .text\r | |
| 53 | \r | |
| 54 | ASM_PFX(gcSmiHandlerTemplate):\r | |
| 55 | \r | |
| 56 | _SmiEntryPoint:\r | |
| 57 | #\r | |
| 58 | # The encoding of BX in 16-bit addressing mode is the same as of RDI in 64-\r | |
| 59 | # bit addressing mode. And that coincidence has been used in the following\r | |
| 60 | # "64-bit like" 16-bit code. Be aware that once RDI is referenced as a\r | |
| 61 | # base address register, it is actually BX that is referenced.\r | |
| 62 | #\r | |
| 63 | .byte 0xbb # mov bx, imm16\r | |
| 64 | .word _GdtDesc - _SmiEntryPoint + 0x8000\r | |
| 65 | #\r | |
| 66 | # fix GDT descriptor\r | |
| 67 | #\r | |
| 68 | .byte 0x2e,0xa1 # mov ax, cs:[offset16]\r | |
| 69 | .word DSC_OFFSET + DSC_GDTSIZ\r | |
| 70 | .byte 0x48 # dec ax\r | |
| 71 | .byte 0x2e\r | |
| 72 | movl %eax, (%rdi) # mov cs:[bx], ax\r | |
| 73 | .byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]\r | |
| 74 | .word DSC_OFFSET + DSC_GDTPTR\r | |
| 75 | .byte 0x2e\r | |
| 76 | movw %ax, 2(%rdi)\r | |
| 77 | .byte 0x66,0x2e\r | |
| 78 | lgdt (%rdi)\r | |
| 79 | #\r | |
| 80 | # Patch ProtectedMode Segment\r | |
| 81 | #\r | |
| 82 | .byte 0xb8\r | |
| 83 | .word PROTECT_MODE_CS\r | |
| 84 | .byte 0x2e\r | |
| 85 | movl %eax, -2(%rdi)\r | |
| 86 | #\r | |
| 87 | # Patch ProtectedMode entry\r | |
| 88 | #\r | |
| 89 | .byte 0x66, 0xbf # mov edi, SMBASE\r | |
| 90 | ASM_PFX(gSmbase): .space 4\r | |
| 91 | lea ((ProtectedMode - _SmiEntryPoint) + 0x8000)(%edi), %ax\r | |
| 92 | .byte 0x2e\r | |
| 93 | movw %ax, -6(%rdi)\r | |
| 94 | #\r | |
| 95 | # Switch into ProtectedMode\r | |
| 96 | #\r | |
| 97 | movq %cr0, %rbx\r | |
| 98 | .byte 0x66\r | |
| 99 | andl $0x9ffafff3, %ebx\r | |
| 100 | .byte 0x66\r | |
| 101 | orl $0x00000023, %ebx\r | |
| 102 | \r | |
| 103 | movq %rbx, %cr0\r | |
| 104 | .byte 0x66, 0xea\r | |
| 105 | .space 6\r | |
| 106 | \r | |
| 107 | _GdtDesc: .space 6\r | |
| 108 | \r | |
| 109 | ProtectedMode:\r | |
| 110 | movw $PROTECT_MODE_DS, %ax\r | |
| 111 | movl %eax, %ds\r | |
| 112 | movl %eax, %es\r | |
| 113 | movl %eax, %fs\r | |
| 114 | movl %eax, %gs\r | |
| 115 | movl %eax, %ss\r | |
| 116 | .byte 0xbc # mov esp, imm32\r | |
| 117 | ASM_PFX(gSmiStack): .space 4\r | |
| 118 | jmp ProtFlatMode\r | |
| 119 | \r | |
| 120 | ProtFlatMode:\r | |
| 121 | .byte 0xb8\r | |
| 122 | ASM_PFX(gSmiCr3): .space 4\r | |
| 123 | movq %rax, %cr3\r | |
| 124 | movl $0x668,%eax # as cr4.PGE is not set here, refresh cr3\r | |
| 125 | movq %rax, %cr4 # in PreModifyMtrrs() to flush TLB.\r | |
| 126 | # Load TSS\r | |
| 127 | subl $8, %esp # reserve room in stack\r | |
| 128 | sgdt (%rsp)\r | |
| 129 | movl 2(%rsp), %eax # eax = GDT base\r | |
| 130 | addl $8, %esp\r | |
| 427e3573 MK |
131 | movb $0x89, %dl\r |
| 132 | movb %dl, (TSS_SEGMENT + 5)(%rax) # clear busy flag\r | |
| 133 | movl $TSS_SEGMENT, %eax\r | |
| 134 | ltr %ax\r | |
| 135 | \r | |
| 136 | #\r | |
| 137 | # Switch to LongMode\r | |
| 138 | #\r | |
| 139 | pushq $LONG_MODE_CS # push cs hardcore here\r | |
| 140 | call Base # push return address for retf later\r | |
| 141 | Base:\r | |
| 142 | addl $(LongMode - Base), (%rsp) # offset for far retf, seg is the 1st arg\r | |
| 143 | movl $0xc0000080, %ecx\r | |
| 144 | rdmsr\r | |
| 145 | orb $1,%ah\r | |
| 146 | wrmsr\r | |
| 147 | movq %cr0, %rbx\r | |
| 148 | btsl $31, %ebx\r | |
| 149 | movq %rbx, %cr0\r | |
| 150 | retf\r | |
| 151 | LongMode: # long mode (64-bit code) starts here\r | |
| 152 | movabsq $ASM_PFX(gSmiHandlerIdtr), %rax\r | |
| 153 | lidt (%rax)\r | |
| 154 | lea (DSC_OFFSET)(%rdi), %ebx\r | |
| 155 | movw DSC_DS(%rbx), %ax\r | |
| 156 | movl %eax,%ds\r | |
| 157 | movw DSC_OTHERSEG(%rbx), %ax\r | |
| 158 | movl %eax,%es\r | |
| 159 | movl %eax,%fs\r | |
| 160 | movl %eax,%gs\r | |
| 161 | movw DSC_SS(%rbx), %ax\r | |
| 162 | movl %eax,%ss\r | |
| 163 | # jmp _SmiHandler ; instruction is not needed\r | |
| 164 | \r | |
| 165 | _SmiHandler:\r | |
| 166 | movabsq $ASM_PFX(FeaturePcdGet (PcdCpuSmmDebug)), %rax\r | |
| 167 | cmpb $0, (%rax)\r | |
| 168 | jz L1\r | |
| 169 | \r | |
| 170 | .byte 0x48, 0x8b, 0x0d # mov rcx, [rip + disp32]\r | |
| 171 | .long SSM_DR6 - (. + 4 - _SmiEntryPoint + 0x8000)\r | |
| 172 | .byte 0x48, 0x8b, 0x15 # mov rdx, [rip + disp32]\r | |
| 173 | .long SSM_DR7 - (. + 4 - _SmiEntryPoint + 0x8000)\r | |
| 174 | movq %rcx, %dr6\r | |
| 175 | movq %rdx, %dr7\r | |
| 176 | L1:\r | |
| 177 | \r | |
| 178 | movabsq $ASM_PFX(SmiRendezvous), %rax\r | |
| 179 | movq (%rsp), %rcx\r | |
| 180 | # Save FP registers\r | |
| 181 | \r | |
| 182 | subq $0x208, %rsp\r | |
| 183 | .byte 0x48 # FXSAVE64\r | |
| 184 | fxsave (%rsp)\r | |
| 185 | \r | |
| 186 | addq $-0x20, %rsp\r | |
| 187 | call *%rax\r | |
| 188 | addq $0x20, %rsp\r | |
| 189 | \r | |
| 190 | #\r | |
| 191 | # Restore FP registers\r | |
| 192 | #\r | |
| 193 | .byte 0x48 # FXRSTOR64\r | |
| 194 | fxrstor (%rsp)\r | |
| 195 | \r | |
| 196 | movabsq $ASM_PFX(FeaturePcdGet (PcdCpuSmmDebug)), %rax\r | |
| 197 | cmpb $0, (%rax)\r | |
| 198 | jz L2\r | |
| 199 | \r | |
| 200 | movq %dr7, %rdx\r | |
| 201 | movq %dr6, %rcx\r | |
| 202 | .byte 0x48, 0x89, 0x15 # mov [rip + disp32], rdx\r | |
| 203 | .long SSM_DR7 - (. + 4 - _SmiEntryPoint + 0x8000)\r | |
| 204 | .byte 0x48, 0x89, 0x0d # mov [rip + disp32], rcx\r | |
| 205 | .long SSM_DR6 - (. + 4 - _SmiEntryPoint + 0x8000)\r | |
| 206 | L2:\r | |
| 207 | rsm\r | |
| 208 | \r | |
| 209 | ASM_PFX(gcSmiHandlerSize): .word . - _SmiEntryPoint\r |