MdePkg/BaseLib: add PatchInstructionX86()

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / X64 / SmiEntry.asm

;------------------------------------------------------------------------------ ;\r
; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution.  The full text of the license may be found at\r
; http://opensource.org/licenses/bsd-license.php.\r
;\r
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
;\r
; Module Name:\r
;\r
;   SmiEntry.asm\r
;\r
; Abstract:\r
;\r
;   Code template of the SMI handler for a particular processor\r
;\r
;-------------------------------------------------------------------------------\r
\r
;\r
; Variables referenced by C code\r
;\r
EXTERNDEF   SmiRendezvous:PROC\r
EXTERNDEF   CpuSmmDebugEntry:PROC\r
EXTERNDEF   CpuSmmDebugExit:PROC\r
EXTERNDEF   gcSmiHandlerTemplate:BYTE\r
EXTERNDEF   gcSmiHandlerSize:WORD\r
EXTERNDEF   gSmiCr3:DWORD\r
EXTERNDEF   gSmiStack:DWORD\r
EXTERNDEF   gSmbase:DWORD\r
EXTERNDEF   mXdSupported:BYTE\r
EXTERNDEF   gSmiHandlerIdtr:FWORD\r
\r
MSR_IA32_MISC_ENABLE  EQU     1A0h\r
MSR_EFER      EQU     0c0000080h\r
MSR_EFER_XD   EQU     0800h\r
\r
;\r
; Constants relating to PROCESSOR_SMM_DESCRIPTOR\r
;\r
DSC_OFFSET    EQU     0fb00h\r
DSC_GDTPTR    EQU     30h\r
DSC_GDTSIZ    EQU     38h\r
DSC_CS        EQU     14\r
DSC_DS        EQU     16\r
DSC_SS        EQU     18\r
DSC_OTHERSEG  EQU     20\r
;\r
; Constants relating to CPU State Save Area\r
;\r
SSM_DR6         EQU     0ffd0h\r
SSM_DR7         EQU     0ffc8h\r
\r
PROTECT_MODE_CS EQU     08h\r
PROTECT_MODE_DS EQU     20h\r
LONG_MODE_CS    EQU     38h\r
TSS_SEGMENT     EQU     40h\r
GDT_SIZE        EQU     50h\r
\r
    .code\r
\r
gcSmiHandlerTemplate    LABEL   BYTE\r
\r
_SmiEntryPoint:\r
    ;\r
    ; The encoding of BX in 16-bit addressing mode is the same as of RDI in 64-\r
    ; bit addressing mode. And that coincidence has been used in the following\r
    ; "64-bit like" 16-bit code. Be aware that once RDI is referenced as a\r
    ; base address register, it is actually BX that is referenced.\r
    ;\r
    DB      0bbh                        ; mov bx, imm16\r
    DW      offset _GdtDesc - _SmiEntryPoint + 8000h  ; bx = GdtDesc offset\r
; fix GDT descriptor\r
    DB      2eh, 0a1h                   ; mov ax, cs:[offset16]\r
    DW      DSC_OFFSET + DSC_GDTSIZ\r
    DB      48h                         ; dec ax\r
    DB      2eh\r
    mov     [rdi], eax                  ; mov cs:[bx], ax\r
    DB      66h, 2eh, 0a1h              ; mov eax, cs:[offset16]\r
    DW      DSC_OFFSET + DSC_GDTPTR\r
    DB      2eh\r
    mov     [rdi + 2], ax               ; mov cs:[bx + 2], eax\r
    DB      66h, 2eh\r
    lgdt    fword ptr [rdi]             ; lgdt fword ptr cs:[bx]\r
; Patch ProtectedMode Segment\r
    DB      0b8h                        ; mov ax, imm16\r
    DW      PROTECT_MODE_CS             ; set AX for segment directly\r
    DB      2eh\r
    mov     [rdi - 2], eax              ; mov cs:[bx - 2], ax\r
; Patch ProtectedMode entry\r
    DB      66h, 0bfh                   ; mov edi, SMBASE\r
gSmbase    DD    ?\r
    lea     ax, [edi + (@ProtectedMode - _SmiEntryPoint) + 8000h]\r
    DB      2eh\r
    mov     [rdi - 6], ax               ; mov cs:[bx - 6], eax\r
; Switch into @ProtectedMode\r
    mov     rbx, cr0\r
    DB      66h\r
    and     ebx, 9ffafff3h\r
    DB      66h\r
    or      ebx, 00000023h\r
\r
    mov     cr0, rbx\r
    DB      66h, 0eah\r
    DD      ?\r
    DW      ?\r
\r
_GdtDesc    FWORD   ?\r
@ProtectedMode:\r
    mov     ax, PROTECT_MODE_DS\r
    mov     ds, ax\r
    mov     es, ax\r
    mov     fs, ax\r
    mov     gs, ax\r
    mov     ss, ax\r
    DB      0bch                   ; mov esp, imm32\r
gSmiStack   DD      ?\r
    jmp     ProtFlatMode\r
\r
ProtFlatMode:\r
    DB      0b8h                        ; mov eax, offset gSmiCr3\r
gSmiCr3     DD      ?\r
    mov     cr3, rax\r
    mov     eax, 668h                   ; as cr4.PGE is not set here, refresh cr3\r
    mov     cr4, rax                    ; in PreModifyMtrrs() to flush TLB.\r
; Load TSS\r
    sub     esp, 8                      ; reserve room in stack\r
    sgdt    fword ptr [rsp]\r
    mov     eax, [rsp + 2]              ; eax = GDT base\r
    add     esp, 8\r
    mov     dl, 89h\r
    mov     [rax + TSS_SEGMENT + 5], dl ; clear busy flag\r
    mov     eax, TSS_SEGMENT\r
    ltr     ax\r
\r
; enable NXE if supported\r
    DB      0b0h                        ; mov al, imm8\r
mXdSupported     DB      1\r
    cmp     al, 0\r
    jz      @SkipXd\r
;\r
; Check XD disable bit\r
;\r
    mov     ecx, MSR_IA32_MISC_ENABLE\r
    rdmsr\r
    sub     esp, 4\r
    push    rdx                        ; save MSR_IA32_MISC_ENABLE[63-32]\r
    test    edx, BIT2                  ; MSR_IA32_MISC_ENABLE[34]\r
    jz      @f\r
    and     dx, 0FFFBh                 ; clear XD Disable bit if it is set\r
    wrmsr\r
@@:\r
    mov     ecx, MSR_EFER\r
    rdmsr\r
    or      ax, MSR_EFER_XD            ; enable NXE\r
    wrmsr\r
    jmp     @XdDone\r
@SkipXd:\r
    sub     esp, 8\r
@XdDone:\r
\r
; Switch into @LongMode\r
    push    LONG_MODE_CS                ; push cs hardcore here\r
    call    Base                       ; push return address for retf later\r
Base:\r
    add     dword ptr [rsp], @LongMode - Base; offset for far retf, seg is the 1st arg\r
\r
    mov     ecx, MSR_EFER\r
    rdmsr\r
    or      ah, 1                      ; enable LME\r
    wrmsr\r
    mov     rbx, cr0\r
    or      ebx, 080010023h            ; enable paging + WP + NE + MP + PE\r
    mov     cr0, rbx\r
    retf\r
@LongMode:                              ; long mode (64-bit code) starts here\r
    mov     rax, offset gSmiHandlerIdtr\r
    lidt    fword ptr [rax]\r
    lea     ebx, [rdi + DSC_OFFSET]\r
    mov     ax, [rbx + DSC_DS]\r
    mov     ds, eax\r
    mov     ax, [rbx + DSC_OTHERSEG]\r
    mov     es, eax\r
    mov     fs, eax\r
    mov     gs, eax\r
    mov     ax, [rbx + DSC_SS]\r
    mov     ss, eax\r
;   jmp     _SmiHandler                 ; instruction is not needed\r
\r
_SmiHandler:\r
    mov     rbx, [rsp]                  ; rbx <- CpuIndex\r
\r
    ;\r
    ; Save FP registers\r
    ;\r
    sub     rsp, 200h\r
    DB      48h                         ; FXSAVE64\r
    fxsave  [rsp]\r
\r
    add     rsp, -20h\r
\r
    mov     rcx, rbx\r
    mov     rax, CpuSmmDebugEntry\r
    call    rax\r
\r
    mov     rcx, rbx\r
    mov     rax, SmiRendezvous          ; rax <- absolute addr of SmiRedezvous\r
    call    rax\r
\r
    mov     rcx, rbx\r
    mov     rax, CpuSmmDebugExit\r
    call    rax\r
\r
    add     rsp, 20h\r
\r
    ;\r
    ; Restore FP registers\r
    ;\r
    DB      48h                         ; FXRSTOR64\r
    fxrstor [rsp]\r
\r
    add     rsp, 200h\r
\r
    mov     rax, offset ASM_PFX(mXdSupported)\r
    mov     al, [rax]\r
    cmp     al, 0\r
    jz      @f\r
    pop     rdx                       ; get saved MSR_IA32_MISC_ENABLE[63-32]\r
    test    edx, BIT2\r
    jz      @f\r
    mov     ecx, MSR_IA32_MISC_ENABLE\r
    rdmsr\r
    or      dx, BIT2                  ; set XD Disable bit if it was set before entering into SMM\r
    wrmsr\r
\r
@@:\r
    rsm\r
\r
gcSmiHandlerSize    DW      $ - _SmiEntryPoint\r
\r
    END\r