projects / mirror_edk2.git / blame
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| bc252e8e EB |
1 | ;------------------------------------------------------------------------------\r |
| 2 | ; @file\r | |
| 3 | ; Main routine of the pre-SEC code up through the jump into SEC\r | |
| 4 | ;\r | |
| 5 | ; Copyright (c) 2008 - 2009, Intel Corporation\r | |
| 6 | ; All rights reserved. This program and the accompanying materials\r | |
| 7 | ; are licensed and made available under the terms and conditions of the BSD License\r | |
| 8 | ; which accompanies this distribution. The full text of the license may be found at\r | |
| 9 | ; http://opensource.org/licenses/bsd-license.php\r | |
| 10 | ;\r | |
| 11 | ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 12 | ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 13 | ;\r | |
| 14 | ;------------------------------------------------------------------------------\r | |
| 15 | \r | |
| 16 | \r | |
| 17 | BITS 16\r | |
| 18 | \r | |
| 19 | ;\r | |
| 20 | ; Modified: EBX, ECX, EDX, EBP\r | |
| 21 | ;\r | |
| 22 | ; @param[in,out] RAX/EAX Initial value of the EAX register\r | |
| 23 | ; (BIST: Built-in Self Test)\r | |
| 24 | ; @param[in,out] DI 'BP': boot-strap processor, or\r | |
| 25 | ; 'AP': application processor\r | |
| 26 | ; @param[out] RBP/EBP Address of Boot Firmware Volume (BFV)\r | |
| 27 | ;\r | |
| 28 | ; @return None This routine jumps to SEC and does not return\r | |
| 29 | ;\r | |
| 30 | Main16:\r | |
| 31 | OneTimeCall EarlyInit16\r | |
| 32 | \r | |
| 33 | ;\r | |
| 34 | ; Transition the processor from 16-bit real mode to 32-bit flat mode\r | |
| 35 | ;\r | |
| 36 | OneTimeCall TransitionFromReal16To32BitFlat\r | |
| 37 | \r | |
| 38 | BITS 32\r | |
| 39 | \r | |
| 40 | ;\r | |
| 41 | ; Search for the Boot Firmware Volume (BFV)\r | |
| 42 | ;\r | |
| 43 | OneTimeCall Flat32SearchForBfvBase\r | |
| 44 | \r | |
| 45 | ;\r | |
| 46 | ; EBP - Start of BFV\r | |
| 47 | ;\r | |
| 48 | \r | |
| 49 | ;\r | |
| 50 | ; Search for the SEC entry point\r | |
| 51 | ;\r | |
| 52 | OneTimeCall Flat32SearchForSecEntryPoint\r | |
| 53 | \r | |
| 54 | ;\r | |
| 55 | ; ESI - SEC Core entry point\r | |
| 56 | ; EBP - Start of BFV\r | |
| 57 | ;\r | |
| 58 | \r | |
| 59 | %ifdef ARCH_IA32\r | |
| 60 | \r | |
| 61 | ;\r | |
| 62 | ; Restore initial EAX value into the EAX register\r | |
| 63 | ;\r | |
| 64 | mov eax, esp\r | |
| 65 | \r | |
| 66 | ;\r | |
| 67 | ; Jump to the 32-bit SEC entry point\r | |
| 68 | ;\r | |
| 69 | jmp esi\r | |
| 70 | \r | |
| 71 | %else\r | |
| 72 | \r | |
| 73 | ;\r | |
| 74 | ; Transition the processor from 32-bit flat mode to 64-bit flat mode\r | |
| 75 | ;\r | |
| 76 | OneTimeCall Transition32FlatTo64Flat\r | |
| 77 | \r | |
| 78 | BITS 64\r | |
| 79 | \r | |
| 80 | ;\r | |
| 81 | ; Some values were calculated in 32-bit mode. Make sure the upper\r | |
| 82 | ; 32-bits of 64-bit registers are zero for these values.\r | |
| 83 | ;\r | |
| 84 | mov rax, 0x00000000ffffffff\r | |
| 85 | and rsi, rax\r | |
| 86 | and rbp, rax\r | |
| 87 | and rsp, rax\r | |
| 88 | \r | |
| 89 | ;\r | |
| 90 | ; RSI - SEC Core entry point\r | |
| 91 | ; RBP - Start of BFV\r | |
| 92 | ;\r | |
| 93 | \r | |
| 94 | ;\r | |
| 95 | ; Restore initial EAX value into the RAX register\r | |
| 96 | ;\r | |
| 97 | mov rax, rsp\r | |
| 98 | \r | |
| 99 | ;\r | |
| 100 | ; Jump to the 64-bit SEC entry point\r | |
| 101 | ;\r | |
| 102 | jmp rsi\r | |
| 103 | \r | |
| 104 | %endif\r | |
| 105 | \r | |
| 106 | \r |