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1 | ;------------------------------------------------------------------------------\r |
2 | ; @file\r | |
3 | ; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x8000000000 (512GB)\r | |
4 | ;\r | |
5 | ; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>\r | |
6 | ; SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
7 | ; Linear-Address Translation to a 1-GByte Page\r | |
8 | ;\r | |
9 | ;------------------------------------------------------------------------------\r | |
10 | \r | |
11 | BITS 64\r | |
12 | \r | |
13 | %define ALIGN_TOP_TO_4K_FOR_PAGING\r | |
14 | \r | |
15 | %define PAGE_PDP_ATTR (PAGE_ACCESSED + \\r | |
16 | PAGE_READ_WRITE + \\r | |
17 | PAGE_PRESENT)\r | |
18 | \r | |
19 | %define PAGE_PDP_1G_ATTR (PAGE_ACCESSED + \\r | |
20 | PAGE_READ_WRITE + \\r | |
21 | PAGE_DIRTY + \\r | |
22 | PAGE_PRESENT + \\r | |
23 | PAGE_SIZE)\r | |
24 | \r | |
25 | %define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory)\r | |
26 | %define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x))\r | |
27 | \r | |
28 | %define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \\r | |
29 | PAGE_PDP_ATTR)\r | |
30 | \r | |
31 | %define PDP_1G(x) ((x << 30) + PAGE_PDP_1G_ATTR)\r | |
32 | \r | |
33 | ALIGN 16\r | |
34 | \r | |
35 | TopLevelPageDirectory:\r | |
36 | \r | |
37 | ;\r | |
38 | ; Top level Page Directory Pointers (1 * 512GB entry)\r | |
39 | ;\r | |
40 | DQ PDP(0x1000)\r | |
41 | \r | |
42 | TIMES 0x1000-PGTBLS_OFFSET($) DB 0\r | |
43 | ;\r | |
44 | ; Next level Page Directory Pointers (512 * 1GB entries => 512GB)\r | |
45 | ;\r | |
46 | %assign i 0\r | |
47 | %rep 512\r | |
48 | DQ PDP_1G(i)\r | |
49 | %assign i i+1\r | |
50 | %endrep\r | |
51 | TIMES 0x2000-PGTBLS_OFFSET($) DB 0\r | |
52 | \r | |
53 | EndOfPageTables:\r |