MdeModulePkg/PiSmmCore: Cache CommunicationBuffer info before using it
[mirror_edk2.git] / UefiCpuPkg / UefiCpuPkg.dec
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7798fb83 1## @file UefiCpuPkg.dec\r
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2# This Package provides UEFI compatible CPU modules and libraries.\r
3#\r
b1e01bd4 4# Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.<BR>\r
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5#\r
6# This program and the accompanying materials are licensed and made available under\r
7# the terms and conditions of the BSD License which accompanies this distribution.\r
8# The full text of the license may be found at\r
9# http://opensource.org/licenses/bsd-license.php\r
10#\r
11# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13#\r
14##\r
15\r
16[Defines]\r
17 DEC_SPECIFICATION = 0x00010005\r
18 PACKAGE_NAME = UefiCpuPkg\r
abae030a 19 PACKAGE_UNI_FILE = UefiCpuPkg.uni\r
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20 PACKAGE_GUID = 2171df9b-0d39-45aa-ac37-2de190010d23\r
21 PACKAGE_VERSION = 0.3\r
22\r
23[Includes]\r
24 Include\r
25\r
26[LibraryClasses]\r
27 ## @libraryclass Defines some routines that are generic for IA32 family CPU\r
28 ## to be UEFI specification compliant.\r
29 ##\r
30 UefiCpuLib|Include/Library/UefiCpuLib.h\r
31\r
32[LibraryClasses.IA32, LibraryClasses.X64]\r
33 ## @libraryclass Provides functions to manage MTRR settings on IA32 and X64 CPUs.\r
34 ##\r
35 MtrrLib|Include/Library/MtrrLib.h\r
36\r
37 ## @libraryclass Provides functions to manage the Local APIC on IA32 and X64 CPUs.\r
38 ##\r
39 LocalApicLib|Include/Library/LocalApicLib.h\r
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40\r
41 ## @libraryclass Provides platform specific initialization functions in the SEC phase.\r
42 ##\r
43 PlatformSecLib|Include/Library/PlatformSecLib.h\r
529a5a86 44\r
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45 ## @libraryclass Public include file for the SMM CPU Platform Hook Library.\r
46 ##\r
47 SmmCpuPlatformHookLib|Include/Library/SmmCpuPlatformHookLib.h\r
529a5a86 48\r
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49 ## @libraryclass Provides the CPU specific programming for PiSmmCpuDxeSmm module.\r
50 ##\r
51 SmmCpuFeaturesLib|Include/Library/SmmCpuFeaturesLib.h\r
52\r
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53 ## @libraryclass Provides functions to support MP services on CpuMpPei and CpuDxe module.\r
54 ##\r
55 MpInitLib|Include/Library/MpInitLib.h\r
56\r
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57 ## @libraryclass Provides services to access Microcode region on flash device.\r
58 #\r
59 MicrocodeFlashAccessLib|Include/Library/MicrocodeFlashAccessLib.h\r
60\r
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61[Guids]\r
62 gUefiCpuPkgTokenSpaceGuid = { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa, 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}\r
63\r
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64 ## Include/Guid/MicrocodeFmp.h\r
65 gMicrocodeFmpImageTypeIdGuid = { 0x96d4fdcd, 0x1502, 0x424d, { 0x9d, 0x4c, 0x9b, 0x12, 0xd2, 0xdc, 0xae, 0x5c } }\r
66\r
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67[Protocols]\r
68 ## Include/Protocol/SmmCpuService.h\r
69 gEfiSmmCpuServiceProtocolGuid = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }}\r
529a5a86 70\r
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71#\r
72# [Error.gUefiCpuPkgTokenSpaceGuid]\r
73# 0x80000001 | Invalid value provided.\r
74#\r
75\r
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76[PcdsFeatureFlag]\r
77 ## Indicates if SMM Profile will be enabled.\r
78 # If enabled, instruction executions in and data accesses to memory outside of SMRAM will be logged.\r
79 # This PCD is only for validation purpose. It should be set to false in production.<BR><BR>\r
80 # TRUE - SMM Profile will be enabled.<BR>\r
81 # FALSE - SMM Profile will be disabled.<BR>\r
82 # @Prompt Enable SMM Profile.\r
83 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE|BOOLEAN|0x32132109\r
84\r
85 ## Indicates if the SMM profile log buffer is a ring buffer.\r
86 # If disabled, no additional log can be done when the buffer is full.<BR><BR>\r
87 # TRUE - the SMM profile log buffer is a ring buffer.<BR>\r
88 # FALSE - the SMM profile log buffer is a normal buffer.<BR>\r
89 # @Prompt The SMM profile log buffer is a ring buffer.\r
90 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileRingBuffer|FALSE|BOOLEAN|0x3213210a\r
91\r
92 ## Indicates if SMM Startup AP in a blocking fashion.\r
93 # TRUE - SMM Startup AP in a blocking fashion.<BR>\r
94 # FALSE - SMM Startup AP in a non-blocking fashion.<BR>\r
95 # @Prompt SMM Startup AP in a blocking fashion.\r
96 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|FALSE|BOOLEAN|0x32132108\r
97\r
98 ## Indicates if SMM Stack Guard will be enabled.\r
509f8425 99 # If enabled, stack overflow in SMM can be caught, preventing chaotic consequences.<BR><BR>\r
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100 # TRUE - SMM Stack Guard will be enabled.<BR>\r
101 # FALSE - SMM Stack Guard will be disabled.<BR>\r
102 # @Prompt Enable SMM Stack Guard.\r
509f8425 103 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard|TRUE|BOOLEAN|0x1000001C\r
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104\r
105 ## Indicates if BSP election in SMM will be enabled.\r
106 # If enabled, a BSP will be dynamically elected among all processors in each SMI.\r
107 # Otherwise, processor 0 is always as BSP in each SMI.<BR><BR>\r
108 # TRUE - BSP election in SMM will be enabled.<BR>\r
109 # FALSE - BSP election in SMM will be disabled.<BR>\r
110 # @Prompt Enable BSP election in SMM.\r
111 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE|BOOLEAN|0x32132106\r
112\r
113 ## Indicates if CPU SMM hot-plug will be enabled.<BR><BR>\r
114 # TRUE - SMM CPU hot-plug will be enabled.<BR>\r
115 # FALSE - SMM CPU hot-plug will be disabled.<BR>\r
116 # @Prompt SMM CPU hot-plug.\r
117 gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE|BOOLEAN|0x3213210C\r
118\r
119 ## Indicates if SMM Debug will be enabled.\r
120 # If enabled, hardware breakpoints in SMRAM can be set outside of SMM mode and take effect in SMM.<BR><BR>\r
121 # TRUE - SMM Debug will be enabled.<BR>\r
122 # FALSE - SMM Debug will be disabled.<BR>\r
123 # @Prompt Enable SMM Debug.\r
124 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug|FALSE|BOOLEAN|0x1000001B\r
125\r
126 ## Indicates if lock SMM Feature Control MSR.<BR><BR>\r
127 # TRUE - SMM Feature Control MSR will be locked.<BR>\r
128 # FALSE - SMM Feature Control MSR will not be locked.<BR>\r
129 # @Prompt Lock SMM Feature Control MSR.\r
130 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock|TRUE|BOOLEAN|0x3213210B\r
131\r
7798fb83 132[PcdsFixedAtBuild, PcdsPatchableInModule]\r
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133 ## This value is the CPU Local APIC base address, which aligns the address on a 4-KByte boundary.\r
134 # @Prompt Configure base address of CPU Local APIC\r
abae030a 135 # @Expression 0x80000001 | (gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress & 0xfff) == 0\r
7798fb83 136 gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress|0xfee00000|UINT32|0x00000001\r
529a5a86 137\r
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138 ## Specifies delay value in microseconds after sending out an INIT IPI.\r
139 # @Prompt Configure delay value after send an INIT IPI\r
cf1eb6e6 140 gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10000|UINT32|0x30000002\r
529a5a86 141\r
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142 ## This value specifies the Application Processor (AP) stack size, used for Mp Service, which must\r
143 ## aligns the address on a 4-KByte boundary.\r
144 # @Prompt Configure stack size for Application Processor (AP)\r
145 gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x8000|UINT32|0x00000003\r
7798fb83 146\r
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147 ## Specifies stack size in the temporary RAM. 0 means half of TemporaryRamSize.\r
148 # @Prompt Stack size in the temporary RAM.\r
149 gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0|UINT32|0x10001003\r
150\r
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151 ## Specifies buffer size in bytes to save SMM profile data. The value should be a multiple of 4KB.\r
152 # @Prompt SMM profile data buffer size.\r
153 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileSize|0x200000|UINT32|0x32132107\r
154\r
155 ## Specifies stack size in bytes for each processor in SMM.\r
156 # @Prompt Processor stack size in SMM.\r
157 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x2000|UINT32|0x32132105\r
158\r
159 ## Specifies timeout value in microseconds for the BSP in SMM to wait for all APs to come into SMM.\r
160 # @Prompt AP synchronization timeout value in SMM.\r
161 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000000|UINT64|0x32132104\r
162\r
163 ## Indicates if SMM Code Access Check is enabled.\r
164 # If enabled, the SMM handler cannot execute the code outside SMM regions.\r
165 # This PCD is suggested to TRUE in production image.<BR><BR>\r
166 # TRUE - SMM Code Access Check will be enabled.<BR>\r
167 # FALSE - SMM Code Access Check will be disabled.<BR>\r
168 # @Prompt SMM Code Access Check.\r
169 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable|TRUE|BOOLEAN|0x60000013\r
170\r
171 ## Indicates the CPU synchronization method used when processing an SMI.\r
172 # 0x00 - Traditional CPU synchronization method.<BR>\r
173 # 0x01 - Relaxed CPU synchronization method.<BR>\r
174 # @Prompt SMM CPU Synchronization Method.\r
175 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode|0x00|UINT8|0x60000014\r
176\r
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177 ## Specifies the number of variable MTRRs reserved for OS use. The default number of\r
178 # MTRRs reserved for OS use is 2.\r
179 # @Prompt Number of reserved variable MTRRs.\r
180 gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0x2|UINT32|0x00000015\r
181\r
f79fcf45 182[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]\r
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183 ## Specifies max supported number of Logical Processors.\r
184 # @Prompt Configure max supported number of Logical Processors\r
185 gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|64|UINT32|0x00000002\r
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186 ## Specifies timeout value in microseconds for the BSP to detect all APs for the first time.\r
187 # @Prompt Timeout for the BSP to detect all APs for the first time.\r
188 gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|50000|UINT32|0x00000004\r
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189 ## Specifies the base address of the first microcode Patch in the microcode Region.\r
190 # @Prompt Microcode Region base address.\r
191 gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x00000005\r
192 ## Specifies the size of the microcode Region.\r
193 # @Prompt Microcode Region size.\r
194 gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x00000006\r
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195 ## Specifies the AP wait loop state during POST phase.\r
196 # The value is defined as below.<BR><BR>\r
197 # 1: Place AP in the Hlt-Loop state.<BR>\r
198 # 2: Place AP in the Mwait-Loop state.<BR>\r
199 # 3: Place AP in the Run-Loop state.<BR>\r
200 # @Prompt The AP wait loop state.\r
201 # @ValidRange 0x80000001 | 1 - 3\r
202 gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|1|UINT8|0x60008006\r
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203 ## Specifies the AP target C-state for Mwait during POST phase.\r
204 # The default value 0 means C1 state.\r
205 # The value is defined as below.<BR><BR>\r
206 # @Prompt The specified AP target C-state for Mwait.\r
207 gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0|UINT8|0x00000007\r
f79fcf45 208\r
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209 ## Indicates if SMM uses static page table.\r
210 # If enabled, SMM will not use on-demand paging. SMM will build static page table for all memory.<BR><BR>\r
211 # This flag only impacts X64 build, because SMM alway builds static page table for IA32.\r
212 # TRUE - SMM uses static page table for all memory.<BR>\r
213 # FALSE - SMM uses static page table for below 4G memory and use on-demand paging for above 4G memory.<BR>\r
214 # @Prompt Use static page table for all memory in SMM.\r
215 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStaticPageTable|TRUE|BOOLEAN|0x3213210D\r
216\r
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217[PcdsDynamic, PcdsDynamicEx]\r
218 ## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.\r
219 # @Prompt The pointer to a CPU S3 data buffer.\r
220 # @ValidList 0x80000001 | 0\r
221 gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0x0|UINT64|0x60000010\r
222\r
223 ## Contains the pointer to a CPU Hot Plug Data structure if CPU hot-plug is supported.\r
224 # @Prompt The pointer to CPU Hot Plug Data.\r
225 # @ValidList 0x80000001 | 0\r
226 gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress|0x0|UINT64|0x60000011\r
227\r
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228[UserExtensions.TianoCore."ExtraFiles"]\r
229 UefiCpuPkgExtra.uni\r