projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 7798fb83 | 1 | ## @file UefiCpuPkg.dec\r |
| 7798fb83 HT |
2 | # This Package provides UEFI compatible CPU modules and libraries.\r |
| 3 | #\r | |
| 3eb69b08 | 4 | # Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.<BR>\r |
| 7798fb83 | 5 | #\r |
| 0acd8697 | 6 | # SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 7798fb83 HT |
7 | #\r |
| 8 | ##\r | |
| 9 | \r | |
| 10 | [Defines]\r | |
| 11 | DEC_SPECIFICATION = 0x00010005\r | |
| 12 | PACKAGE_NAME = UefiCpuPkg\r | |
| abae030a | 13 | PACKAGE_UNI_FILE = UefiCpuPkg.uni\r |
| 7798fb83 | 14 | PACKAGE_GUID = 2171df9b-0d39-45aa-ac37-2de190010d23\r |
| 30142a32 | 15 | PACKAGE_VERSION = 0.90\r |
| 7798fb83 HT |
16 | \r |
| 17 | [Includes]\r | |
| 18 | Include\r | |
| 19 | \r | |
| 20 | [LibraryClasses]\r | |
| 21 | ## @libraryclass Defines some routines that are generic for IA32 family CPU\r | |
| 22 | ## to be UEFI specification compliant.\r | |
| 23 | ##\r | |
| 24 | UefiCpuLib|Include/Library/UefiCpuLib.h\r | |
| 25 | \r | |
| 548013c0 JF |
26 | ## @libraryclass Defines some routines that are used to register/manage/program\r |
| 27 | ## CPU features.\r | |
| 28 | ##\r | |
| 245e98bf | 29 | RegisterCpuFeaturesLib|Include/Library/RegisterCpuFeaturesLib.h\r |
| 548013c0 | 30 | \r |
| 7798fb83 HT |
31 | [LibraryClasses.IA32, LibraryClasses.X64]\r |
| 32 | ## @libraryclass Provides functions to manage MTRR settings on IA32 and X64 CPUs.\r | |
| 33 | ##\r | |
| 34 | MtrrLib|Include/Library/MtrrLib.h\r | |
| 35 | \r | |
| 36 | ## @libraryclass Provides functions to manage the Local APIC on IA32 and X64 CPUs.\r | |
| 37 | ##\r | |
| 38 | LocalApicLib|Include/Library/LocalApicLib.h\r | |
| d947a4cc MK |
39 | \r |
| 40 | ## @libraryclass Provides platform specific initialization functions in the SEC phase.\r | |
| 41 | ##\r | |
| 42 | PlatformSecLib|Include/Library/PlatformSecLib.h\r | |
| 529a5a86 | 43 | \r |
| 406c7200 MK |
44 | ## @libraryclass Public include file for the SMM CPU Platform Hook Library.\r |
| 45 | ##\r | |
| 46 | SmmCpuPlatformHookLib|Include/Library/SmmCpuPlatformHookLib.h\r | |
| 529a5a86 | 47 | \r |
| 406c7200 MK |
48 | ## @libraryclass Provides the CPU specific programming for PiSmmCpuDxeSmm module.\r |
| 49 | ##\r | |
| 50 | SmmCpuFeaturesLib|Include/Library/SmmCpuFeaturesLib.h\r | |
| 51 | \r | |
| 87896d03 JF |
52 | ## @libraryclass Provides functions to support MP services on CpuMpPei and CpuDxe module.\r |
| 53 | ##\r | |
| 54 | MpInitLib|Include/Library/MpInitLib.h\r | |
| 55 | \r | |
| 7798fb83 HT |
56 | [Guids]\r |
| 57 | gUefiCpuPkgTokenSpaceGuid = { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa, 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}\r | |
| f7c11c53 | 58 | gMsegSmramGuid = { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1, 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }}\r |
| 7798fb83 | 59 | \r |
| 98f4a565 JF |
60 | ## Include/Guid/CpuFeaturesSetDone.h\r |
| 61 | gEdkiiCpuFeaturesSetDoneGuid = { 0xa82485ce, 0xad6b, 0x4101, { 0x99, 0xd3, 0xe1, 0x35, 0x8c, 0x9e, 0x7e, 0x37 }}\r | |
| 62 | \r | |
| e000e774 JF |
63 | ## Include/Guid/CpuFeaturesInitDone.h\r |
| 64 | gEdkiiCpuFeaturesInitDoneGuid = { 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }}\r | |
| 65 | \r | |
| 406c7200 MK |
66 | [Protocols]\r |
| 67 | ## Include/Protocol/SmmCpuService.h\r | |
| 68 | gEfiSmmCpuServiceProtocolGuid = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }}\r | |
| 529a5a86 | 69 | \r |
| f7c11c53 MK |
70 | ## Include/Protocol/SmMonitorInit.h\r |
| 71 | gEfiSmMonitorInitProtocolGuid = { 0x228f344d, 0xb3de, 0x43bb, { 0xa4, 0xd7, 0xea, 0x20, 0xb, 0x1b, 0x14, 0x82 }}\r | |
| 72 | \r | |
| abae030a LG |
73 | #\r |
| 74 | # [Error.gUefiCpuPkgTokenSpaceGuid]\r | |
| 75 | # 0x80000001 | Invalid value provided.\r | |
| 76 | #\r | |
| 77 | \r | |
| ebfbb701 ED |
78 | [Ppis]\r |
| 79 | gEdkiiPeiMpServices2PpiGuid = { 0x5cb9cb3d, 0x31a4, 0x480c, { 0x94, 0x98, 0x29, 0xd2, 0x69, 0xba, 0xcf, 0xba}}\r | |
| 80 | \r | |
| 529a5a86 MK |
81 | [PcdsFeatureFlag]\r |
| 82 | ## Indicates if SMM Profile will be enabled.\r | |
| 83 | # If enabled, instruction executions in and data accesses to memory outside of SMRAM will be logged.\r | |
| f64a597d RN |
84 | # In X64 build, it could not be enabled when PcdCpuSmmRestrictedMemoryAccess is TRUE.\r |
| 85 | # In IA32 build, the page table memory is not marked as read-only when it is enabled.\r | |
| 529a5a86 MK |
86 | # This PCD is only for validation purpose. It should be set to false in production.<BR><BR>\r |
| 87 | # TRUE - SMM Profile will be enabled.<BR>\r | |
| 88 | # FALSE - SMM Profile will be disabled.<BR>\r | |
| 89 | # @Prompt Enable SMM Profile.\r | |
| 90 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE|BOOLEAN|0x32132109\r | |
| 91 | \r | |
| 92 | ## Indicates if the SMM profile log buffer is a ring buffer.\r | |
| 93 | # If disabled, no additional log can be done when the buffer is full.<BR><BR>\r | |
| 94 | # TRUE - the SMM profile log buffer is a ring buffer.<BR>\r | |
| 95 | # FALSE - the SMM profile log buffer is a normal buffer.<BR>\r | |
| 96 | # @Prompt The SMM profile log buffer is a ring buffer.\r | |
| 97 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileRingBuffer|FALSE|BOOLEAN|0x3213210a\r | |
| 98 | \r | |
| 99 | ## Indicates if SMM Startup AP in a blocking fashion.\r | |
| 100 | # TRUE - SMM Startup AP in a blocking fashion.<BR>\r | |
| 101 | # FALSE - SMM Startup AP in a non-blocking fashion.<BR>\r | |
| 102 | # @Prompt SMM Startup AP in a blocking fashion.\r | |
| 103 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|FALSE|BOOLEAN|0x32132108\r | |
| 104 | \r | |
| 105 | ## Indicates if SMM Stack Guard will be enabled.\r | |
| 509f8425 | 106 | # If enabled, stack overflow in SMM can be caught, preventing chaotic consequences.<BR><BR>\r |
| 529a5a86 MK |
107 | # TRUE - SMM Stack Guard will be enabled.<BR>\r |
| 108 | # FALSE - SMM Stack Guard will be disabled.<BR>\r | |
| 109 | # @Prompt Enable SMM Stack Guard.\r | |
| 509f8425 | 110 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard|TRUE|BOOLEAN|0x1000001C\r |
| 529a5a86 MK |
111 | \r |
| 112 | ## Indicates if BSP election in SMM will be enabled.\r | |
| 113 | # If enabled, a BSP will be dynamically elected among all processors in each SMI.\r | |
| 114 | # Otherwise, processor 0 is always as BSP in each SMI.<BR><BR>\r | |
| 115 | # TRUE - BSP election in SMM will be enabled.<BR>\r | |
| 116 | # FALSE - BSP election in SMM will be disabled.<BR>\r | |
| 117 | # @Prompt Enable BSP election in SMM.\r | |
| 118 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE|BOOLEAN|0x32132106\r | |
| 119 | \r | |
| 120 | ## Indicates if CPU SMM hot-plug will be enabled.<BR><BR>\r | |
| 121 | # TRUE - SMM CPU hot-plug will be enabled.<BR>\r | |
| 122 | # FALSE - SMM CPU hot-plug will be disabled.<BR>\r | |
| 123 | # @Prompt SMM CPU hot-plug.\r | |
| 124 | gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE|BOOLEAN|0x3213210C\r | |
| 125 | \r | |
| 126 | ## Indicates if SMM Debug will be enabled.\r | |
| 127 | # If enabled, hardware breakpoints in SMRAM can be set outside of SMM mode and take effect in SMM.<BR><BR>\r | |
| 128 | # TRUE - SMM Debug will be enabled.<BR>\r | |
| 129 | # FALSE - SMM Debug will be disabled.<BR>\r | |
| 130 | # @Prompt Enable SMM Debug.\r | |
| 131 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug|FALSE|BOOLEAN|0x1000001B\r | |
| 132 | \r | |
| 133 | ## Indicates if lock SMM Feature Control MSR.<BR><BR>\r | |
| 134 | # TRUE - SMM Feature Control MSR will be locked.<BR>\r | |
| 135 | # FALSE - SMM Feature Control MSR will not be locked.<BR>\r | |
| 136 | # @Prompt Lock SMM Feature Control MSR.\r | |
| 137 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock|TRUE|BOOLEAN|0x3213210B\r | |
| 138 | \r | |
| adb9f50e JW |
139 | [PcdsFixedAtBuild]\r |
| 140 | ## List of exception vectors which need switching stack.\r | |
| 141 | # This PCD will only take into effect if PcdCpuStackGuard is enabled.\r | |
| 142 | # By default exception #DD(8), #PF(14) are supported.\r | |
| 143 | # @Prompt Specify exception vectors which need switching stack.\r | |
| 144 | gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList|{0x08, 0x0E}|VOID*|0x30002000\r | |
| 145 | \r | |
| 146 | ## Size of good stack for an exception.\r | |
| 147 | # This PCD will only take into effect if PcdCpuStackGuard is enabled.\r | |
| 148 | # @Prompt Specify size of good stack of exception which need switching stack.\r | |
| 149 | gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize|2048|UINT32|0x30002001\r | |
| 150 | \r | |
| 7798fb83 | 151 | [PcdsFixedAtBuild, PcdsPatchableInModule]\r |
| 529a5a86 MK |
152 | ## This value is the CPU Local APIC base address, which aligns the address on a 4-KByte boundary.\r |
| 153 | # @Prompt Configure base address of CPU Local APIC\r | |
| abae030a | 154 | # @Expression 0x80000001 | (gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress & 0xfff) == 0\r |
| 7798fb83 | 155 | gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress|0xfee00000|UINT32|0x00000001\r |
| 529a5a86 | 156 | \r |
| abae030a LG |
157 | ## Specifies delay value in microseconds after sending out an INIT IPI.\r |
| 158 | # @Prompt Configure delay value after send an INIT IPI\r | |
| cf1eb6e6 | 159 | gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10000|UINT32|0x30000002\r |
| 529a5a86 | 160 | \r |
| 6a26a597 CF |
161 | ## This value specifies the Application Processor (AP) stack size, used for Mp Service, which must\r |
| 162 | ## aligns the address on a 4-KByte boundary.\r | |
| 163 | # @Prompt Configure stack size for Application Processor (AP)\r | |
| 164 | gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x8000|UINT32|0x00000003\r | |
| 7798fb83 | 165 | \r |
| d947a4cc MK |
166 | ## Specifies stack size in the temporary RAM. 0 means half of TemporaryRamSize.\r |
| 167 | # @Prompt Stack size in the temporary RAM.\r | |
| 168 | gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0|UINT32|0x10001003\r | |
| 169 | \r | |
| 529a5a86 MK |
170 | ## Specifies buffer size in bytes to save SMM profile data. The value should be a multiple of 4KB.\r |
| 171 | # @Prompt SMM profile data buffer size.\r | |
| 172 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileSize|0x200000|UINT32|0x32132107\r | |
| 173 | \r | |
| 174 | ## Specifies stack size in bytes for each processor in SMM.\r | |
| 175 | # @Prompt Processor stack size in SMM.\r | |
| 176 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x2000|UINT32|0x32132105\r | |
| 177 | \r | |
| 3eb69b08 JY |
178 | ## Specifies shadow stack size in bytes for each processor in SMM.\r |
| 179 | # @Prompt Processor shadow stack size in SMM.\r | |
| 180 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmShadowStackSize|0x2000|UINT32|0x3213210E\r | |
| 181 | \r | |
| 529a5a86 MK |
182 | ## Indicates if SMM Code Access Check is enabled.\r |
| 183 | # If enabled, the SMM handler cannot execute the code outside SMM regions.\r | |
| 184 | # This PCD is suggested to TRUE in production image.<BR><BR>\r | |
| 185 | # TRUE - SMM Code Access Check will be enabled.<BR>\r | |
| 186 | # FALSE - SMM Code Access Check will be disabled.<BR>\r | |
| 187 | # @Prompt SMM Code Access Check.\r | |
| 188 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable|TRUE|BOOLEAN|0x60000013\r | |
| 189 | \r | |
| 46309b11 JF |
190 | ## Specifies the number of variable MTRRs reserved for OS use. The default number of\r |
| 191 | # MTRRs reserved for OS use is 2.\r | |
| 192 | # @Prompt Number of reserved variable MTRRs.\r | |
| 193 | gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0x2|UINT32|0x00000015\r | |
| 194 | \r | |
| f7c11c53 MK |
195 | ## Specifies buffer size in bytes for STM exception stack. The value should be a multiple of 4KB.\r |
| 196 | # @Prompt STM exception stack size.\r | |
| 197 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStmExceptionStackSize|0x1000|UINT32|0x32132111\r | |
| 198 | \r | |
| 199 | ## Specifies buffer size in bytes of MSEG. The value should be a multiple of 4KB.\r | |
| 200 | # @Prompt MSEG size.\r | |
| 201 | gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize|0x200000|UINT32|0x32132112\r | |
| 202 | \r | |
| 98eb0095 JF |
203 | ## Specifies the supported CPU features bit in array.\r |
| 204 | # @Prompt Supported CPU features.\r | |
| 7eee4e1e JF |
205 | gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSupport|{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}|VOID*|0x00000016\r |
| 206 | \r | |
| 98eb0095 JF |
207 | ## Specifies if CPU features will be initialized after SMM relocation.\r |
| 208 | # @Prompt If CPU features will be initialized after SMM relocation.\r | |
| 82e75ac6 JF |
209 | gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitAfterSmmRelocation|FALSE|BOOLEAN|0x0000001C\r |
| 210 | \r | |
| 98eb0095 JF |
211 | ## Specifies if CPU features will be initialized during S3 resume.\r |
| 212 | # @Prompt If CPU features will be initialized during S3 resume.\r | |
| 82e75ac6 JF |
213 | gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitOnS3Resume|FALSE|BOOLEAN|0x0000001D\r |
| 214 | \r | |
| 30781feb DK |
215 | ## Specifies CPUID Leaf 0x15 Time Stamp Counter and Nominal Core Crystal Clock Frequency.\r |
| 216 | # TSC Frequency = ECX (core crystal clock frequency) * EBX/EAX.\r | |
| 217 | # Intel Xeon Processor Scalable Family with CPUID signature 06_55H = 25000000 (25MHz)\r | |
| 218 | # 6th and 7th generation Intel Core processors and Intel Xeon W Processor Family = 24000000 (24MHz)\r | |
| 219 | # Intel Atom processors based on Goldmont Microarchitecture with CPUID signature 06_5CH = 19200000 (19.2MHz)\r | |
| 220 | # @Prompt This PCD is the nominal frequency of the core crystal clock in Hz as is CPUID Leaf 0x15:ECX\r | |
| 221 | gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency|24000000|UINT64|0x32132113\r | |
| 222 | \r | |
| f79fcf45 | 223 | [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]\r |
| b1e01bd4 JF |
224 | ## Specifies max supported number of Logical Processors.\r |
| 225 | # @Prompt Configure max supported number of Logical Processors\r | |
| 226 | gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|64|UINT32|0x00000002\r | |
| f79fcf45 JF |
227 | ## Specifies timeout value in microseconds for the BSP to detect all APs for the first time.\r |
| 228 | # @Prompt Timeout for the BSP to detect all APs for the first time.\r | |
| 229 | gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|50000|UINT32|0x00000004\r | |
| 30314463 JF |
230 | ## Specifies the base address of the first microcode Patch in the microcode Region.\r |
| 231 | # @Prompt Microcode Region base address.\r | |
| 232 | gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x00000005\r | |
| 233 | ## Specifies the size of the microcode Region.\r | |
| 234 | # @Prompt Microcode Region size.\r | |
| 235 | gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x00000006\r | |
| 54a3e8c9 JF |
236 | ## Specifies the AP wait loop state during POST phase.\r |
| 237 | # The value is defined as below.<BR><BR>\r | |
| 238 | # 1: Place AP in the Hlt-Loop state.<BR>\r | |
| 239 | # 2: Place AP in the Mwait-Loop state.<BR>\r | |
| 240 | # 3: Place AP in the Run-Loop state.<BR>\r | |
| 241 | # @Prompt The AP wait loop state.\r | |
| 242 | # @ValidRange 0x80000001 | 1 - 3\r | |
| 243 | gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|1|UINT8|0x60008006\r | |
| 9d39ed93 JF |
244 | ## Specifies the AP target C-state for Mwait during POST phase.\r |
| 245 | # The default value 0 means C1 state.\r | |
| 246 | # The value is defined as below.<BR><BR>\r | |
| 247 | # @Prompt The specified AP target C-state for Mwait.\r | |
| 248 | gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0|UINT8|0x00000007\r | |
| f79fcf45 | 249 | \r |
| 28b020b5 | 250 | ## Indicates if SMM uses static page table.\r |
| 1015fb3c SZ |
251 | # If enabled, SMM will not use on-demand paging. SMM will build static page table for all memory.\r |
| 252 | # This flag only impacts X64 build, because SMM always builds static page table for IA32.\r | |
| 253 | # It could not be enabled at the same time with SMM profile feature (PcdCpuSmmProfileEnable).\r | |
| 254 | # It could not be enabled also at the same time with heap guard feature for SMM\r | |
| 255 | # (PcdHeapGuardPropertyMask in MdeModulePkg).<BR><BR>\r | |
| 28b020b5 JY |
256 | # TRUE - SMM uses static page table for all memory.<BR>\r |
| 257 | # FALSE - SMM uses static page table for below 4G memory and use on-demand paging for above 4G memory.<BR>\r | |
| 258 | # @Prompt Use static page table for all memory in SMM.\r | |
| 259 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStaticPageTable|TRUE|BOOLEAN|0x3213210D\r | |
| 260 | \r | |
| b43dd229 LE |
261 | ## Specifies timeout value in microseconds for the BSP in SMM to wait for all APs to come into SMM.\r |
| 262 | # @Prompt AP synchronization timeout value in SMM.\r | |
| 263 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000000|UINT64|0x32132104\r | |
| 264 | \r | |
| 265 | ## Indicates the CPU synchronization method used when processing an SMI.\r | |
| 266 | # 0x00 - Traditional CPU synchronization method.<BR>\r | |
| 267 | # 0x01 - Relaxed CPU synchronization method.<BR>\r | |
| 268 | # @Prompt SMM CPU Synchronization Method.\r | |
| 269 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode|0x00|UINT8|0x60000014\r | |
| 270 | \r | |
| 0a70d1c3 JF |
271 | ## Specifies the On-demand clock modulation duty cycle when ACPI feature is enabled.\r |
| 272 | # @Prompt The encoded values for target duty cycle modulation.\r | |
| 273 | # @ValidRange 0x80000001 | 0 - 15\r | |
| 274 | gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle|0x0|UINT8|0x0000001A\r | |
| 275 | \r | |
| 276 | ## Indicates if the current boot is a power-on reset.<BR><BR>\r | |
| 277 | # TRUE - Current boot is a power-on reset.<BR>\r | |
| 278 | # FALSE - Current boot is not a power-on reset.<BR>\r | |
| 279 | # @Prompt Current boot is a power-on reset.\r | |
| 280 | gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset|FALSE|BOOLEAN|0x0000001B\r | |
| 281 | \r | |
| 87184487 RN |
282 | [PcdsFixedAtBuild.X64, PcdsPatchableInModule.X64, PcdsDynamic.X64, PcdsDynamicEx.X64]\r |
| 283 | ## Indicate access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.\r | |
| 284 | # MMIO access is always allowed regardless of the value of this PCD.\r | |
| 285 | # Loose of such restriction is only required by RAS components in X64 platforms.\r | |
| 286 | # The PCD value is considered as constantly TRUE in IA32 platforms.\r | |
| 287 | # When the PCD value is TRUE, page table is initialized to cover all memory spaces\r | |
| 288 | # and the memory occupied by page table is protected by page table itself as read-only.\r | |
| f64a597d RN |
289 | # In X64 build, it cannot be enabled at the same time with SMM profile feature (PcdCpuSmmProfileEnable).\r |
| 290 | # In X64 build, it could not be enabled also at the same time with heap guard feature for SMM\r | |
| 291 | # (PcdHeapGuardPropertyMask in MdeModulePkg).\r | |
| 292 | # In IA32 build, page table memory is not marked as read-only when either SMM profile feature (PcdCpuSmmProfileEnable)\r | |
| 293 | # or heap guard feature for SMM (PcdHeapGuardPropertyMask in MdeModulePkg) is enabled.\r | |
| 87184487 RN |
294 | # TRUE - Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.<BR>\r |
| 295 | # FALSE - Access to any type of non-SMRAM memory after SmmReadyToLock is allowed.<BR>\r | |
| 296 | # @Prompt Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.\r | |
| 297 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0x3213210F\r | |
| 298 | \r | |
| 529a5a86 MK |
299 | [PcdsDynamic, PcdsDynamicEx]\r |
| 300 | ## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.\r | |
| 301 | # @Prompt The pointer to a CPU S3 data buffer.\r | |
| 302 | # @ValidList 0x80000001 | 0\r | |
| 303 | gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0x0|UINT64|0x60000010\r | |
| 304 | \r | |
| 305 | ## Contains the pointer to a CPU Hot Plug Data structure if CPU hot-plug is supported.\r | |
| 306 | # @Prompt The pointer to CPU Hot Plug Data.\r | |
| 307 | # @ValidList 0x80000001 | 0\r | |
| 308 | gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress|0x0|UINT64|0x60000011\r | |
| 309 | \r | |
| 7eee4e1e JF |
310 | ## Indicates processor feature capabilities, each bit corresponding to a specific feature.\r |
| 311 | # @Prompt Processor feature capabilities.\r | |
| 312 | # @ValidList 0x80000001 | 0\r | |
| 313 | gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000018\r | |
| 314 | \r | |
| 6214ffb4 ED |
315 | ## As input, specifies user's desired settings for enabling/disabling processor features.\r |
| 316 | ## As output, specifies actual settings for processor features, each bit corresponding to a specific feature.\r | |
| 317 | # @Prompt As input, specifies user's desired processor feature settings. As output, specifies actual processor feature settings.\r | |
| 7eee4e1e JF |
318 | # @ValidList 0x80000001 | 0\r |
| 319 | gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000019\r | |
| 320 | \r | |
| 234d4c5f | 321 | ## Contains the size of memory required when CPU processor trace is enabled.<BR><BR>\r |
| 34b6a0e2 ED |
322 | # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>\r |
| 323 | # This PCD is ignored if CPU processor trace is disabled.<BR><BR>\r | |
| 324 | # Default value is 0x00 which means 4KB of memory is allocated if CPU processor trace is enabled.<BR>\r | |
| 234d4c5f ED |
325 | # 0x0 - 4K.<BR>\r |
| 326 | # 0x1 - 8K.<BR>\r | |
| 327 | # 0x2 - 16K.<BR>\r | |
| 328 | # 0x3 - 32K.<BR>\r | |
| 329 | # 0x4 - 64K.<BR>\r | |
| 330 | # 0x5 - 128K.<BR>\r | |
| 331 | # 0x6 - 256K.<BR>\r | |
| 332 | # 0x7 - 512K.<BR>\r | |
| 333 | # 0x8 - 1M.<BR>\r | |
| 334 | # 0x9 - 2M.<BR>\r | |
| 335 | # 0xA - 4M.<BR>\r | |
| 336 | # 0xB - 8M.<BR>\r | |
| 337 | # 0xC - 16M.<BR>\r | |
| 338 | # 0xD - 32M.<BR>\r | |
| 339 | # 0xE - 64M.<BR>\r | |
| 340 | # 0xF - 128M.<BR>\r | |
| 34b6a0e2 ED |
341 | # @Prompt The memory size used for processor trace if processor trace is enabled.\r |
| 342 | # @ValidRange 0x80000001 | 0 - 0xF\r | |
| 343 | gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize|0x0|UINT32|0x60000012\r | |
| c7399a0c | 344 | \r |
| 234d4c5f | 345 | ## Contains the processor trace output scheme when CPU processor trace is enabled.<BR><BR>\r |
| 34b6a0e2 ED |
346 | # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>\r |
| 347 | # This PCD is ignored if CPU processor trace is disabled.<BR><BR>\r | |
| 348 | # Default value is 0 which means single range output scheme will be used if CPU processor trace is enabled.<BR>\r | |
| 234d4c5f ED |
349 | # 0 - Single Range output scheme.<BR>\r |
| 350 | # 1 - ToPA(Table of physical address) scheme.<BR>\r | |
| 34b6a0e2 ED |
351 | # @Prompt The processor trace output scheme used when processor trace is enabled.\r |
| 352 | # @ValidRange 0x80000001 | 0 - 1\r | |
| 353 | gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme|0x0|UINT8|0x60000015\r | |
| c7399a0c | 354 | \r |
| abae030a LG |
355 | [UserExtensions.TianoCore."ExtraFiles"]\r |
| 356 | UefiCpuPkgExtra.uni\r |