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7798fb83 1## @file UefiCpuPkg.dec\r
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2# This Package provides UEFI compatible CPU modules and libraries.\r
3#\r
4a68176c 4# Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.<BR>\r
7798fb83 5#\r
0acd8697 6# SPDX-License-Identifier: BSD-2-Clause-Patent\r
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7#\r
8##\r
9\r
10[Defines]\r
11 DEC_SPECIFICATION = 0x00010005\r
12 PACKAGE_NAME = UefiCpuPkg\r
abae030a 13 PACKAGE_UNI_FILE = UefiCpuPkg.uni\r
7798fb83 14 PACKAGE_GUID = 2171df9b-0d39-45aa-ac37-2de190010d23\r
30142a32 15 PACKAGE_VERSION = 0.90\r
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16\r
17[Includes]\r
18 Include\r
19\r
20[LibraryClasses]\r
21 ## @libraryclass Defines some routines that are generic for IA32 family CPU\r
22 ## to be UEFI specification compliant.\r
23 ##\r
24 UefiCpuLib|Include/Library/UefiCpuLib.h\r
25\r
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26 ## @libraryclass Defines some routines that are used to register/manage/program\r
27 ## CPU features.\r
28 ##\r
245e98bf 29 RegisterCpuFeaturesLib|Include/Library/RegisterCpuFeaturesLib.h\r
548013c0 30\r
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31[LibraryClasses.IA32, LibraryClasses.X64]\r
32 ## @libraryclass Provides functions to manage MTRR settings on IA32 and X64 CPUs.\r
33 ##\r
34 MtrrLib|Include/Library/MtrrLib.h\r
35\r
36 ## @libraryclass Provides functions to manage the Local APIC on IA32 and X64 CPUs.\r
37 ##\r
38 LocalApicLib|Include/Library/LocalApicLib.h\r
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39\r
40 ## @libraryclass Provides platform specific initialization functions in the SEC phase.\r
41 ##\r
42 PlatformSecLib|Include/Library/PlatformSecLib.h\r
529a5a86 43\r
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44 ## @libraryclass Public include file for the SMM CPU Platform Hook Library.\r
45 ##\r
46 SmmCpuPlatformHookLib|Include/Library/SmmCpuPlatformHookLib.h\r
529a5a86 47\r
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48 ## @libraryclass Provides the CPU specific programming for PiSmmCpuDxeSmm module.\r
49 ##\r
50 SmmCpuFeaturesLib|Include/Library/SmmCpuFeaturesLib.h\r
51\r
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52 ## @libraryclass Provides functions to support MP services on CpuMpPei and CpuDxe module.\r
53 ##\r
54 MpInitLib|Include/Library/MpInitLib.h\r
55\r
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56 ## @libraryclass Provides function to support VMGEXIT processing.\r
57 VmgExitLib|Include/Library/VmgExitLib.h\r
58\r
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59 ## @libraryclass Provides function to get CPU cache information.\r
60 CpuCacheInfoLib|Include/Library/CpuCacheInfoLib.h\r
61\r
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62 ## @libraryclass Provides function for loading microcode.\r
63 MicrocodeLib|Include/Library/MicrocodeLib.h\r
64\r
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65[Guids]\r
66 gUefiCpuPkgTokenSpaceGuid = { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa, 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}\r
f7c11c53 67 gMsegSmramGuid = { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1, 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }}\r
7798fb83 68\r
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69 ## Include/Guid/CpuFeaturesSetDone.h\r
70 gEdkiiCpuFeaturesSetDoneGuid = { 0xa82485ce, 0xad6b, 0x4101, { 0x99, 0xd3, 0xe1, 0x35, 0x8c, 0x9e, 0x7e, 0x37 }}\r
71\r
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72 ## Include/Guid/CpuFeaturesInitDone.h\r
73 gEdkiiCpuFeaturesInitDoneGuid = { 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }}\r
74\r
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75 ## Include/Guid/MicrocodePatchHob.h\r
76 gEdkiiMicrocodePatchHobGuid = { 0xd178f11d, 0x8716, 0x418e, { 0xa1, 0x31, 0x96, 0x7d, 0x2a, 0xc4, 0x28, 0x43 }}\r
77\r
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78[Protocols]\r
79 ## Include/Protocol/SmmCpuService.h\r
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80 gEfiSmmCpuServiceProtocolGuid = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }}\r
81 gEdkiiSmmCpuRendezvousProtocolGuid = { 0xaa00d50b, 0x4911, 0x428f, { 0xb9, 0x1a, 0xa5, 0x9d, 0xdb, 0x13, 0xe2, 0x4c }}\r
529a5a86 82\r
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83 ## Include/Protocol/SmMonitorInit.h\r
84 gEfiSmMonitorInitProtocolGuid = { 0x228f344d, 0xb3de, 0x43bb, { 0xa4, 0xd7, 0xea, 0x20, 0xb, 0x1b, 0x14, 0x82 }}\r
85\r
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86#\r
87# [Error.gUefiCpuPkgTokenSpaceGuid]\r
88# 0x80000001 | Invalid value provided.\r
89#\r
90\r
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91[Ppis]\r
92 gEdkiiPeiMpServices2PpiGuid = { 0x5cb9cb3d, 0x31a4, 0x480c, { 0x94, 0x98, 0x29, 0xd2, 0x69, 0xba, 0xcf, 0xba}}\r
93\r
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94 ## Include/Ppi/ShadowMicrocode.h\r
95 gEdkiiPeiShadowMicrocodePpiGuid = { 0x430f6965, 0x9a69, 0x41c5, { 0x93, 0xed, 0x8b, 0xf0, 0x64, 0x35, 0xc1, 0xc6 }}\r
96\r
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97 ## Include/Ppi/RepublishSecPpi.h\r
98 gRepublishSecPpiPpiGuid = { 0x27a71b1e, 0x73ee, 0x43d6, { 0xac, 0xe3, 0x52, 0x1a, 0x2d, 0xc5, 0xd0, 0x92 }}\r
99\r
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100[PcdsFeatureFlag]\r
101 ## Indicates if SMM Profile will be enabled.\r
102 # If enabled, instruction executions in and data accesses to memory outside of SMRAM will be logged.\r
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103 # In X64 build, it could not be enabled when PcdCpuSmmRestrictedMemoryAccess is TRUE.\r
104 # In IA32 build, the page table memory is not marked as read-only when it is enabled.\r
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105 # This PCD is only for validation purpose. It should be set to false in production.<BR><BR>\r
106 # TRUE - SMM Profile will be enabled.<BR>\r
107 # FALSE - SMM Profile will be disabled.<BR>\r
108 # @Prompt Enable SMM Profile.\r
109 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE|BOOLEAN|0x32132109\r
110\r
111 ## Indicates if the SMM profile log buffer is a ring buffer.\r
112 # If disabled, no additional log can be done when the buffer is full.<BR><BR>\r
113 # TRUE - the SMM profile log buffer is a ring buffer.<BR>\r
114 # FALSE - the SMM profile log buffer is a normal buffer.<BR>\r
115 # @Prompt The SMM profile log buffer is a ring buffer.\r
116 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileRingBuffer|FALSE|BOOLEAN|0x3213210a\r
117\r
118 ## Indicates if SMM Startup AP in a blocking fashion.\r
119 # TRUE - SMM Startup AP in a blocking fashion.<BR>\r
120 # FALSE - SMM Startup AP in a non-blocking fashion.<BR>\r
121 # @Prompt SMM Startup AP in a blocking fashion.\r
122 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|FALSE|BOOLEAN|0x32132108\r
123\r
124 ## Indicates if SMM Stack Guard will be enabled.\r
509f8425 125 # If enabled, stack overflow in SMM can be caught, preventing chaotic consequences.<BR><BR>\r
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126 # TRUE - SMM Stack Guard will be enabled.<BR>\r
127 # FALSE - SMM Stack Guard will be disabled.<BR>\r
128 # @Prompt Enable SMM Stack Guard.\r
509f8425 129 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard|TRUE|BOOLEAN|0x1000001C\r
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130\r
131 ## Indicates if BSP election in SMM will be enabled.\r
132 # If enabled, a BSP will be dynamically elected among all processors in each SMI.\r
133 # Otherwise, processor 0 is always as BSP in each SMI.<BR><BR>\r
134 # TRUE - BSP election in SMM will be enabled.<BR>\r
135 # FALSE - BSP election in SMM will be disabled.<BR>\r
136 # @Prompt Enable BSP election in SMM.\r
137 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE|BOOLEAN|0x32132106\r
138\r
139 ## Indicates if CPU SMM hot-plug will be enabled.<BR><BR>\r
140 # TRUE - SMM CPU hot-plug will be enabled.<BR>\r
141 # FALSE - SMM CPU hot-plug will be disabled.<BR>\r
142 # @Prompt SMM CPU hot-plug.\r
143 gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE|BOOLEAN|0x3213210C\r
144\r
145 ## Indicates if SMM Debug will be enabled.\r
146 # If enabled, hardware breakpoints in SMRAM can be set outside of SMM mode and take effect in SMM.<BR><BR>\r
147 # TRUE - SMM Debug will be enabled.<BR>\r
148 # FALSE - SMM Debug will be disabled.<BR>\r
149 # @Prompt Enable SMM Debug.\r
150 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug|FALSE|BOOLEAN|0x1000001B\r
151\r
152 ## Indicates if lock SMM Feature Control MSR.<BR><BR>\r
153 # TRUE - SMM Feature Control MSR will be locked.<BR>\r
154 # FALSE - SMM Feature Control MSR will not be locked.<BR>\r
155 # @Prompt Lock SMM Feature Control MSR.\r
156 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock|TRUE|BOOLEAN|0x3213210B\r
157\r
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158[PcdsFixedAtBuild]\r
159 ## List of exception vectors which need switching stack.\r
160 # This PCD will only take into effect if PcdCpuStackGuard is enabled.\r
161 # By default exception #DD(8), #PF(14) are supported.\r
162 # @Prompt Specify exception vectors which need switching stack.\r
163 gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList|{0x08, 0x0E}|VOID*|0x30002000\r
164\r
165 ## Size of good stack for an exception.\r
166 # This PCD will only take into effect if PcdCpuStackGuard is enabled.\r
167 # @Prompt Specify size of good stack of exception which need switching stack.\r
168 gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize|2048|UINT32|0x30002001\r
169\r
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170 ## Count of pre allocated SMM MP tokens per chunk.\r
171 # @Prompt Specify the count of pre allocated SMM MP tokens per chunk.\r
172 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmMpTokenCountPerChunk|64|UINT32|0x30002002\r
173\r
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174 ## Area of memory where the SEV-ES work area block lives.\r
175 # @Prompt Configure the SEV-ES work area base\r
176 gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase|0x0|UINT32|0x30002005\r
177\r
178 ## Size of teh area of memory where the SEV-ES work area block lives.\r
179 # @Prompt Configure the SEV-ES work area base\r
180 gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaSize|0x0|UINT32|0x30002006\r
181\r
7798fb83 182[PcdsFixedAtBuild, PcdsPatchableInModule]\r
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183 ## This value is the CPU Local APIC base address, which aligns the address on a 4-KByte boundary.\r
184 # @Prompt Configure base address of CPU Local APIC\r
abae030a 185 # @Expression 0x80000001 | (gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress & 0xfff) == 0\r
7798fb83 186 gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress|0xfee00000|UINT32|0x00000001\r
529a5a86 187\r
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188 ## Specifies delay value in microseconds after sending out an INIT IPI.\r
189 # @Prompt Configure delay value after send an INIT IPI\r
cf1eb6e6 190 gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10000|UINT32|0x30000002\r
529a5a86 191\r
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192 ## This value specifies the Application Processor (AP) stack size, used for Mp Service, which must\r
193 ## aligns the address on a 4-KByte boundary.\r
194 # @Prompt Configure stack size for Application Processor (AP)\r
195 gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x8000|UINT32|0x00000003\r
7798fb83 196\r
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197 ## Specifies stack size in the temporary RAM. 0 means half of TemporaryRamSize.\r
198 # @Prompt Stack size in the temporary RAM.\r
199 gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0|UINT32|0x10001003\r
200\r
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201 ## Specifies buffer size in bytes to save SMM profile data. The value should be a multiple of 4KB.\r
202 # @Prompt SMM profile data buffer size.\r
203 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileSize|0x200000|UINT32|0x32132107\r
204\r
205 ## Specifies stack size in bytes for each processor in SMM.\r
206 # @Prompt Processor stack size in SMM.\r
207 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x2000|UINT32|0x32132105\r
208\r
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209 ## Specifies shadow stack size in bytes for each processor in SMM.\r
210 # @Prompt Processor shadow stack size in SMM.\r
211 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmShadowStackSize|0x2000|UINT32|0x3213210E\r
212\r
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213 ## Indicates if SMM Code Access Check is enabled.\r
214 # If enabled, the SMM handler cannot execute the code outside SMM regions.\r
215 # This PCD is suggested to TRUE in production image.<BR><BR>\r
216 # TRUE - SMM Code Access Check will be enabled.<BR>\r
217 # FALSE - SMM Code Access Check will be disabled.<BR>\r
218 # @Prompt SMM Code Access Check.\r
219 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable|TRUE|BOOLEAN|0x60000013\r
220\r
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221 ## Specifies the number of variable MTRRs reserved for OS use. The default number of\r
222 # MTRRs reserved for OS use is 2.\r
223 # @Prompt Number of reserved variable MTRRs.\r
224 gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0x2|UINT32|0x00000015\r
225\r
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226 ## Specifies buffer size in bytes for STM exception stack. The value should be a multiple of 4KB.\r
227 # @Prompt STM exception stack size.\r
228 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStmExceptionStackSize|0x1000|UINT32|0x32132111\r
229\r
230 ## Specifies buffer size in bytes of MSEG. The value should be a multiple of 4KB.\r
231 # @Prompt MSEG size.\r
232 gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize|0x200000|UINT32|0x32132112\r
233\r
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234 ## Specifies the supported CPU features bit in array.\r
235 # @Prompt Supported CPU features.\r
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236 gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSupport|{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}|VOID*|0x00000016\r
237\r
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238 ## Specifies if CPU features will be initialized after SMM relocation.\r
239 # @Prompt If CPU features will be initialized after SMM relocation.\r
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240 gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitAfterSmmRelocation|FALSE|BOOLEAN|0x0000001C\r
241\r
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242 ## Specifies if CPU features will be initialized during S3 resume.\r
243 # @Prompt If CPU features will be initialized during S3 resume.\r
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244 gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitOnS3Resume|FALSE|BOOLEAN|0x0000001D\r
245\r
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246 ## Specifies CPUID Leaf 0x15 Time Stamp Counter and Nominal Core Crystal Clock Frequency.\r
247 # TSC Frequency = ECX (core crystal clock frequency) * EBX/EAX.\r
248 # Intel Xeon Processor Scalable Family with CPUID signature 06_55H = 25000000 (25MHz)\r
249 # 6th and 7th generation Intel Core processors and Intel Xeon W Processor Family = 24000000 (24MHz)\r
250 # Intel Atom processors based on Goldmont Microarchitecture with CPUID signature 06_5CH = 19200000 (19.2MHz)\r
251 # @Prompt This PCD is the nominal frequency of the core crystal clock in Hz as is CPUID Leaf 0x15:ECX\r
252 gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency|24000000|UINT64|0x32132113\r
253\r
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254 ## Specifies the periodic interval value in microseconds for the status check\r
255 # of APs for StartupAllAPs() and StartupThisAP() executed in non-blocking\r
256 # mode in DXE phase.\r
257 # @Prompt Periodic interval value in microseconds for AP status check in DXE.\r
258 gUefiCpuPkgTokenSpaceGuid.PcdCpuApStatusCheckIntervalInMicroSeconds|100000|UINT32|0x0000001E\r
259\r
f79fcf45 260[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]\r
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261 ## Specifies max supported number of Logical Processors.\r
262 # @Prompt Configure max supported number of Logical Processors\r
263 gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|64|UINT32|0x00000002\r
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264 ## Specifies timeout value in microseconds for the BSP to detect all APs for the first time.\r
265 # @Prompt Timeout for the BSP to detect all APs for the first time.\r
266 gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|50000|UINT32|0x00000004\r
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267 ## Specifies the number of Logical Processors that are available in the\r
268 # preboot environment after platform reset, including BSP and APs. Possible\r
269 # values:<BR><BR>\r
270 # zero (default) - PcdCpuBootLogicalProcessorNumber is ignored, and\r
271 # PcdCpuApInitTimeOutInMicroSeconds limits the initial AP\r
272 # detection by the BSP.<BR>\r
273 # nonzero - PcdCpuApInitTimeOutInMicroSeconds is ignored. The initial\r
274 # AP detection finishes only when the detected CPU count\r
275 # (BSP plus APs) reaches the value of\r
276 # PcdCpuBootLogicalProcessorNumber, regardless of how long\r
277 # that takes.<BR>\r
278 # @Prompt Number of Logical Processors available after platform reset.\r
279 gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber|0|UINT32|0x00000008\r
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280 ## Specifies the base address of the first microcode Patch in the microcode Region.\r
281 # @Prompt Microcode Region base address.\r
282 gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x00000005\r
283 ## Specifies the size of the microcode Region.\r
284 # @Prompt Microcode Region size.\r
285 gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x00000006\r
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286 ## Specifies the AP wait loop state during POST phase.\r
287 # The value is defined as below.<BR><BR>\r
288 # 1: Place AP in the Hlt-Loop state.<BR>\r
289 # 2: Place AP in the Mwait-Loop state.<BR>\r
290 # 3: Place AP in the Run-Loop state.<BR>\r
291 # @Prompt The AP wait loop state.\r
292 # @ValidRange 0x80000001 | 1 - 3\r
293 gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|1|UINT8|0x60008006\r
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294 ## Specifies the AP target C-state for Mwait during POST phase.\r
295 # The default value 0 means C1 state.\r
296 # The value is defined as below.<BR><BR>\r
297 # @Prompt The specified AP target C-state for Mwait.\r
298 gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0|UINT8|0x00000007\r
f79fcf45 299\r
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300 ## Specifies timeout value in microseconds for the BSP in SMM to wait for all APs to come into SMM.\r
301 # @Prompt AP synchronization timeout value in SMM.\r
302 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000000|UINT64|0x32132104\r
303\r
304 ## Indicates the CPU synchronization method used when processing an SMI.\r
305 # 0x00 - Traditional CPU synchronization method.<BR>\r
306 # 0x01 - Relaxed CPU synchronization method.<BR>\r
307 # @Prompt SMM CPU Synchronization Method.\r
308 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode|0x00|UINT8|0x60000014\r
309\r
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310 ## Specifies the On-demand clock modulation duty cycle when ACPI feature is enabled.\r
311 # @Prompt The encoded values for target duty cycle modulation.\r
312 # @ValidRange 0x80000001 | 0 - 15\r
313 gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle|0x0|UINT8|0x0000001A\r
314\r
315 ## Indicates if the current boot is a power-on reset.<BR><BR>\r
316 # TRUE - Current boot is a power-on reset.<BR>\r
317 # FALSE - Current boot is not a power-on reset.<BR>\r
318 # @Prompt Current boot is a power-on reset.\r
319 gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset|FALSE|BOOLEAN|0x0000001B\r
320\r
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321[PcdsFixedAtBuild.X64, PcdsPatchableInModule.X64, PcdsDynamic.X64, PcdsDynamicEx.X64]\r
322 ## Indicate access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.\r
323 # MMIO access is always allowed regardless of the value of this PCD.\r
324 # Loose of such restriction is only required by RAS components in X64 platforms.\r
325 # The PCD value is considered as constantly TRUE in IA32 platforms.\r
326 # When the PCD value is TRUE, page table is initialized to cover all memory spaces\r
327 # and the memory occupied by page table is protected by page table itself as read-only.\r
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328 # In X64 build, it cannot be enabled at the same time with SMM profile feature (PcdCpuSmmProfileEnable).\r
329 # In X64 build, it could not be enabled also at the same time with heap guard feature for SMM\r
330 # (PcdHeapGuardPropertyMask in MdeModulePkg).\r
331 # In IA32 build, page table memory is not marked as read-only when either SMM profile feature (PcdCpuSmmProfileEnable)\r
332 # or heap guard feature for SMM (PcdHeapGuardPropertyMask in MdeModulePkg) is enabled.\r
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333 # TRUE - Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.<BR>\r
334 # FALSE - Access to any type of non-SMRAM memory after SmmReadyToLock is allowed.<BR>\r
335 # @Prompt Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.\r
336 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0x3213210F\r
337\r
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338[PcdsDynamic, PcdsDynamicEx]\r
339 ## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.\r
340 # @Prompt The pointer to a CPU S3 data buffer.\r
341 # @ValidList 0x80000001 | 0\r
342 gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0x0|UINT64|0x60000010\r
343\r
344 ## Contains the pointer to a CPU Hot Plug Data structure if CPU hot-plug is supported.\r
345 # @Prompt The pointer to CPU Hot Plug Data.\r
346 # @ValidList 0x80000001 | 0\r
347 gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress|0x0|UINT64|0x60000011\r
348\r
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349 ## Indicates processor feature capabilities, each bit corresponding to a specific feature.\r
350 # @Prompt Processor feature capabilities.\r
351 # @ValidList 0x80000001 | 0\r
352 gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000018\r
353\r
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354 ## As input, specifies user's desired settings for enabling/disabling processor features.\r
355 ## As output, specifies actual settings for processor features, each bit corresponding to a specific feature.\r
356 # @Prompt As input, specifies user's desired processor feature settings. As output, specifies actual processor feature settings.\r
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357 # @ValidList 0x80000001 | 0\r
358 gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000019\r
359\r
234d4c5f 360 ## Contains the size of memory required when CPU processor trace is enabled.<BR><BR>\r
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361 # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>\r
362 # This PCD is ignored if CPU processor trace is disabled.<BR><BR>\r
363 # Default value is 0x00 which means 4KB of memory is allocated if CPU processor trace is enabled.<BR>\r
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364 # 0x0 - 4K.<BR>\r
365 # 0x1 - 8K.<BR>\r
366 # 0x2 - 16K.<BR>\r
367 # 0x3 - 32K.<BR>\r
368 # 0x4 - 64K.<BR>\r
369 # 0x5 - 128K.<BR>\r
370 # 0x6 - 256K.<BR>\r
371 # 0x7 - 512K.<BR>\r
372 # 0x8 - 1M.<BR>\r
373 # 0x9 - 2M.<BR>\r
374 # 0xA - 4M.<BR>\r
375 # 0xB - 8M.<BR>\r
376 # 0xC - 16M.<BR>\r
377 # 0xD - 32M.<BR>\r
378 # 0xE - 64M.<BR>\r
379 # 0xF - 128M.<BR>\r
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380 # @Prompt The memory size used for processor trace if processor trace is enabled.\r
381 # @ValidRange 0x80000001 | 0 - 0xF\r
382 gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize|0x0|UINT32|0x60000012\r
c7399a0c 383\r
234d4c5f 384 ## Contains the processor trace output scheme when CPU processor trace is enabled.<BR><BR>\r
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385 # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>\r
386 # This PCD is ignored if CPU processor trace is disabled.<BR><BR>\r
387 # Default value is 0 which means single range output scheme will be used if CPU processor trace is enabled.<BR>\r
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388 # 0 - Single Range output scheme.<BR>\r
389 # 1 - ToPA(Table of physical address) scheme.<BR>\r
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390 # @Prompt The processor trace output scheme used when processor trace is enabled.\r
391 # @ValidRange 0x80000001 | 0 - 1\r
392 gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme|0x0|UINT8|0x60000015\r
c7399a0c 393\r
c9db7bf1
TL
394 ## This dynamic PCD indicates whether SEV-ES is enabled\r
395 # TRUE - SEV-ES is enabled\r
396 # FALSE - SEV-ES is not enabled\r
397 # @Prompt SEV-ES Status\r
398 gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|FALSE|BOOLEAN|0x60000016\r
399\r
f4e3ce5f
BS
400 ## This dynamic PCD contains the hypervisor features value obtained through the GHCB HYPERVISOR\r
401 # features VMGEXIT defined in the version 2 of GHCB spec.\r
402 # @Prompt GHCB Hypervisor Features\r
403 gUefiCpuPkgTokenSpaceGuid.PcdGhcbHypervisorFeatures|0x0|UINT64|0x60000018\r
404\r
abae030a
LG
405[UserExtensions.TianoCore."ExtraFiles"]\r
406 UefiCpuPkgExtra.uni\r