]> git.proxmox.com Git - mirror_edk2.git/blame - UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c
UefiPayloadPkg: Enhance UEFI payload for coreboot and Slim Bootloader
[mirror_edk2.git] / UefiPayloadPkg / Library / PlatformHookLib / PlatformHookLib.c
CommitLineData
04af8bf2
DG
1/** @file\r
2 Platform Hook Library instance for UART device.\r
3\r
4 Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
5 SPDX-License-Identifier: BSD-2-Clause-Patent\r
6\r
7**/\r
8\r
9#include <Base.h>\r
10#include <Uefi/UefiBaseType.h>\r
11#include <Library/PciLib.h>\r
12#include <Library/PlatformHookLib.h>\r
13#include <Library/BlParseLib.h>\r
14#include <Library/PcdLib.h>\r
15\r
16typedef struct {\r
17 UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries.\r
18 UINT16 DeviceId; ///< Device ID to match the PCI device\r
19 UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz\r
20 UINT64 Offset; ///< The byte offset into to the BAR\r
21 UINT8 BarIndex; ///< Which BAR to get the UART base address\r
22 UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte.\r
23 UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.\r
24 UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.\r
25 UINT8 Reserved[2];\r
26} PCI_SERIAL_PARAMETER;\r
27\r
28/**\r
29 Performs platform specific initialization required for the CPU to access\r
30 the hardware associated with a SerialPortLib instance. This function does\r
31 not initialize the serial port hardware itself. Instead, it initializes\r
32 hardware devices that are required for the CPU to access the serial port\r
33 hardware. This function may be called more than once.\r
34\r
35 @retval RETURN_SUCCESS The platform specific initialization succeeded.\r
36 @retval RETURN_DEVICE_ERROR The platform specific initialization could not be completed.\r
37\r
38**/\r
39RETURN_STATUS\r
40EFIAPI\r
41PlatformHookSerialPortInitialize (\r
42 VOID\r
43 )\r
44{\r
45 RETURN_STATUS Status;\r
46 UINT32 DeviceVendor;\r
47 PCI_SERIAL_PARAMETER *SerialParam;\r
48 SERIAL_PORT_INFO SerialPortInfo;\r
49\r
50 Status = ParseSerialInfo (&SerialPortInfo);\r
51 if (RETURN_ERROR (Status)) {\r
52 return Status;\r
53 }\r
54\r
55 if (SerialPortInfo.Type == PLD_SERIAL_TYPE_MEMORY_MAPPED) {\r
56 Status = PcdSetBoolS (PcdSerialUseMmio, TRUE);\r
57 } else { //IO\r
58 Status = PcdSetBoolS (PcdSerialUseMmio, FALSE);\r
59 }\r
60 if (RETURN_ERROR (Status)) {\r
61 return Status;\r
62 }\r
63 Status = PcdSet64S (PcdSerialRegisterBase, SerialPortInfo.BaseAddr);\r
64 if (RETURN_ERROR (Status)) {\r
65 return Status;\r
66 }\r
67\r
68 Status = PcdSet32S (PcdSerialRegisterStride, SerialPortInfo.RegWidth);\r
69 if (RETURN_ERROR (Status)) {\r
70 return Status;\r
71 }\r
72\r
73 Status = PcdSet32S (PcdSerialBaudRate, SerialPortInfo.Baud);\r
74 if (RETURN_ERROR (Status)) {\r
75 return Status;\r
76 }\r
77\r
78 Status = PcdSet64S (PcdUartDefaultBaudRate, SerialPortInfo.Baud);\r
79 if (RETURN_ERROR (Status)) {\r
80 return Status;\r
81 }\r
82\r
83 Status = PcdSet32S (PcdSerialClockRate, SerialPortInfo.InputHertz);\r
84 if (RETURN_ERROR (Status)) {\r
85 return Status;\r
86 }\r
87\r
88 if (SerialPortInfo.UartPciAddr >= 0x80000000) {\r
89 DeviceVendor = PciRead32 (SerialPortInfo.UartPciAddr & 0x0ffff000);\r
90 SerialParam = PcdGetPtr(PcdPciSerialParameters);\r
91 SerialParam->VendorId = (UINT16)DeviceVendor;\r
92 SerialParam->DeviceId = DeviceVendor >> 16;\r
93 SerialParam->ClockRate = SerialPortInfo.InputHertz;\r
94 SerialParam->RegisterStride = (UINT8)SerialPortInfo.RegWidth;\r
95 }\r
96\r
97 return RETURN_SUCCESS;\r
98}\r