ArmPkg: only attempt buildin MmCommunicationDxe for AArch64
[mirror_edk2.git] / UefiPayloadPkg / SecCore / Ia32 / SecEntry.nasm
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04af8bf2
DG
1;------------------------------------------------------------------------------\r
2;\r
3; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
4; SPDX-License-Identifier: BSD-2-Clause-Patent\r
5;\r
6; Abstract:\r
7;\r
8; Entry point for the coreboot UEFI payload.\r
9;\r
10;------------------------------------------------------------------------------\r
11\r
12SECTION .text\r
13\r
14; C Functions\r
15extern ASM_PFX(SecStartup)\r
16\r
17; Pcds\r
18extern ASM_PFX(PcdGet32 (PcdPayloadFdMemBase))\r
19extern ASM_PFX(PcdGet32 (PcdPayloadStackTop))\r
20\r
21;\r
22; SecCore Entry Point\r
23;\r
24; Processor is in flat protected mode\r
25;\r
26; @param[in] EAX Initial value of the EAX register (BIST: Built-in Self Test)\r
27; @param[in] DI 'BP': boot-strap processor, or 'AP': application processor\r
28; @param[in] EBP Pointer to the start of the Boot Firmware Volume\r
29;\r
30; @return None This routine does not return\r
31;\r
32global ASM_PFX(_ModuleEntryPoint)\r
33ASM_PFX(_ModuleEntryPoint):\r
34 ;\r
35 ; Disable all the interrupts\r
36 ;\r
37 cli\r
38\r
39 ;\r
40 ; Save the Payload HOB base address before switching the stack\r
41 ;\r
42 mov eax, [esp + 4]\r
43\r
44 ;\r
45 ; Construct the temporary memory at 0x80000, length 0x10000\r
46 ;\r
47 mov esp, DWORD [ASM_PFX(PcdGet32 (PcdPayloadStackTop))]\r
48\r
49 ;\r
50 ; Push the Payload HOB base address onto new stack\r
51 ;\r
52 push eax\r
53\r
54 ;\r
55 ; Pass BFV into the PEI Core\r
56 ;\r
57 push DWORD [ASM_PFX(PcdGet32 (PcdPayloadFdMemBase))]\r
58\r
59 ;\r
60 ; Pass stack base into the PEI Core\r
61 ;\r
62 push BASE_512KB\r
63\r
64 ;\r
65 ; Pass stack size into the PEI Core\r
66 ;\r
67 push SIZE_64KB\r
68\r
69 ;\r
70 ; Pass Control into the PEI Core\r
71 ;\r
72 call ASM_PFX(SecStartup)\r
73\r
74 ;\r
75 ; Should never return\r
76 ;\r
77 jmp $\r
78\r