Vlv2DeviceRefCodePkg&Vlv2TbltDevicePkg:Convert Mix to DOS.
[mirror_edk2.git] / Vlv2DeviceRefCodePkg / AcpiTablesPCAT / GloblNvs.asl
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1/**************************************************************************;\r
2;* *;\r
3;* *;\r
4;* Intel Corporation - ACPI Reference Code for the Baytrail *;\r
5;* Family of Customer Reference Boards. *;\r
6;* *;\r
7;* *;\r
52a99493 8;* Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved *;\r
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9;\r
10; This program and the accompanying materials are licensed and made available under\r
11; the terms and conditions of the BSD License that accompanies this distribution.\r
12; The full text of the license may be found at\r
13; http://opensource.org/licenses/bsd-license.php.\r
14;\r
15; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
16; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
17;\r
18;* *;\r
19;* *;\r
20;**************************************************************************/\r
21\r
22\r
23\r
24// Define a Global region of ACPI NVS Region that may be used for any\r
25// type of implementation. The starting offset and size will be fixed\r
26// up by the System BIOS during POST. Note that the Size must be a word\r
27// in size to be fixed up correctly.\r
28\r
29OperationRegion(GNVS,SystemMemory,0xFFFF0000,0xAA55)\r
30Field(GNVS,AnyAcc,Lock,Preserve)\r
31{\r
32 Offset(0), // Miscellaneous Dynamic Registers:\r
33 OSYS, 16, // (00) Operating System\r
34 , 8, // (02)\r
35 , 8, // (03)\r
36 , 8, // (04)\r
37 , 8, // (05)\r
38 , 8, // (06)\r
39 , 8, // (07)\r
40 , 8, // (08)\r
41 , 8, // (09)\r
42 , 8, // (10)\r
43 P80D, 32, // (11) Port 80 Debug Port Value\r
44 LIDS, 8, // (15) Lid State (Lid Open = 1)\r
45 , 8, // (16)\r
46 , 8, // (17)\r
47 Offset(18), // Thermal Policy Registers:\r
48 , 8, // (18)\r
49 , 8, // (19)\r
50 ACTT, 8, // (20) Active Trip Point\r
51 PSVT, 8, // (21) Passive Trip Point\r
52 TC1V, 8, // (22) Passive Trip Point TC1 Value\r
53 TC2V, 8, // (23) Passive Trip Point TC2 Value\r
54 TSPV, 8, // (24) Passive Trip Point TSP Value\r
55 CRTT, 8, // (25) Critical Trip Point\r
56 DTSE, 8, // (26) Digital Thermal Sensor Enable\r
57 DTS1, 8, // (27) Digital Thermal Sensor 1 Reading\r
58 DTS2, 8, // (28) Digital Thermal Sensor 2 Reading\r
59 DTSF, 8, // (29) DTS SMI Function Call\r
60 Offset(30), // Battery Support Registers:\r
61 , 8, // (30)\r
62 , 8, // (31)\r
63 , 8, // (32)\r
64 , 8, // (33)\r
65 , 8, // (34)\r
66 , 8, // (35)\r
67 , 8, // (36)\r
68 Offset(40), // CPU Identification Registers:\r
69 APIC, 8, // (40) APIC Enabled by SBIOS (APIC Enabled = 1)\r
70 MPEN, 8, // (41) Number of Logical Processors if MP Enabled != 0\r
71 , 8, // (42)\r
72 , 8, // (43)\r
73 , 8, // (44)\r
74 , 32, // (45)\r
75 Offset(50), // SIO CMOS Configuration Registers:\r
76 , 8, // (50)\r
77 , 8, // (51)\r
78 , 8, // (52)\r
79 , 8, // (53)\r
80 , 8, // (54)\r
81 , 8, // (55)\r
82 , 8, // (56)\r
83 , 8, // (57)\r
84 , 8, // (58)\r
85 Offset(60), // Internal Graphics Registers:\r
86 , 8, // (60)\r
87 , 8, // (61)\r
88 CADL, 8, // (62) Current Attached Device List\r
89 , 8, // (63)\r
90 CSTE, 16, // (64) Current Display State\r
91 NSTE, 16, // (66) Next Display State\r
92 , 16, // (68)\r
93 NDID, 8, // (70) Number of Valid Device IDs\r
94 DID1, 32, // (71) Device ID 1\r
95 DID2, 32, // (75) Device ID 2\r
96 DID3, 32, // (79) Device ID 3\r
97 DID4, 32, // (83) Device ID 4\r
98 DID5, 32, // (87) Device ID 5\r
99 , 32, // (91)\r
100 , 8, // (95) Fifth byte of AKSV (mannufacturing mode)\r
101 Offset(103), // Backlight Control Registers:\r
102 , 8, // (103)\r
103 BRTL, 8, // (104) Brightness Level Percentage\r
104 Offset(105), // Ambiant Light Sensor Registers:\r
105 , 8, // (105)\r
106 , 8, // (106)\r
107 LLOW, 8, // (107) LUX Low Value\r
108 , 8, // (108)\r
109 Offset(110), // EMA Registers:\r
110 , 8, // (110)\r
111 , 16, // (111)\r
112 , 16, // (113)\r
113 Offset(116), // MEF Registers:\r
114 , 8, // (116) MEF Enable\r
115 Offset(117), // PCIe Dock:\r
116 , 8, // (117)\r
117 Offset(120), // TPM Registers:\r
118 , 8, // (120)\r
119 , 8, // (121)\r
120 , 8, // (122)\r
121 , 8, // (123)\r
122 , 32, // (124)\r
123 , 8, // (125)\r
124 , 8, // (129)\r
125 Offset(130), //\r
126 , 56, // (130)\r
127 , 56, // (137)\r
128 , 8, // (144)\r
129 , 56, // (145)\r
130 Offset(170), // IGD OpRegion/Software SCI base address\r
131 ASLB, 32, // (170) IGD OpRegion base address\r
132 Offset(174), // IGD OpRegion/Software SCI shared data\r
133 IBTT, 8, // (174) IGD Boot Display Device\r
134 IPAT, 8, // (175) IGD Panel Type CMOs option\r
135 ITVF, 8, // (176) IGD TV Format CMOS option\r
136 ITVM, 8, // (177) IGD TV Minor Format CMOS option\r
137 IPSC, 8, // (178) IGD Panel Scaling\r
138 IBLC, 8, // (179) IGD BLC Configuration\r
139 IBIA, 8, // (180) IGD BIA Configuration\r
140 ISSC, 8, // (181) IGD SSC Configuration\r
141 I409, 8, // (182) IGD 0409 Modified Settings Flag\r
142 I509, 8, // (183) IGD 0509 Modified Settings Flag\r
143 I609, 8, // (184) IGD 0609 Modified Settings Flag\r
144 I709, 8, // (185) IGD 0709 Modified Settings Flag\r
145 IDMM, 8, // (186) IGD DVMT Mode\r
146 IDMS, 8, // (187) IGD DVMT Memory Size\r
147 IF1E, 8, // (188) IGD Function 1 Enable\r
148 HVCO, 8, // (189) HPLL VCO\r
149 NXD1, 32, // (190) Next state DID1 for _DGS\r
150 NXD2, 32, // (194) Next state DID2 for _DGS\r
151 NXD3, 32, // (198) Next state DID3 for _DGS\r
152 NXD4, 32, // (202) Next state DID4 for _DGS\r
153 NXD5, 32, // (206) Next state DID5 for _DGS\r
154 NXD6, 32, // (210) Next state DID6 for _DGS\r
155 NXD7, 32, // (214) Next state DID7 for _DGS\r
156 NXD8, 32, // (218) Next state DID8 for _DGS\r
157 GSMI, 8, // (222) GMCH SMI/SCI mode (0=SCI)\r
158 PAVP, 8, // (223) IGD PAVP data\r
159 Offset(225),\r
160 OSCC, 8, // (225) PCIE OSC Control\r
161 NEXP, 8, // (226) Native PCIE Setup Value\r
162 Offset(235), // Global Variables\r
163 DSEN, 8, // (235) _DOS Display Support Flag.\r
164 ECON, 8, // (236) Embedded Controller Availability Flag.\r
165 GPIC, 8, // (237) Global IOAPIC/8259 Interrupt Mode Flag.\r
166 CTYP, 8, // (238) Global Cooling Type Flag.\r
167 L01C, 8, // (239) Global L01 Counter.\r
168 VFN0, 8, // (240) Virtual Fan0 Status.\r
169 VFN1, 8, // (241) Virtual Fan1 Status.\r
170 Offset(256),\r
171 NVGA, 32, // (256) NVIG opregion address\r
172 NVHA, 32, // (260) NVHM opregion address\r
173 AMDA, 32, // (264) AMDA opregion address\r
174 DID6, 32, // (268) Device ID 6\r
175 DID7, 32, // (272) Device ID 7\r
176 DID8, 32, // (276) Device ID 8\r
177 Offset(332),\r
178 USEL, 8, // (332) UART Selection\r
179 PU1E, 8, // (333) PCU UART 1 Enabled\r
180 PU2E, 8, // (334) PCU UART 2 Enabled\r
181\r
182 LPE0, 32, // (335) LPE Bar0\r
183 LPE1, 32, // (339) LPE Bar1\r
184 LPE2, 32, // (343) LPE Bar2\r
185\r
186 Offset(347),\r
187 , 8, // (347)\r
188 , 8, // (348)\r
189 PFLV, 8, // (349) Platform Flavor\r
190\r
191 Offset(351),\r
192 ICNF, 8, // (351) ISCT / AOAC Configuration\r
193 XHCI, 8, // (352) xHCI controller mode\r
194 PMEN, 8, // (353) PMIC enable/disable\r
195\r
196 LPEE, 8, // (354) LPE enable/disable\r
197 ISPA, 32, // (355) ISP Base Addr\r
198 ISPD, 8, // (359) ISP Device Selection 0: Disabled; 1: PCI Device 2; 2: PCI Device 3\r
199\r
200 offset(360), // ((4+8+6)*4+2)*4=296\r
201 //\r
202 // Lpss controllers\r
203 //\r
204 PCIB, 32,\r
205 PCIT, 32,\r
206 D10A, 32, //DMA1\r
207 D10L, 32,\r
208 D11A, 32,\r
209 D11L, 32,\r
210 P10A, 32, // PWM1\r
211 P10L, 32,\r
212 P11A, 32,\r
213 P11L, 32,\r
214 P20A, 32, // PWM2\r
215 P20L, 32,\r
216 P21A, 32,\r
217 P21L, 32,\r
218 U10A, 32, // UART1\r
219 U10L, 32,\r
220 U11A, 32,\r
221 U11L, 32,\r
222 U20A, 32, // UART2\r
223 U20L, 32,\r
224 U21A, 32,\r
225 U21L, 32,\r
226 SP0A, 32, // SPI\r
227 SP0L, 32,\r
228 SP1A, 32,\r
229 SP1L, 32,\r
230\r
231 D20A, 32, //DMA2\r
232 D20L, 32,\r
233 D21A, 32,\r
234 D21L, 32,\r
235 I10A, 32, // I2C1\r
236 I10L, 32,\r
237 I11A, 32,\r
238 I11L, 32,\r
239 I20A, 32, // I2C2\r
240 I20L, 32,\r
241 I21A, 32,\r
242 I21L, 32,\r
243 I30A, 32, // I2C3\r
244 I30L, 32,\r
245 I31A, 32,\r
246 I31L, 32,\r
247 I40A, 32, // I2C4\r
248 I40L, 32,\r
249 I41A, 32,\r
250 I41L, 32,\r
251 I50A, 32, // I2C5\r
252 I50L, 32,\r
253 I51A, 32,\r
254 I51L, 32,\r
255 I60A, 32, // I2C6\r
256 I60L, 32,\r
257 I61A, 32,\r
258 I61L, 32,\r
259 I70A, 32, // I2C7\r
260 I70L, 32,\r
261 I71A, 32,\r
262 I71L, 32,\r
263 //\r
264 // Scc controllers\r
265 //\r
266 eM0A, 32, // EMMC\r
267 eM0L, 32,\r
268 eM1A, 32,\r
269 eM1L, 32,\r
270 SI0A, 32, // SDIO\r
271 SI0L, 32,\r
272 SI1A, 32,\r
273 SI1L, 32,\r
274 SD0A, 32, // SDCard\r
275 SD0L, 32,\r
276 SD1A, 32,\r
277 SD1L, 32,\r
278 MH0A, 32, //\r
279 MH0L, 32,\r
280 MH1A, 32,\r
281 MH1L, 32,\r
282\r
283 offset(656),\r
284 SDRM, 8,\r
285 offset(657),\r
286 HLPS, 8, //(657) Hide Devices\r
287 offset(658),\r
288 OSEL, 8, //(658) OS Seletion - Windows/Android\r
289\r
290 offset(659), // VLV1 DPTF\r
291 SDP1, 8, //(659) An enumerated value corresponding to SKU\r
292 DPTE, 8, //(660) DPTF Enable\r
293 THM0, 8, //(661) System Thermal 0\r
294 THM1, 8, //(662) System Thermal 1\r
295 THM2, 8, //(663) System Thermal 2\r
296 THM3, 8, //(664) System Thermal 3\r
297 THM4, 8, //(665) System Thermal 3\r
298 CHGR, 8, //(666) DPTF Changer Device\r
299 DDSP, 8, //(667) DPTF Display Device\r
300 DSOC, 8, //(668) DPTF SoC device\r
301 DPSR, 8, //(669) DPTF Processor device\r
302 DPCT, 32, //(670) DPTF Processor participant critical temperature\r
303 DPPT, 32, //(674) DPTF Processor participant passive temperature\r
304 DGC0, 32, //(678) DPTF Generic sensor0 participant critical temperature\r
305 DGP0, 32, //(682) DPTF Generic sensor0 participant passive temperature\r
306 DGC1, 32, //(686) DPTF Generic sensor1 participant critical temperature\r
307 DGP1, 32, //(690) DPTF Generic sensor1 participant passive temperature\r
308 DGC2, 32, //(694) DPTF Generic sensor2 participant critical temperature\r
309 DGP2, 32, //(698) DPTF Generic sensor2 participant passive temperature\r
310 DGC3, 32, //(702) DPTF Generic sensor3 participant critical temperature\r
311 DGP3, 32, //(706) DPTF Generic sensor3 participant passive temperature\r
312 DGC4, 32, //(710)DPTF Generic sensor3 participant critical temperature\r
313 DGP4, 32, //(714)DPTF Generic sensor3 participant passive temperature\r
314 DLPM, 8, //(718) DPTF Current low power mode setting\r
315 DSC0, 32, //(719) DPTF Critical threshold0 for SCU\r
316 DSC1, 32, //(723) DPTF Critical threshold1 for SCU\r
317 DSC2, 32, //(727) DPTF Critical threshold2 for SCU\r
318 DSC3, 32, //(731) DPTF Critical threshold3 for SCU\r
319 DSC4, 32, //(735) DPTF Critical threshold3 for SCU\r
320 DDBG, 8, //(739) DPTF Super Debug option. 0 - Disabled, 1 - Enabled\r
321 LPOE, 32, //(740) DPTF LPO Enable\r
322 LPPS, 32, //(744) P-State start index\r
323 LPST, 32, //(748) Step size\r
324 LPPC, 32, //(752) Power control setting\r
325 LPPF, 32, //(756) Performance control setting\r
326 DPME, 8, //(760) DPTF DPPM enable/disable\r
327 BCSL, 8, //(761) Battery charging solution 0-CLV 1-ULPMC\r
328 NFCS, 8, //(762) NFCx Select 1: NFC1 2:NFC2\r
329 PCIM, 8, //(763) EMMC device 0-ACPI mode, 1-PCI mode\r
330 TPMA, 32, //(764)\r
331 TPML, 32, //(768)\r
332 ITSA, 8, //(772) I2C Touch Screen Address\r
333 S0IX, 8, //(773) S0ix status\r
334 SDMD, 8, //(774) SDIO Mode\r
335 EMVR, 8, //(775) eMMC controller version\r
336 BMBD, 32, //(776) BM Bound\r
337 FSAS, 8, //(780) FSA Status\r
338 BDID, 8, //(781) Board ID\r
339 FBID, 8, //(782) FAB ID\r
340 OTGM, 8, //(783) OTG mode\r
341 STEP, 8, //(784) Stepping ID\r
342 WITT, 8, //(785) Enable Test Device connected to I2C for WHCK test.\r
343 SOCS, 8, //(786) provide the SoC stepping infomation\r
344 AMTE, 8, //(787) Ambient Trip point change\r
345 UTS, 8, //(788) Enable Test Device connected to URT for WHCK test.\r
346 SCPE, 8, //(789) Allow higher performance on AC/USB - Enable/Disable\r
347 Offset(792),\r
348 EDPV, 8, //(792) Check for eDP display device\r
349 DIDX, 32, //(793) Device ID for eDP device\r
52a99493 350 IOT, 8, //(794) MinnowBoard Max JP1 is configured for MSFT IOT project.\r
a0f3b028 351 BATT, 8, //(795) The Flag of RTC Battery Prensent.\r
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352}\r
353\r