Vlv2DeviceRefCodePkg&Vlv2TbltDevicePkg:Add setup option of LPE Audio.
[mirror_edk2.git] / Vlv2DeviceRefCodePkg / AcpiTablesPCAT / Pch.asl
CommitLineData
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1/**************************************************************************;\r
2;* *;\r
3;* *;\r
4;* Intel Corporation - ACPI Reference Code for the Baytrail *;\r
5;* Family of Customer Reference Boards. *;\r
6;* *;\r
7;* *;\r
aa44e98d 8;* Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved *;\r
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9;\r
10; This program and the accompanying materials are licensed and made available under\r
11; the terms and conditions of the BSD License that accompanies this distribution.\r
12; The full text of the license may be found at\r
13; http://opensource.org/licenses/bsd-license.php.\r
14;\r
15; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
16; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
17;\r
18;* *;\r
19;* *;\r
20;**************************************************************************/\r
21\r
22\r
23Scope(\)\r
24{\r
25 //\r
26 // Define VLV ABASE I/O as an ACPI operating region. The base address\r
27 // can be found in Device 31, Registers 40-43h.\r
28 //\r
29 OperationRegion(PMIO, SystemIo, \PMBS, 0x46)\r
30 Field(PMIO, ByteAcc, NoLock, Preserve)\r
31 {\r
32 , 8,\r
33 PWBS, 1, // Power Button Status\r
34 Offset(0x20),\r
35 , 13,\r
36 PMEB, 1, // PME_B0_STS\r
37 Offset(0x42), // General Purpose Control\r
38 , 1,\r
39 GPEC, 1\r
40 }\r
41 Field(PMIO, ByteAcc, NoLock, WriteAsZeros)\r
42 {\r
43 Offset(0x20), // GPE0 Status\r
44 , 4,\r
45 PSCI, 1, // PUNIT SCI Status\r
46 SCIS, 1 // GUNIT SCI Status\r
47 }\r
48\r
49\r
50\r
51 //\r
52 // Define a Memory Region that will allow access to the PMC\r
53 // Register Block. Note that in the Intel Reference Solution, the PMC\r
54 // will get fixed up dynamically during POST.\r
55 //\r
56 OperationRegion(PMCR, SystemMemory, \PFDR, 0x04)// PMC Function Disable Register\r
57 Field(PMCR,DWordAcc,Lock,Preserve)\r
58 {\r
59 Offset(0x00), // Function Disable Register\r
60 L10D, 1, // (0) LPIO1 DMA Disable\r
61 L11D, 1, // (1) LPIO1 PWM #1 Disable\r
62 L12D, 1, // (2) LPIO1 PWM #2 Disable\r
63 L13D, 1, // (3) LPIO1 HS-UART #1 Disable\r
64 L14D, 1, // (4) LPIO1 HS-UART #2 Disable\r
65 L15D, 1, // (5) LPIO1 SPI Disable\r
66 , 2, // (6:7) Reserved\r
67 SD1D, 1, // (8) SCC SDIO #1 Disable\r
68 SD2D, 1, // (9) SCC SDIO #2 Disable\r
69 SD3D, 1, // (10) SCC SDIO #3 Disable\r
70 HSID, 1, // (11)\r
71 HDAD, 1, // (12) Azalia Disable\r
72 LPED, 1, // (13) LPE Disable\r
73 OTGD, 1, // (14) USB OTG Disable\r
74 , 1, // (15) USH Disable\r
75 , 1, // (16)\r
76 , 1, // (17)\r
77 , 1, // (18) USB Disable\r
78 , 1, // (19) SEC Disable\r
79 RP1D, 1, // (20) Root Port 0 Disable\r
80 RP2D, 1, // (21) Root Port 1 Disable\r
81 RP3D, 1, // (22) Root Port 2 Disable\r
82 RP4D, 1, // (23) Root Port 3 Disable\r
83 L20D, 1, // (24) LPIO2 DMA Disable\r
84 L21D, 1, // (25) LPIO2 I2C #1 Disable\r
85 L22D, 1, // (26) LPIO2 I2C #2 Disable\r
86 L23D, 1, // (27) LPIO2 I2C #3 Disable\r
87 L24D, 1, // (28) LPIO2 I2C #4 Disable\r
88 L25D, 1, // (29) LPIO2 I2C #5 Disable\r
89 L26D, 1, // (30) LPIO2 I2C #6 Disable\r
90 L27D, 1 // (31) LPIO2 I2C #7 Disable\r
91 }\r
92\r
93\r
94 OperationRegion(CLKC, SystemMemory, \PCLK, 0x18)// PMC CLK CTL Registers\r
95 Field(CLKC,DWordAcc,Lock,Preserve)\r
96 {\r
97 Offset(0x00), // PLT_CLK_CTL_0\r
98 CKC0, 2,\r
99 CKF0, 1,\r
100 , 29,\r
101 Offset(0x04), // PLT_CLK_CTL_1\r
102 CKC1, 2,\r
103 CKF1, 1,\r
104 , 29,\r
105 Offset(0x08), // PLT_CLK_CTL_2\r
106 CKC2, 2,\r
107 CKF2, 1,\r
108 , 29,\r
109 Offset(0x0C), // PLT_CLK_CTL_3\r
110 CKC3, 2,\r
111 CKF3, 1,\r
112 , 29,\r
113 Offset(0x10), // PLT_CLK_CTL_4\r
114 CKC4, 2,\r
115 CKF4, 1,\r
116 , 29,\r
117 Offset(0x14), // PLT_CLK_CTL_5\r
118 CKC5, 2,\r
119 CKF5, 1,\r
120 , 29,\r
121 }\r
122} //end Scope(\)\r
123\r
124scope (\_SB)\r
125{\r
126 Device(LPEA)\r
127 {\r
128 Name (_ADR, 0)\r
129 Name (_HID, "80860F28")\r
130 Name (_CID, "80860F28")\r
131 //Name (_CLS, Package (3) {0x04, 0x01, 0x00})\r
132 Name (_DDN, "Intel(R) Low Power Audio Controller - 80860F28")\r
133 Name (_SUB, "80867270")\r
134 Name (_UID, 1)\r
135 Name (_DEP, Package() {\_SB.I2C2.RTEK})\r
136 Name(_PR0,Package() {PLPE})\r
137\r
138 Method (_STA, 0x0, NotSerialized)\r
139 {\r
140 If (LAnd(LAnd(LEqual(LPEE, 2), LEqual(LPED, 0)), LEqual(OSEL, 0)))\r
141 {\r
aa44e98d 142 If(LEqual(LPAD, 1))\r
143 {\r
144 Return (0xF)\r
145 }\r
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146 }\r
147 Return (0x0)\r
148 }\r
149\r
150 Method (_DIS, 0x0, NotSerialized)\r
151 {\r
152 //Add a dummy disable function\r
153 }\r
154\r
155 Name (RBUF, ResourceTemplate ()\r
156 {\r
157 Memory32Fixed (ReadWrite, 0xFE400000, 0x00200000, BAR0) // MMIO 1 - LPE MMIO\r
158 Memory32Fixed (ReadWrite, 0xFE830000, 0x00001000, BAR1) // MMIO 2 - Shadowed PCI Config Space\r
159 Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00100000, BAR2) // LPE Memory Bar Allocate during post\r
160 Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {24}\r
161 Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {25}\r
162 Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {26}\r
163 Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {27}\r
164 Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {28}\r
165 Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {29}\r
166 GpioInt(Edge, ActiveBoth, ExclusiveAndWake, PullNone, 0,"\\_SB.GPO2") {28} // Audio jack interrupt\r
167 }\r
168 )\r
169\r
170 Method (_CRS, 0x0, NotSerialized)\r
171 {\r
172 CreateDwordField(^RBUF, ^BAR0._BAS, B0BA)\r
173 Store(LPE0, B0BA)\r
174 CreateDwordField(^RBUF, ^BAR1._BAS, B1BA)\r
175 Store(LPE1, B1BA)\r
176 CreateDwordField(^RBUF, ^BAR2._BAS, B2BA)\r
177 Store(LPE2, B2BA)\r
178 Return (RBUF)\r
179 }\r
180\r
181 OperationRegion (KEYS, SystemMemory, LPE1, 0x100)\r
182 Field (KEYS, DWordAcc, NoLock, WriteAsZeros)\r
183 {\r
184 Offset (0x84),\r
185 PSAT, 32\r
186 }\r
187\r
188 PowerResource(PLPE, 0, 0) // Power Resource for LPEA\r
189 {\r
190 Method (_STA)\r
191 {\r
192 Return (1) // Power Resource is always available.\r
193 }\r
194\r
195 Method (_ON)\r
196 {\r
197 And(PSAT, 0xfffffffC, PSAT)\r
198 OR(PSAT, 0X00000000, PSAT)\r
199 }\r
200\r
201 Method (_OFF)\r
202 {\r
203 OR(PSAT, 0x00000003, PSAT)\r
204 OR(PSAT, 0X00000000, PSAT)\r
205 }\r
206 } // End PLPE\r
207 } // End "Low Power Engine Audio"\r
208\r
209 Device(LPA2)\r
210 {\r
211 Name (_ADR, 0)\r
212 Name (_HID, "LPE0F28") // _HID: Hardware ID\r
213 Name (_CID, "LPE0F28") // _CID: Compatible ID\r
214 Name (_DDN, "Intel(R) SST Audio - LPE0F28") // _DDN: DOS Device Name\r
215 Name (_SUB, "80867270")\r
216 Name (_UID, 1)\r
217 Name (_DEP, Package() {\_SB.I2C2.RTEK})\r
218 Name(_PR0,Package() {PLPE})\r
219\r
220 Method (_STA, 0x0, NotSerialized)\r
221 {\r
222 If (LAnd(LAnd(LEqual(LPEE, 2), LEqual(LPED, 0)), LEqual(OSEL, 1)))\r
223 {\r
aa44e98d 224 If(LEqual(LPAD, 1))\r
225 {\r
226 Return (0xF)\r
227 }\r
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228 }\r
229 Return (0x0)\r
230 }\r
231\r
232 Method (_DIS, 0x0, NotSerialized)\r
233 {\r
234 //Add a dummy disable function\r
235 }\r
236\r
237 Name (RBUF, ResourceTemplate ()\r
238 {\r
239 Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00100000, BAR2) // LPE Memory Bar Allocate during post\r
240 Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00000100, SHIM)\r
241 Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00001000, MBOX)\r
242 Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00014000, IRAM)\r
243 Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00028000, DRAM)\r
244 Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {29}\r
245 Memory32Fixed (ReadWrite, 0xFE830000, 0x00001000, BAR1) // MMIO 2 - Shadowed PCI Config Space\r
246 }\r
247 )\r
248\r
249 Method (_CRS, 0x0, NotSerialized)\r
250 {\r
251 CreateDwordField(^RBUF, ^SHIM._BAS, SHBA)\r
252 Add(LPE0, 0x140000, SHBA)\r
253 CreateDwordField(^RBUF, ^MBOX._BAS, MBBA)\r
254 Add(LPE0, 0x144000, MBBA)\r
255 CreateDwordField(^RBUF, ^IRAM._BAS, IRBA)\r
256 Add(LPE0, 0xC0000, IRBA)\r
257 CreateDwordField(^RBUF, ^DRAM._BAS, DRBA)\r
258 Add(LPE0, 0x100000, DRBA)\r
259 CreateDwordField(^RBUF, ^BAR1._BAS, B1BA)\r
260 Store(LPE1, B1BA)\r
261 CreateDwordField(^RBUF, ^BAR2._BAS, B2BA)\r
262 Store(LPE2, B2BA)\r
263 Return (RBUF)\r
264 }\r
265\r
266 OperationRegion (KEYS, SystemMemory, LPE1, 0x100)\r
267 Field (KEYS, DWordAcc, NoLock, WriteAsZeros)\r
268 {\r
269 Offset (0x84),\r
270 PSAT, 32\r
271 }\r
272\r
273 PowerResource(PLPE, 0, 0) // Power Resource for LPEA\r
274 {\r
275 Method (_STA)\r
276 {\r
277 Return (1) // Power Resource is always available.\r
278 }\r
279\r
280 Method (_ON)\r
281 {\r
282 And(PSAT, 0xfffffffC, PSAT)\r
283 OR(PSAT, 0X00000000, PSAT)\r
284 }\r
285\r
286 Method (_OFF)\r
287 {\r
288 OR(PSAT, 0x00000003, PSAT)\r
289 OR(PSAT, 0X00000000, PSAT)\r
290 }\r
291 } // End PLPE\r
292\r
293 Device (ADMA)\r
294 {\r
295 Name (_ADR, Zero) // _ADR: Address\r
296 Name (_HID, "DMA0F28") // _HID: Hardware ID\r
297 Name (_CID, "DMA0F28") // _CID: Compatible ID\r
298 Name (_DDN, "Intel(R) Audio DMA0 - DMA0F28") // _DDN: DOS Device Name\r
299 Name (_UID, One) // _UID: Unique ID\r
300 Name (RBUF, ResourceTemplate ()\r
301 {\r
302 Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00001000, DMA0) // LPE BASE + LPE DMA0 offset\r
303 Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00001000, SHIM) // LPE BASE + LPE SHIM offset\r
304 Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {24}\r
305 })\r
306\r
307 Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings\r
308 {\r
309 CreateDwordField(^RBUF, ^DMA0._BAS, D0BA)\r
310 Add(LPE0, 0x98000, D0BA)\r
311 CreateDwordField(^RBUF, ^SHIM._BAS, SHBA)\r
312 Add(LPE0, 0x140000, SHBA)\r
313 Return (RBUF)\r
314 }\r
315 }\r
316 } // End "Low Power Engine Audio" for Android\r
317}\r
318\r
319scope (\_SB.PCI0)\r
320{\r
321\r
322 //\r
323 // Serial ATA Host Controller - Device 19, Function 0\r
324 //\r
325\r
326 Device(SATA)\r
327 {\r
328 Name(_ADR,0x00130000)\r
329 //\r
330 // SATA Methods pulled in via SSDT.\r
331 //\r
332\r
333 OperationRegion(SATR, PCI_Config, 0x74,0x4)\r
334 Field(SATR,WordAcc,NoLock,Preserve)\r
335 {\r
336 Offset(0x00), // 0x74, PMCR\r
337 , 8,\r
338 PMEE, 1, //PME_EN\r
339 , 6,\r
340 PMES, 1 //PME_STS\r
341 }\r
342\r
343 Method (_STA, 0x0, NotSerialized)\r
344 {\r
345 Return(0xf)\r
346 }\r
347\r
348 Method(_DSW, 3)\r
349 {\r
350 } // End _DSW\r
351 }\r
352\r
353 //\r
354 // For eMMC 4.41 PCI mode in order to present non-removable device under Windows environment\r
355 //\r
356 Device(EM41)\r
357 {\r
358 Name(_ADR,0x00100000)\r
359 OperationRegion(SDIO, PCI_Config, 0x84,0x4)\r
360 Field(SDIO,WordAcc,NoLock,Preserve)\r
361 {\r
362 Offset(0x00), // 0x84, PMCR\r
363 , 8,\r
364 PMEE, 1, //PME_EN\r
365 , 6,\r
366 PMES, 1 //PME_STS\r
367 }\r
368\r
369 Method (_STA, 0x0, NotSerialized)\r
370 {\r
371 If (LAnd(LEqual(PCIM, 1), LEqual(SD1D, 0)))\r
372 {\r
373 Return(0xF)\r
374 }\r
375 Else\r
376 {\r
377 Return(0x0)\r
378 }\r
379 }\r
380\r
381 Method(_DSW, 3)\r
382 {\r
383 } // End _DSW\r
384\r
385 Device (CARD)\r
386 {\r
387 Name (_ADR, 0x00000008)\r
388 Method(_RMV, 0x0, NotSerialized)\r
389 {\r
390 Return (0)\r
391 } // End _DSW\r
392 }\r
393 }\r
394\r
395 //\r
396 // For eMMC 4.5 PCI mode in order to present non-removable device under Windows environment\r
397 //\r
398 Device(EM45)\r
399 {\r
400 Name(_ADR,0x00170000)\r
401 OperationRegion(SDIO, PCI_Config, 0x84,0x4)\r
402 Field(SDIO,WordAcc,NoLock,Preserve)\r
403 {\r
404 Offset(0x00), // 0x84, PMCR\r
405 , 8,\r
406 PMEE, 1, //PME_EN\r
407 , 6,\r
408 PMES, 1 //PME_STS\r
409 }\r
410\r
411 Method (_STA, 0x0, NotSerialized)\r
412 {\r
413 If (LAnd(LEqual(PCIM, 1), LEqual(HSID, 0)))\r
414 {\r
415 Return(0xF)\r
416 }\r
417 Else\r
418 {\r
419 Return(0x0)\r
420 }\r
421 }\r
422\r
423 Method(_DSW, 3)\r
424 {\r
425 } // End _DSW\r
426\r
427 Device (CARD)\r
428 {\r
429 Name (_ADR, 0x00000008)\r
430 Method(_RMV, 0x0, NotSerialized)\r
431 {\r
432 Return (0)\r
433 } // End _DSW\r
434 }\r
435 }\r
436 //\r
437 // For SD Host Controller (Bus 0x00 : Dev 0x12 : Func 0x00) PCI mode in order to present non-removable device under Windows environment\r
438 //\r
439 Device(SD12)\r
440 {\r
441 Name(_ADR,0x00120000)\r
442\r
443 Method (_STA, 0x0, NotSerialized)\r
444 {\r
445 //\r
446 // PCIM>> 0:ACPI mode 1:PCI mode\r
447 //\r
448 If (LEqual(PCIM, 0)) {\r
449 Return (0x0)\r
450 }\r
451\r
452 //\r
453 // If device is disabled.\r
454 //\r
455 If (LEqual(SD3D, 1))\r
456 {\r
457 Return (0x0)\r
458 }\r
459\r
460 Return (0xF)\r
461 }\r
462\r
463 Device (CARD)\r
464 {\r
465 Name (_ADR, 0x00000008)\r
466 Method(_RMV, 0x0, NotSerialized)\r
467 {\r
468 // SDRM = 0 non-removable;\r
469 If (LEqual(SDRM, 0))\r
470 {\r
471 Return (0)\r
472 }\r
473\r
474 Return (1)\r
475 }\r
476 }\r
477 }\r
478\r
479 // xHCI Controller - Device 20, Function 0\r
480 include("PchXhci.asl")\r
481\r
482 //\r
483 // High Definition Audio Controller - Device 27, Function 0\r
484 //\r
485 Device(HDEF)\r
486 {\r
487 Name(_ADR, 0x001B0000)\r
488 include("PchAudio.asl")\r
489\r
490 Method (_STA, 0x0, NotSerialized)\r
491 {\r
492 If (LEqual(HDAD, 0))\r
493 {\r
494 Return(0xf)\r
495 }\r
496 Return(0x0)\r
497 }\r
498\r
499 Method(_DSW, 3)\r
500 {\r
501 } // End _DSW\r
502 } // end "High Definition Audio Controller"\r
503\r
504\r
505\r
506 //\r
507 // PCIE Root Port #1\r
508 //\r
509 Device(RP01)\r
510 {\r
511 Name(_ADR, 0x001C0000)\r
512 include("PchPcie.asl")\r
513 Name(_PRW, Package() {9, 4})\r
514\r
515 Method(_PRT,0)\r
516 {\r
517 If(PICM) { Return(AR04) }// APIC mode\r
518 Return (PR04) // PIC Mode\r
519 } // end _PRT\r
520 } // end "PCIE Root Port #1"\r
521\r
522 //\r
523 // PCIE Root Port #2\r
524 //\r
525 Device(RP02)\r
526 {\r
527 Name(_ADR, 0x001C0001)\r
528 include("PchPcie.asl")\r
529 Name(_PRW, Package() {9, 4})\r
530\r
531 Method(_PRT,0)\r
532 {\r
533 If(PICM) { Return(AR05) }// APIC mode\r
534 Return (PR05) // PIC Mode\r
535 } // end _PRT\r
536\r
537 } // end "PCIE Root Port #2"\r
538\r
539 //\r
540 // PCIE Root Port #3\r
541 //\r
542 Device(RP03)\r
543 {\r
544 Name(_ADR, 0x001C0002)\r
545 include("PchPcie.asl")\r
546 Name(_PRW, Package() {9, 4})\r
547 Method(_PRT,0)\r
548 {\r
549 If(PICM) { Return(AR06) }// APIC mode\r
550 Return (PR06) // PIC Mode\r
551 } // end _PRT\r
552\r
553 } // end "PCIE Root Port #3"\r
554\r
555 //\r
556 // PCIE Root Port #4\r
557 //\r
558 Device(RP04)\r
559 {\r
560 Name(_ADR, 0x001C0003)\r
561 include("PchPcie.asl")\r
562 Name(_PRW, Package() {9, 4})\r
563 Method(_PRT,0)\r
564 {\r
565 If(PICM) { Return(AR07) }// APIC mode\r
566 Return (PR07) // PIC Mode\r
567 } // end _PRT\r
568\r
569 } // end "PCIE Root Port #4"\r
570\r
571\r
572 Scope(\_SB)\r
573 {\r
574 //\r
575 // Dummy power resource for USB D3 cold support\r
576 //\r
577 PowerResource(USBC, 0, 0)\r
578 {\r
579 Method(_STA) { Return (0xF) }\r
580 Method(_ON) {}\r
581 Method(_OFF) {}\r
582 }\r
583 }\r
584 //\r
585 // EHCI Controller - Device 29, Function 0\r
586 //\r
587 Device(EHC1)\r
588 {\r
589 Name(_ADR, 0x001D0000)\r
590 Name(_DEP, Package(0x1)\r
591 {\r
592 PEPD\r
593 })\r
594 include("PchEhci.asl")\r
595 Name(_PRW, Package() {0x0D, 4})\r
596\r
597 OperationRegion(USBR, PCI_Config, 0x54,0x4)\r
598 Field(USBR,WordAcc,NoLock,Preserve)\r
599 {\r
600 Offset(0x00), // 0x54, PMCR\r
601 , 8,\r
602 PMEE, 1, //PME_EN\r
603 , 6,\r
604 PMES, 1 //PME_STS\r
605 }\r
606\r
607 Method (_STA, 0x0, NotSerialized)\r
608 {\r
609 If(LEqual(XHCI, 0)) //XHCI is not present. It means EHCI is there\r
610 {\r
611 Return (0xF)\r
612 } Else\r
613 {\r
614 Return (0x0)\r
615 }\r
616 }\r
617\r
618 Method (_RMV, 0, NotSerialized)\r
619 {\r
620 Return (0x0)\r
621 }\r
622 //\r
623 // Create a dummy PR3 method to indicate to the PCI driver\r
624 // that the device is capable of D3 cold\r
625 //\r
626 Method(_PR3, 0x0, NotSerialized)\r
627 {\r
628 return (Package() {\_SB.USBC})\r
629 }\r
630\r
631 } // end "EHCI Controller"\r
632\r
633 //\r
634 // SMBus Controller - Device 31, Function 3\r
635 //\r
636 Device(SBUS)\r
637 {\r
638 Name(_ADR,0x001F0003)\r
639 Include("PchSmb.asl")\r
640 }\r
641\r
642 Device(SEC0)\r
643 {\r
644 Name (_ADR, 0x001a0000) // Device 0x1a, Function 0\r
645 Name(_DEP, Package(0x1)\r
646 {\r
647 PEPD\r
648 })\r
649\r
650\r
651 OperationRegion (PMEB, PCI_Config, 0x84, 0x04) //PMECTRLSTATUS\r
652 Field (PMEB, WordAcc, NoLock, Preserve)\r
653 {\r
654 , 8,\r
655 PMEE, 1, //bit8 PMEENABLE\r
656 , 6,\r
657 PMES, 1 //bit15 PMESTATUS\r
658 }\r
659\r
660 // Arg0 -- integer that contains the device wake capability control (0-disable 1- enable)\r
661 // Arg1 -- integer that contains target system state (0-4)\r
662 // Arg2 -- integer that contains the target device state\r
663 Method (_DSW, 3, NotSerialized) // _DSW: Device Sleep Wake\r
664 {\r
665 }\r
666\r
667 Method (_CRS, 0, NotSerialized)\r
668 {\r
669 Name (RBUF, ResourceTemplate ()\r
670 {\r
671 Memory32Fixed (ReadWrite, 0x1e000000, 0x2000000)\r
672 })\r
673\r
674 If (LEqual(PAVP, 2))\r
675 {\r
676 Return (RBUF)\r
677 }\r
678 Return (ResourceTemplate() {})\r
679 }\r
680\r
681 Method (_STA)\r
682 {\r
683 If (LNotEqual(PAVP, 0))\r
684 {\r
685 Return (0xF)\r
686 }\r
687 Return (0x0)\r
688 }\r
689 } // Device(SEC0)\r
690\r
691} // End scope (\_SB.PCI0)\r
a0f3b028 692\r