projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3cbfba02 DW |
1 | /**************************************************************************;\r |
| 2 | ;* *;\r | |
| 3 | ;* *;\r | |
| 4 | ;* Intel Corporation - ACPI Reference Code for the Baytrail *;\r | |
| 5 | ;* Family of Customer Reference Boards. *;\r | |
| 6 | ;* *;\r | |
| 7 | ;* *;\r | |
| 8 | ;* Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved *;\r | |
| 9 | ;\r | |
| 10 | ; This program and the accompanying materials are licensed and made available under\r | |
| 11 | ; the terms and conditions of the BSD License that accompanies this distribution.\r | |
| 12 | ; The full text of the license may be found at\r | |
| 13 | ; http://opensource.org/licenses/bsd-license.php.\r | |
| 14 | ;\r | |
| 15 | ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 16 | ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 17 | ;\r | |
| 18 | ;* *;\r | |
| 19 | ;* *;\r | |
| 20 | ;**************************************************************************/\r | |
| 21 | \r | |
| 22 | \r | |
| 23 | // Define various SMBus PCI Configuration Space Registers.\r | |
| 24 | \r | |
| 25 | OperationRegion(SMBP,PCI_Config,0x40,0xC0)\r | |
| 26 | Field(SMBP,DWordAcc,NoLock,Preserve)\r | |
| 27 | {\r | |
| 28 | , 2,\r | |
| 29 | I2CE, 1\r | |
| 30 | }\r | |
| 31 | \r | |
| 32 | // SMBus Send Byte - This function will write a single byte of\r | |
| 33 | // data to a specific Slave Device per SMBus Send Byte Protocol.\r | |
| 34 | // Arg0 = Address\r | |
| 35 | // Arg1 = Data\r | |
| 36 | // Return: Success = 1\r | |
| 37 | // Failure = 0\r | |
| 38 | \r | |
| 39 | Method(SSXB,2,Serialized)\r | |
| 40 | {\r | |
| 41 | OperationRegion(SMPB,PCI_Config,0x20,4)\r | |
| 42 | Field(SMPB,DWordAcc,NoLock,Preserve)\r | |
| 43 | {\r | |
| 44 | , 5,\r | |
| 45 | SBAR, 11\r | |
| 46 | }\r | |
| 47 | \r | |
| 48 | // Define various SMBus IO Mapped Registers.\r | |
| 49 | \r | |
| 50 | OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r | |
| 51 | Field(SMBI,ByteAcc,NoLock,Preserve)\r | |
| 52 | {\r | |
| 53 | HSTS, 8, // 0 - Host Status Register\r | |
| 54 | Offset(0x02),\r | |
| 55 | HCON, 8, // 2 - Host Control\r | |
| 56 | HCOM, 8, // 3 - Host Command\r | |
| 57 | TXSA, 8, // 4 - Transmit Slave Address\r | |
| 58 | DAT0, 8, // 5 - Host Data 0\r | |
| 59 | DAT1, 8, // 6 - Host Data 1\r | |
| 60 | HBDR, 8, // 7 - Host Block Data\r | |
| 61 | PECR, 8, // 8 - Packer Error Check\r | |
| 62 | RXSA, 8, // 9 - Receive Slave Address\r | |
| 63 | SDAT, 16, // A - Slave Data\r | |
| 64 | }\r | |
| 65 | \r | |
| 66 | // Step 1: Confirm the ICHx SMBus is ready to perform\r | |
| 67 | // communication.\r | |
| 68 | \r | |
| 69 | If(STRT())\r | |
| 70 | {\r | |
| 71 | Return(0)\r | |
| 72 | }\r | |
| 73 | \r | |
| 74 | // Step 2: Initiate a Send Byte.\r | |
| 75 | \r | |
| 76 | Store(0,I2CE) // Ensure SMbus Mode.\r | |
| 77 | Store(0xBF,HSTS) // Clear all but INUSE_STS.\r | |
| 78 | Store(Arg0,TXSA) // Write Address in TXSA.\r | |
| 79 | Store(Arg1,HCOM) // Data in HCOM.\r | |
| 80 | \r | |
| 81 | // Set the SMBus Host control register to 0x48.\r | |
| 82 | // Bit 7: = 0 = reserved\r | |
| 83 | // Bit 6: = 1 = start\r | |
| 84 | // Bit 5: = 0 = disregard, I2C related bit\r | |
| 85 | // Bits 4:2: = 001 = Byte Protocol\r | |
| 86 | // Bit 1: = 0 = Normal Function\r | |
| 87 | // Bit 0: = 0 = Disable interrupt generation\r | |
| 88 | \r | |
| 89 | Store(0x48,HCON)\r | |
| 90 | \r | |
| 91 | // Step 3: Exit the Method correctly.\r | |
| 92 | \r | |
| 93 | If(COMP)\r | |
| 94 | {\r | |
| 95 | Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others..\r | |
| 96 | Return(1) // Return Success.\r | |
| 97 | }\r | |
| 98 | \r | |
| 99 | Return(0)\r | |
| 100 | }\r | |
| 101 | \r | |
| 102 | // SMBus Receive Byte - This function will write a single byte\r | |
| 103 | // of data to a specific Slave Device per SMBus Receive Byte\r | |
| 104 | // Protocol.\r | |
| 105 | // Arg0 = Address\r | |
| 106 | // Return: Success = Byte-Size Value\r | |
| 107 | // Failure = Word-Size Value = FFFFh.\r | |
| 108 | \r | |
| 109 | Method(SRXB,1,Serialized)\r | |
| 110 | {\r | |
| 111 | OperationRegion(SMPB,PCI_Config,0x20,4)\r | |
| 112 | Field(SMPB,DWordAcc,NoLock,Preserve)\r | |
| 113 | {\r | |
| 114 | , 5,\r | |
| 115 | SBAR, 11\r | |
| 116 | }\r | |
| 117 | \r | |
| 118 | // Define various SMBus IO Mapped Registers.\r | |
| 119 | \r | |
| 120 | OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r | |
| 121 | Field(SMBI,ByteAcc,NoLock,Preserve)\r | |
| 122 | {\r | |
| 123 | HSTS, 8, // 0 - Host Status Register\r | |
| 124 | Offset(0x02),\r | |
| 125 | HCON, 8, // 2 - Host Control\r | |
| 126 | HCOM, 8, // 3 - Host Command\r | |
| 127 | TXSA, 8, // 4 - Transmit Slave Address\r | |
| 128 | DAT0, 8, // 5 - Host Data 0\r | |
| 129 | DAT1, 8, // 6 - Host Data 1\r | |
| 130 | HBDR, 8, // 7 - Host Block Data\r | |
| 131 | PECR, 8, // 8 - Packer Error Check\r | |
| 132 | RXSA, 8, // 9 - Receive Slave Address\r | |
| 133 | SDAT, 16, // A - Slave Data\r | |
| 134 | }\r | |
| 135 | // Step 1: Confirm the ICHx SMBus is ready to perform\r | |
| 136 | // communication.\r | |
| 137 | \r | |
| 138 | If(STRT())\r | |
| 139 | {\r | |
| 140 | Return(0xFFFF)\r | |
| 141 | }\r | |
| 142 | \r | |
| 143 | // Step 2: Initiate a Receive Byte.\r | |
| 144 | \r | |
| 145 | Store(0,I2CE) // Ensure SMbus Mode.\r | |
| 146 | Store(0xBF,HSTS) // Clear all but INUSE_STS.\r | |
| 147 | Store(Or(Arg0,1),TXSA) // Read Address in TXSA.\r | |
| 148 | \r | |
| 149 | // Set the SMBus Host control register to 0x48.\r | |
| 150 | // Bit 7: = 0 = reserved\r | |
| 151 | // Bit 6: = 1 = start\r | |
| 152 | // Bit 5: = 0 = disregard, I2C related bit\r | |
| 153 | // Bits 4:2: = 001 = Byte Protocol\r | |
| 154 | // Bit 1: = 0 = Normal Function\r | |
| 155 | // Bit 0: = 0 = Disable interrupt generation\r | |
| 156 | \r | |
| 157 | Store(0x44,HCON)\r | |
| 158 | \r | |
| 159 | // Step 3: Exit the Method correctly.\r | |
| 160 | \r | |
| 161 | If(COMP)\r | |
| 162 | {\r | |
| 163 | Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others..\r | |
| 164 | Return(DAT0) // Return Success.\r | |
| 165 | }\r | |
| 166 | \r | |
| 167 | Return(0xFFFF) // Return Failure.\r | |
| 168 | }\r | |
| 169 | \r | |
| 170 | // SMBus Write Byte - This function will write a single byte\r | |
| 171 | // of data to a specific Slave Device per SMBus Write Byte\r | |
| 172 | // Protocol.\r | |
| 173 | // Arg0 = Address\r | |
| 174 | // Arg1 = Command\r | |
| 175 | // Arg2 = Data\r | |
| 176 | // Return: Success = 1\r | |
| 177 | // Failure = 0\r | |
| 178 | \r | |
| 179 | Method(SWRB,3,Serialized)\r | |
| 180 | {\r | |
| 181 | OperationRegion(SMPB,PCI_Config,0x20,4)\r | |
| 182 | Field(SMPB,DWordAcc,NoLock,Preserve)\r | |
| 183 | {\r | |
| 184 | , 5,\r | |
| 185 | SBAR, 11\r | |
| 186 | }\r | |
| 187 | \r | |
| 188 | // Define various SMBus IO Mapped Registers.\r | |
| 189 | \r | |
| 190 | OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r | |
| 191 | Field(SMBI,ByteAcc,NoLock,Preserve)\r | |
| 192 | {\r | |
| 193 | HSTS, 8, // 0 - Host Status Register\r | |
| 194 | Offset(0x02),\r | |
| 195 | HCON, 8, // 2 - Host Control\r | |
| 196 | HCOM, 8, // 3 - Host Command\r | |
| 197 | TXSA, 8, // 4 - Transmit Slave Address\r | |
| 198 | DAT0, 8, // 5 - Host Data 0\r | |
| 199 | DAT1, 8, // 6 - Host Data 1\r | |
| 200 | HBDR, 8, // 7 - Host Block Data\r | |
| 201 | PECR, 8, // 8 - Packer Error Check\r | |
| 202 | RXSA, 8, // 9 - Receive Slave Address\r | |
| 203 | SDAT, 16, // A - Slave Data\r | |
| 204 | }\r | |
| 205 | // Step 1: Confirm the ICHx SMBus is ready to perform communication.\r | |
| 206 | \r | |
| 207 | If(STRT())\r | |
| 208 | {\r | |
| 209 | Return(0)\r | |
| 210 | }\r | |
| 211 | \r | |
| 212 | // Step 2: Initiate a Write Byte.\r | |
| 213 | \r | |
| 214 | Store(0,I2CE) // Ensure SMbus Mode.\r | |
| 215 | Store(0xBF,HSTS) // Clear all but INUSE_STS.\r | |
| 216 | Store(Arg0,TXSA) // Write Address in TXSA.\r | |
| 217 | Store(Arg1,HCOM) // Command in HCOM.\r | |
| 218 | Store(Arg2,DAT0) // Data in DAT0.\r | |
| 219 | \r | |
| 220 | // Set the SMBus Host control register to 0x48.\r | |
| 221 | // Bit 7: = 0 = reserved\r | |
| 222 | // Bit 6: = 1 = start\r | |
| 223 | // Bit 5: = 0 = disregard, I2C related bit\r | |
| 224 | // Bits 4:2: = 010 = Byte Data Protocol\r | |
| 225 | // Bit 1: = 0 = Normal Function\r | |
| 226 | // Bit 0: = 0 = Disable interrupt generation\r | |
| 227 | \r | |
| 228 | Store(0x48,HCON)\r | |
| 229 | \r | |
| 230 | // Step 3: Exit the Method correctly.\r | |
| 231 | \r | |
| 232 | If(COMP)\r | |
| 233 | {\r | |
| 234 | Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others..\r | |
| 235 | Return(1) // Return Success.\r | |
| 236 | }\r | |
| 237 | \r | |
| 238 | Return(0) // Return Failure.\r | |
| 239 | }\r | |
| 240 | \r | |
| 241 | // SMBus Read Byte - This function will read a single byte of data\r | |
| 242 | // from a specific slave device per SMBus Read Byte Protocol.\r | |
| 243 | // Arg0 = Address\r | |
| 244 | // Arg1 = Command\r | |
| 245 | // Return: Success = Byte-Size Value\r | |
| 246 | // Failure = Word-Size Value\r | |
| 247 | \r | |
| 248 | Method(SRDB,2,Serialized)\r | |
| 249 | {\r | |
| 250 | OperationRegion(SMPB,PCI_Config,0x20,4)\r | |
| 251 | Field(SMPB,DWordAcc,NoLock,Preserve)\r | |
| 252 | {\r | |
| 253 | , 5,\r | |
| 254 | SBAR, 11\r | |
| 255 | }\r | |
| 256 | \r | |
| 257 | // Define various SMBus IO Mapped Registers.\r | |
| 258 | \r | |
| 259 | OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r | |
| 260 | Field(SMBI,ByteAcc,NoLock,Preserve)\r | |
| 261 | {\r | |
| 262 | HSTS, 8, // 0 - Host Status Register\r | |
| 263 | Offset(0x02),\r | |
| 264 | HCON, 8, // 2 - Host Control\r | |
| 265 | HCOM, 8, // 3 - Host Command\r | |
| 266 | TXSA, 8, // 4 - Transmit Slave Address\r | |
| 267 | DAT0, 8, // 5 - Host Data 0\r | |
| 268 | DAT1, 8, // 6 - Host Data 1\r | |
| 269 | HBDR, 8, // 7 - Host Block Data\r | |
| 270 | PECR, 8, // 8 - Packer Error Check\r | |
| 271 | RXSA, 8, // 9 - Receive Slave Address\r | |
| 272 | SDAT, 16, // A - Slave Data\r | |
| 273 | }\r | |
| 274 | // Step 1: Confirm the ICHx SMBus is ready to perform communication.\r | |
| 275 | \r | |
| 276 | If(STRT())\r | |
| 277 | {\r | |
| 278 | Return(0xFFFF)\r | |
| 279 | }\r | |
| 280 | \r | |
| 281 | // Step 2: Initiate a Read Byte.\r | |
| 282 | \r | |
| 283 | Store(0,I2CE) // Ensure SMbus Mode.\r | |
| 284 | Store(0xBF,HSTS) // Clear all but INUSE_STS.\r | |
| 285 | Store(Or(Arg0,1),TXSA) // Read Address in TXSA.\r | |
| 286 | Store(Arg1,HCOM) // Command in HCOM.\r | |
| 287 | \r | |
| 288 | // Set the SMBus Host control register to 0x48.\r | |
| 289 | // Bit 7: = 0 = reserved\r | |
| 290 | // Bit 6: = 1 = start\r | |
| 291 | // Bit 5: = 0 = disregard, I2C related bit\r | |
| 292 | // Bits 4:2: = 010 = Byte Data Protocol\r | |
| 293 | // Bit 1: = 0 = Normal Function\r | |
| 294 | // Bit 0: = 0 = Disable interrupt generation\r | |
| 295 | \r | |
| 296 | Store(0x48,HCON)\r | |
| 297 | \r | |
| 298 | // Step 3: Exit the Method correctly.\r | |
| 299 | \r | |
| 300 | If(COMP)\r | |
| 301 | {\r | |
| 302 | Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others..\r | |
| 303 | Return(DAT0) // Return Success.\r | |
| 304 | }\r | |
| 305 | \r | |
| 306 | Return(0xFFFF) // Return Failure.\r | |
| 307 | }\r | |
| 308 | \r | |
| 309 | // SMBus Write Word - This function will write a single word\r | |
| 310 | // of data to a specific Slave Device per SMBus Write Word\r | |
| 311 | // Protocol.\r | |
| 312 | // Arg0 = Address\r | |
| 313 | // Arg1 = Command\r | |
| 314 | // Arg2 = Data (16 bits in size)\r | |
| 315 | // Return: Success = 1\r | |
| 316 | // Failure = 0\r | |
| 317 | \r | |
| 318 | Method(SWRW,3,Serialized)\r | |
| 319 | {\r | |
| 320 | OperationRegion(SMPB,PCI_Config,0x20,4)\r | |
| 321 | Field(SMPB,DWordAcc,NoLock,Preserve)\r | |
| 322 | {\r | |
| 323 | , 5,\r | |
| 324 | SBAR, 11\r | |
| 325 | }\r | |
| 326 | \r | |
| 327 | // Define various SMBus IO Mapped Registers.\r | |
| 328 | \r | |
| 329 | OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r | |
| 330 | Field(SMBI,ByteAcc,NoLock,Preserve)\r | |
| 331 | {\r | |
| 332 | HSTS, 8, // 0 - Host Status Register\r | |
| 333 | Offset(0x02),\r | |
| 334 | HCON, 8, // 2 - Host Control\r | |
| 335 | HCOM, 8, // 3 - Host Command\r | |
| 336 | TXSA, 8, // 4 - Transmit Slave Address\r | |
| 337 | DAT0, 8, // 5 - Host Data 0\r | |
| 338 | DAT1, 8, // 6 - Host Data 1\r | |
| 339 | HBDR, 8, // 7 - Host Block Data\r | |
| 340 | PECR, 8, // 8 - Packer Error Check\r | |
| 341 | RXSA, 8, // 9 - Receive Slave Address\r | |
| 342 | SDAT, 16, // A - Slave Data\r | |
| 343 | }\r | |
| 344 | // Step 1: Confirm the ICHx SMBus is ready to perform communication.\r | |
| 345 | \r | |
| 346 | If(STRT())\r | |
| 347 | {\r | |
| 348 | Return(0)\r | |
| 349 | }\r | |
| 350 | \r | |
| 351 | // Step 2: Initiate a Write Word.\r | |
| 352 | \r | |
| 353 | Store(0,I2CE) // Ensure SMbus Mode.\r | |
| 354 | Store(0xBF,HSTS) // Clear all but INUSE_STS.\r | |
| 355 | Store(Arg0,TXSA) // Write Address in TXSA.\r | |
| 356 | Store(Arg1,HCOM) // Command in HCOM.\r | |
| 357 | And(Arg2,0xFF,DAT1) // Low byte Data in DAT1.\r | |
| 358 | And(ShiftRight(Arg2,8),0xFF,DAT0) // High byte Data in DAT0.\r | |
| 359 | \r | |
| 360 | // Set the SMBus Host control register to 0x4C.\r | |
| 361 | // Bit 7: = 0 = reserved\r | |
| 362 | // Bit 6: = 1 = start\r | |
| 363 | // Bit 5: = 0 = disregard, I2C related bit\r | |
| 364 | // Bits 4:2: = 011 = Word Data Protocol\r | |
| 365 | // Bit 1: = 0 = Normal Function\r | |
| 366 | // Bit 0: = 0 = Disable interrupt generation\r | |
| 367 | \r | |
| 368 | Store(0x4C,HCON)\r | |
| 369 | \r | |
| 370 | // Step 3: Exit the Method correctly.\r | |
| 371 | \r | |
| 372 | If(COMP())\r | |
| 373 | {\r | |
| 374 | Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others.\r | |
| 375 | Return(1) // Return Success.\r | |
| 376 | }\r | |
| 377 | \r | |
| 378 | Return(0) // Return Failure.\r | |
| 379 | }\r | |
| 380 | \r | |
| 381 | // SMBus Read Word - This function will read a single byte of data\r | |
| 382 | // from a specific slave device per SMBus Read Word Protocol.\r | |
| 383 | // Arg0 = Address\r | |
| 384 | // Arg1 = Command\r | |
| 385 | // Return: Success = Word-Size Value\r | |
| 386 | // Failure = Dword-Size Value\r | |
| 387 | \r | |
| 388 | Method(SRDW,2,Serialized)\r | |
| 389 | {\r | |
| 390 | OperationRegion(SMPB,PCI_Config,0x20,4)\r | |
| 391 | Field(SMPB,DWordAcc,NoLock,Preserve)\r | |
| 392 | {\r | |
| 393 | , 5,\r | |
| 394 | SBAR, 11\r | |
| 395 | }\r | |
| 396 | \r | |
| 397 | // Define various SMBus IO Mapped Registers.\r | |
| 398 | \r | |
| 399 | OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r | |
| 400 | Field(SMBI,ByteAcc,NoLock,Preserve)\r | |
| 401 | {\r | |
| 402 | HSTS, 8, // 0 - Host Status Register\r | |
| 403 | Offset(0x02),\r | |
| 404 | HCON, 8, // 2 - Host Control\r | |
| 405 | HCOM, 8, // 3 - Host Command\r | |
| 406 | TXSA, 8, // 4 - Transmit Slave Address\r | |
| 407 | DAT0, 8, // 5 - Host Data 0\r | |
| 408 | DAT1, 8, // 6 - Host Data 1\r | |
| 409 | HBDR, 8, // 7 - Host Block Data\r | |
| 410 | PECR, 8, // 8 - Packer Error Check\r | |
| 411 | RXSA, 8, // 9 - Receive Slave Address\r | |
| 412 | SDAT, 16, // A - Slave Data\r | |
| 413 | }\r | |
| 414 | // Step 1: Confirm the ICHx SMBus is ready to perform communication.\r | |
| 415 | \r | |
| 416 | If(STRT())\r | |
| 417 | {\r | |
| 418 | Return(0xFFFF)\r | |
| 419 | }\r | |
| 420 | \r | |
| 421 | // Step 2: Initiate a Read Word.\r | |
| 422 | \r | |
| 423 | Store(0,I2CE) // Ensure SMbus Mode.\r | |
| 424 | Store(0xBF,HSTS) // Clear all but INUSE_STS.\r | |
| 425 | Store(Or(Arg0,1),TXSA) // Read Address in TXSA.\r | |
| 426 | Store(Arg1,HCOM) // Command in HCOM.\r | |
| 427 | \r | |
| 428 | // Set the SMBus Host control register to 0x4C.\r | |
| 429 | // Bit 7: = 0 = reserved\r | |
| 430 | // Bit 6: = 1 = start\r | |
| 431 | // Bit 5: = 0 = disregard, I2C related bit\r | |
| 432 | // Bits 4:2: = 011 = Word Data Protocol\r | |
| 433 | // Bit 1: = 0 = Normal Function\r | |
| 434 | // Bit 0: = 0 = Disable interrupt generation\r | |
| 435 | \r | |
| 436 | Store(0x4C,HCON)\r | |
| 437 | \r | |
| 438 | // Step 3: Exit the Method correctly.\r | |
| 439 | \r | |
| 440 | If(COMP())\r | |
| 441 | {\r | |
| 442 | Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others.\r | |
| 443 | Return(Or(ShiftLeft(DAT0,8),DAT1)) // Return Success.\r | |
| 444 | }\r | |
| 445 | \r | |
| 446 | Return(0xFFFFFFFF) // Return Failure.\r | |
| 447 | }\r | |
| 448 | \r | |
| 449 | // SMBus Block Write - This function will write an entire block of data\r | |
| 450 | // to a specific slave device per SMBus Block Write Protocol.\r | |
| 451 | // Arg0 = Address\r | |
| 452 | // Arg1 = Command\r | |
| 453 | // Arg2 = Buffer of Data to Write\r | |
| 454 | // Arg3 = 1 = I2C Block Write, 0 = SMBus Block Write\r | |
| 455 | // Return: Success = 1\r | |
| 456 | // Failure = 0\r | |
| 457 | \r | |
| 458 | Method(SBLW,4,Serialized)\r | |
| 459 | {\r | |
| 460 | OperationRegion(SMPB,PCI_Config,0x20,4)\r | |
| 461 | Field(SMPB,DWordAcc,NoLock,Preserve)\r | |
| 462 | {\r | |
| 463 | , 5,\r | |
| 464 | SBAR, 11\r | |
| 465 | }\r | |
| 466 | \r | |
| 467 | // Define various SMBus IO Mapped Registers.\r | |
| 468 | \r | |
| 469 | OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r | |
| 470 | Field(SMBI,ByteAcc,NoLock,Preserve)\r | |
| 471 | {\r | |
| 472 | HSTS, 8, // 0 - Host Status Register\r | |
| 473 | Offset(0x02),\r | |
| 474 | HCON, 8, // 2 - Host Control\r | |
| 475 | HCOM, 8, // 3 - Host Command\r | |
| 476 | TXSA, 8, // 4 - Transmit Slave Address\r | |
| 477 | DAT0, 8, // 5 - Host Data 0\r | |
| 478 | DAT1, 8, // 6 - Host Data 1\r | |
| 479 | HBDR, 8, // 7 - Host Block Data\r | |
| 480 | PECR, 8, // 8 - Packer Error Check\r | |
| 481 | RXSA, 8, // 9 - Receive Slave Address\r | |
| 482 | SDAT, 16, // A - Slave Data\r | |
| 483 | }\r | |
| 484 | // Step 1: Confirm the ICHx SMBus is ready to perform communication.\r | |
| 485 | \r | |
| 486 | If(STRT())\r | |
| 487 | {\r | |
| 488 | Return(0)\r | |
| 489 | }\r | |
| 490 | \r | |
| 491 | // Step 2: Initiate a Block Write.\r | |
| 492 | \r | |
| 493 | Store(Arg3,I2CE) // Select the proper protocol.\r | |
| 494 | Store(0xBF,HSTS) // Clear all but INUSE_STS.\r | |
| 495 | Store(Arg0,TXSA) // Write Address in TXSA.\r | |
| 496 | Store(Arg1,HCOM) // Command in HCOM.\r | |
| 497 | Store(Sizeof(Arg2),DAT0) // Count in DAT0.\r | |
| 498 | Store(0,Local1) // Init Pointer to Buffer.\r | |
| 499 | Store(DerefOf(Index(Arg2,0)),HBDR) // First Byte in HBD Register.\r | |
| 500 | \r | |
| 501 | // Set the SMBus Host control register to 0x48.\r | |
| 502 | // Bit 7: = 0 = reserved\r | |
| 503 | // Bit 6: = 1 = start\r | |
| 504 | // Bit 5: = 0 = disregard, I2C related bit\r | |
| 505 | // Bits 4:2: = 101 = Block Protocol\r | |
| 506 | // Bit 1: = 0 = Normal Function\r | |
| 507 | // Bit 0: = 0 = Disable interrupt generation\r | |
| 508 | \r | |
| 509 | Store(0x54,HCON)\r | |
| 510 | \r | |
| 511 | // Step 3: Send the entire Block of Data.\r | |
| 512 | \r | |
| 513 | While(LGreater(Sizeof(Arg2),Local1))\r | |
| 514 | {\r | |
| 515 | // Wait up to 200ms for Host Status to get set.\r | |
| 516 | \r | |
| 517 | Store(4000,Local0) // 4000 * 50us = 200ms.\r | |
| 518 | \r | |
| 519 | While(LAnd(LNot(And(HSTS,0x80)),Local0))\r | |
| 520 | {\r | |
| 521 | Decrement(Local0) // Decrement Count.\r | |
| 522 | Stall(50) // Delay = 50us.\r | |
| 523 | }\r | |
| 524 | \r | |
| 525 | If(LNot(Local0)) // Timeout?\r | |
| 526 | {\r | |
| 527 | KILL() // Yes. Kill Communication.\r | |
| 528 | Return(0) // Return failure.\r | |
| 529 | }\r | |
| 530 | \r | |
| 531 | Store(0x80,HSTS) // Clear Host Status.\r | |
| 532 | Increment(Local1) // Point to Next Byte.\r | |
| 533 | \r | |
| 534 | // Place next byte in HBDR if last byte has not been sent.\r | |
| 535 | \r | |
| 536 | If(LGreater(Sizeof(Arg2),Local1))\r | |
| 537 | {\r | |
| 538 | Store(DerefOf(Index(Arg2,Local1)),HBDR)\r | |
| 539 | }\r | |
| 540 | }\r | |
| 541 | \r | |
| 542 | // Step 4: Exit the Method correctly.\r | |
| 543 | \r | |
| 544 | If(COMP())\r | |
| 545 | {\r | |
| 546 | Or(HSTS,0xFF,HSTS) // Clear all status bits.\r | |
| 547 | Return(1) // Return Success.\r | |
| 548 | }\r | |
| 549 | \r | |
| 550 | Return(0) // Return Failure.\r | |
| 551 | }\r | |
| 552 | \r | |
| 553 | // SMBus Block Read - This function will read a block of data from\r | |
| 554 | // a specific slave device per SMBus Block Read Protocol.\r | |
| 555 | // Arg0 = Address\r | |
| 556 | // Arg1 = Command\r | |
| 557 | // Arg2 = 1 = I2C Block Write, 0 = SMBus Block Write\r | |
| 558 | // Return: Success = Data Buffer (First Byte = length)\r | |
| 559 | // Failure = 0\r | |
| 560 | \r | |
| 561 | Method(SBLR,3,Serialized)\r | |
| 562 | {\r | |
| 563 | OperationRegion(SMPB,PCI_Config,0x20,4)\r | |
| 564 | Field(SMPB,DWordAcc,NoLock,Preserve)\r | |
| 565 | {\r | |
| 566 | , 5,\r | |
| 567 | SBAR, 11\r | |
| 568 | }\r | |
| 569 | \r | |
| 570 | // Define various SMBus IO Mapped Registers.\r | |
| 571 | \r | |
| 572 | OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r | |
| 573 | Field(SMBI,ByteAcc,NoLock,Preserve)\r | |
| 574 | {\r | |
| 575 | HSTS, 8, // 0 - Host Status Register\r | |
| 576 | Offset(0x02),\r | |
| 577 | HCON, 8, // 2 - Host Control\r | |
| 578 | HCOM, 8, // 3 - Host Command\r | |
| 579 | TXSA, 8, // 4 - Transmit Slave Address\r | |
| 580 | DAT0, 8, // 5 - Host Data 0\r | |
| 581 | DAT1, 8, // 6 - Host Data 1\r | |
| 582 | HBDR, 8, // 7 - Host Block Data\r | |
| 583 | PECR, 8, // 8 - Packer Error Check\r | |
| 584 | RXSA, 8, // 9 - Receive Slave Address\r | |
| 585 | SDAT, 16, // A - Slave Data\r | |
| 586 | }\r | |
| 587 | Name(TBUF, Buffer(256) {})\r | |
| 588 | \r | |
| 589 | // Step 1: Confirm the ICHx SMBus is ready to perform communication.\r | |
| 590 | \r | |
| 591 | If(STRT())\r | |
| 592 | {\r | |
| 593 | Return(0)\r | |
| 594 | }\r | |
| 595 | \r | |
| 596 | // Step 2: Initiate a Block Read.\r | |
| 597 | \r | |
| 598 | Store(Arg2,I2CE) // Select the proper protocol.\r | |
| 599 | Store(0xBF,HSTS) // Clear all but INUSE_STS.\r | |
| 600 | Store(Or(Arg0,1),TXSA) // Read Address in TXSA.\r | |
| 601 | Store(Arg1,HCOM) // Command in HCOM.\r | |
| 602 | \r | |
| 603 | // Set the SMBus Host control register to 0x48.\r | |
| 604 | // Bit 7: = 0 = reserved\r | |
| 605 | // Bit 6: = 1 = start\r | |
| 606 | // Bit 5: = 0 = disregard, I2C related bit\r | |
| 607 | // Bits 4:2: = 101 = Block Protocol\r | |
| 608 | // Bit 1: = 0 = Normal Function\r | |
| 609 | // Bit 0: = 0 = Disable interrupt generation\r | |
| 610 | \r | |
| 611 | Store(0x54,HCON)\r | |
| 612 | \r | |
| 613 | // Step 3: Wait up to 200ms to get the Data Count.\r | |
| 614 | \r | |
| 615 | Store(4000,Local0) // 4000 * 50us = 200ms.\r | |
| 616 | \r | |
| 617 | While(LAnd(LNot(And(HSTS,0x80)),Local0))\r | |
| 618 | {\r | |
| 619 | Decrement(Local0) // Decrement Count.\r | |
| 620 | Stall(50) // Delay = 50us.\r | |
| 621 | }\r | |
| 622 | \r | |
| 623 | If(LNot(Local0)) // Timeout?\r | |
| 624 | {\r | |
| 625 | KILL() // Yes. Kill Communication.\r | |
| 626 | Return(0) // Return failure.\r | |
| 627 | }\r | |
| 628 | \r | |
| 629 | Store(DAT0,Index(TBUF,0)) // Get the Data Count.\r | |
| 630 | Store(0x80,HSTS) // Clear Host Status.\r | |
| 631 | Store(1,Local1) // Local1 = Buffer Pointer.\r | |
| 632 | \r | |
| 633 | // Step 4: Get the Block Data and store it.\r | |
| 634 | \r | |
| 635 | While(LLess(Local1,DerefOf(Index(TBUF,0))))\r | |
| 636 | {\r | |
| 637 | // Wait up to 200ms for Host Status to get set.\r | |
| 638 | \r | |
| 639 | Store(4000,Local0) // 4000 * 50us = 200ms.\r | |
| 640 | \r | |
| 641 | While(LAnd(LNot(And(HSTS,0x80)),Local0))\r | |
| 642 | {\r | |
| 643 | Decrement(Local0) // Decrement Count.\r | |
| 644 | Stall(50) // Delay = 50us.\r | |
| 645 | }\r | |
| 646 | \r | |
| 647 | If(LNot(Local0)) // Timeout?\r | |
| 648 | {\r | |
| 649 | KILL() // Yes. Kill Communication.\r | |
| 650 | Return(0) // Return failure.\r | |
| 651 | }\r | |
| 652 | \r | |
| 653 | Store(HBDR,Index(TBUF,Local1)) // Place into Buffer.\r | |
| 654 | Store(0x80,HSTS) // Clear Host Status.\r | |
| 655 | Increment(Local1)\r | |
| 656 | }\r | |
| 657 | \r | |
| 658 | // Step 5: Exit the Method correctly.\r | |
| 659 | \r | |
| 660 | If(COMP())\r | |
| 661 | {\r | |
| 662 | Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others.\r | |
| 663 | Return(TBUF) // Return Success.\r | |
| 664 | }\r | |
| 665 | \r | |
| 666 | Return(0) // Return Failure.\r | |
| 667 | }\r | |
| 668 | \r | |
| 669 | \r | |
| 670 | // SMBus Start Check\r | |
| 671 | // Return: Success = 0\r | |
| 672 | // Failure = 1\r | |
| 673 | \r | |
| 674 | Method(STRT,0,Serialized)\r | |
| 675 | {\r | |
| 676 | OperationRegion(SMPB,PCI_Config,0x20,4)\r | |
| 677 | Field(SMPB,DWordAcc,NoLock,Preserve)\r | |
| 678 | {\r | |
| 679 | , 5,\r | |
| 680 | SBAR, 11\r | |
| 681 | }\r | |
| 682 | \r | |
| 683 | // Define various SMBus IO Mapped Registers.\r | |
| 684 | \r | |
| 685 | OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r | |
| 686 | Field(SMBI,ByteAcc,NoLock,Preserve)\r | |
| 687 | {\r | |
| 688 | HSTS, 8, // 0 - Host Status Register\r | |
| 689 | Offset(0x02),\r | |
| 690 | HCON, 8, // 2 - Host Control\r | |
| 691 | HCOM, 8, // 3 - Host Command\r | |
| 692 | TXSA, 8, // 4 - Transmit Slave Address\r | |
| 693 | DAT0, 8, // 5 - Host Data 0\r | |
| 694 | DAT1, 8, // 6 - Host Data 1\r | |
| 695 | HBDR, 8, // 7 - Host Block Data\r | |
| 696 | PECR, 8, // 8 - Packer Error Check\r | |
| 697 | RXSA, 8, // 9 - Receive Slave Address\r | |
| 698 | SDAT, 16, // A - Slave Data\r | |
| 699 | }\r | |
| 700 | // Wait up to 200ms to confirm the SMBus Semaphore has been\r | |
| 701 | // released (In Use Status = 0). Note that the Sleep time may take\r | |
| 702 | // longer as the This function will yield the Processor such that it\r | |
| 703 | // may perform different tasks during the delay.\r | |
| 704 | \r | |
| 705 | Store(200,Local0) // 200 * 1ms = 200ms.\r | |
| 706 | \r | |
| 707 | While(Local0)\r | |
| 708 | {\r | |
| 709 | If(And(HSTS,0x40)) // In Use Set?\r | |
| 710 | {\r | |
| 711 | Decrement(Local0) // Yes. Decrement Count.\r | |
| 712 | Sleep(1) // Delay = 1ms.\r | |
| 713 | If(LEqual(Local0,0)) // Count = 0?\r | |
| 714 | {\r | |
| 715 | Return(1) // Return failure.\r | |
| 716 | }\r | |
| 717 | }\r | |
| 718 | Else\r | |
| 719 | {\r | |
| 720 | Store(0,Local0) // In Use Clear. Continue.\r | |
| 721 | }\r | |
| 722 | }\r | |
| 723 | \r | |
| 724 | // In Use Status = 0 during last read, which will make subsequent\r | |
| 725 | // reads return In Use Status = 1 until software clears it. All\r | |
| 726 | // software using ICHx SMBus should check this bit before initiating\r | |
| 727 | // any SMBus communication.\r | |
| 728 | \r | |
| 729 | // Wait up to 200ms to confirm the Host Interface is\r | |
| 730 | // not processing a command.\r | |
| 731 | \r | |
| 732 | Store(4000,Local0) // 4000 * 50us = 200ms.\r | |
| 733 | \r | |
| 734 | While(Local0)\r | |
| 735 | {\r | |
| 736 | If(And(HSTS,0x01)) // Host Busy Set?\r | |
| 737 | {\r | |
| 738 | Decrement(Local0) // Decrement Count.\r | |
| 739 | Stall(50) // Delay = 50us.\r | |
| 740 | If(LEqual(Local0,0)) // Count = 0?\r | |
| 741 | {\r | |
| 742 | KILL() // Yes. Kill Communication.\r | |
| 743 | }\r | |
| 744 | }\r | |
| 745 | Else\r | |
| 746 | {\r | |
| 747 | Return(0)\r | |
| 748 | }\r | |
| 749 | }\r | |
| 750 | \r | |
| 751 | Return(1) // Timeout. Return failure.\r | |
| 752 | }\r | |
| 753 | \r | |
| 754 | // SMBus Completion Check\r | |
| 755 | // Return: Success = 1\r | |
| 756 | // Failure = 0\r | |
| 757 | \r | |
| 758 | Method(COMP,0,Serialized)\r | |
| 759 | {\r | |
| 760 | OperationRegion(SMPB,PCI_Config,0x20,4)\r | |
| 761 | Field(SMPB,DWordAcc,NoLock,Preserve)\r | |
| 762 | {\r | |
| 763 | , 5,\r | |
| 764 | SBAR, 11\r | |
| 765 | }\r | |
| 766 | \r | |
| 767 | // Define various SMBus IO Mapped Registers.\r | |
| 768 | \r | |
| 769 | OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r | |
| 770 | Field(SMBI,ByteAcc,NoLock,Preserve)\r | |
| 771 | {\r | |
| 772 | HSTS, 8, // 0 - Host Status Register\r | |
| 773 | Offset(0x02),\r | |
| 774 | HCON, 8, // 2 - Host Control\r | |
| 775 | HCOM, 8, // 3 - Host Command\r | |
| 776 | TXSA, 8, // 4 - Transmit Slave Address\r | |
| 777 | DAT0, 8, // 5 - Host Data 0\r | |
| 778 | DAT1, 8, // 6 - Host Data 1\r | |
| 779 | HBDR, 8, // 7 - Host Block Data\r | |
| 780 | PECR, 8, // 8 - Packer Error Check\r | |
| 781 | RXSA, 8, // 9 - Receive Slave Address\r | |
| 782 | SDAT, 16, // A - Slave Data\r | |
| 783 | }\r | |
| 784 | // Wait for up to 200ms for the Completion Command\r | |
| 785 | // Status to get set.\r | |
| 786 | \r | |
| 787 | Store(4000,Local0) // 4000 * 50us = 200ms.\r | |
| 788 | \r | |
| 789 | While(Local0)\r | |
| 790 | {\r | |
| 791 | If(And(HSTS,0x02)) // Completion Status Set?\r | |
| 792 | {\r | |
| 793 | Return(1) // Yes. We are done.\r | |
| 794 | }\r | |
| 795 | Else\r | |
| 796 | {\r | |
| 797 | Decrement(Local0) // Decrement Count.\r | |
| 798 | Stall(50) // Delay 50us.\r | |
| 799 | If(LEqual(Local0,0)) // Count = 0?\r | |
| 800 | {\r | |
| 801 | KILL() // Yes. Kill Communication.\r | |
| 802 | }\r | |
| 803 | }\r | |
| 804 | }\r | |
| 805 | \r | |
| 806 | Return(0) // Timeout. Return Failure.\r | |
| 807 | }\r | |
| 808 | \r | |
| 809 | // SMBus Kill Command\r | |
| 810 | \r | |
| 811 | Method(KILL,0,Serialized)\r | |
| 812 | {\r | |
| 813 | OperationRegion(SMPB,PCI_Config,0x20,4)\r | |
| 814 | Field(SMPB,DWordAcc,NoLock,Preserve)\r | |
| 815 | {\r | |
| 816 | , 5,\r | |
| 817 | SBAR, 11\r | |
| 818 | }\r | |
| 819 | \r | |
| 820 | // Define various SMBus IO Mapped Registers.\r | |
| 821 | \r | |
| 822 | OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r | |
| 823 | Field(SMBI,ByteAcc,NoLock,Preserve)\r | |
| 824 | {\r | |
| 825 | HSTS, 8, // 0 - Host Status Register\r | |
| 826 | Offset(0x02),\r | |
| 827 | HCON, 8, // 2 - Host Control\r | |
| 828 | HCOM, 8, // 3 - Host Command\r | |
| 829 | TXSA, 8, // 4 - Transmit Slave Address\r | |
| 830 | DAT0, 8, // 5 - Host Data 0\r | |
| 831 | DAT1, 8, // 6 - Host Data 1\r | |
| 832 | HBDR, 8, // 7 - Host Block Data\r | |
| 833 | PECR, 8, // 8 - Packer Error Check\r | |
| 834 | RXSA, 8, // 9 - Receive Slave Address\r | |
| 835 | SDAT, 16, // A - Slave Data\r | |
| 836 | }\r | |
| 837 | Or(HCON,0x02,HCON) // Yes. Send Kill command.\r | |
| 838 | Or(HSTS,0xFF,HSTS) // Clear all status.\r | |
| 839 | }\r |