[mirror_edk2.git] / Vlv2DeviceRefCodePkg / AcpiTablesPCAT / RhProxy.asl

/** @file\r
  SSDT for RhProxy Driver.\r
\r
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
DefinitionBlock ("RHPX.aml", "SSDT", 1, "MSFT", "RHPROXY", 1)\r
{\r
    Scope (\_SB)\r
    {\r
        //\r
        // Test peripheral device node for MinnowBoardMax\r
        //\r
        Device(RHPX)\r
        {\r
            Name(_HID, "MSFT8000")\r
            Name(_CID, "MSFT8000")\r
            Name(_UID, 1)\r
\r
            Name(_CRS, ResourceTemplate() \r
            {  \r
                // Index 0 \r
                SPISerialBus(            // Pin 5, 7, 9 , 11 of JP1 for SIO_SPI\r
                    1,                     // Device selection\r
                    PolarityLow,           // Device selection polarity\r
                    FourWireMode,          // wiremode\r
                    8,                     // databit len\r
                    ControllerInitiated,   // slave mode\r
                    8000000,               // Connection speed\r
                    ClockPolarityLow,      // Clock polarity\r
                    ClockPhaseSecond,      // clock phase\r
                    "\\_SB.SPI1",          // ResourceSource: SPI bus controller name\r
                    0,                     // ResourceSourceIndex\r
                    ResourceConsumer,      // Resource usage\r
                    JSPI,                  // DescriptorName: creates name for offset of resource descriptor\r
                    )                      // Vendor Data  \r
    \r
                // Index 1     \r
                I2CSerialBus(            // Pin 13, 15 of JP1, for SIO_I2C5 (signal)\r
                    0xFF,                  // SlaveAddress: bus address (TBD)\r
                    ,                      // SlaveMode: default to ControllerInitiated\r
                    400000,                // ConnectionSpeed: in Hz\r
                    ,                      // Addressing Mode: default to 7 bit\r
                    "\\_SB.I2C6",          // ResourceSource: I2C bus controller name (For MinnowBoard Max, hardware I2C5(0-based) is reported as ACPI I2C6(1-based))\r
                    ,\r
                    ,\r
                    JI2C,                  // Descriptor Name: creates name for offset of resource descriptor\r
                    )                      // VendorData\r
    \r
                // Index 2\r
                UARTSerialBus(           // Pin 17, 19 of JP1, for SIO_UART2\r
                    115200,                // InitialBaudRate: in bits ber second\r
                    ,                      // BitsPerByte: default to 8 bits\r
                    ,                      // StopBits: Defaults to one bit\r
                    0xfc,                  // LinesInUse: 8 1-bit flags to declare line enabled\r
                    ,                      // IsBigEndian: default to LittleEndian\r
                    ,                      // Parity: Defaults to no parity\r
                    ,                      // FlowControl: Defaults to no flow control\r
                    32,                    // ReceiveBufferSize\r
                    32,                    // TransmitBufferSize\r
                    "\\_SB.URT2",          // ResourceSource: UART bus controller name\r
                    ,\r
                    ,\r
                    UAR2,                  // DescriptorName: creates name for offset of resource descriptor\r
                    )                      \r
    \r
                // Index 3\r
                GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {0}  // Pin 21 of JP1 (GPIO_S5[00])\r
                // Index 4\r
                GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {0} \r
    \r
                // Index 5\r
                GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {1}  // Pin 23 of JP1 (GPIO_S5[01])\r
                // Index 6\r
                GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {1}\r
    \r
                // Index 7\r
                GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {2}  // Pin 25 of JP1 (GPIO_S5[02])\r
                // Index 8\r
                GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {2} \r
    \r
                // Index 9\r
                UARTSerialBus(           // Pin 6, 8, 10, 12 of JP1, for SIO_UART1\r
                    115200,                // InitialBaudRate: in bits ber second\r
                    ,                      // BitsPerByte: default to 8 bits\r
                    ,                      // StopBits: Defaults to one bit\r
                    0xfc,                  // LinesInUse: 8 1-bit flags to declare line enabled\r
                    ,                      // IsBigEndian: default to LittleEndian\r
                    ,                      // Parity: Defaults to no parity\r
                    FlowControlHardware,   // FlowControl: Defaults to no flow control\r
                    32,                    // ReceiveBufferSize\r
                    32,                    // TransmitBufferSize\r
                    "\\_SB.URT1",          // ResourceSource: UART bus controller name\r
                    ,\r
                    ,\r
                    UAR1,              // DescriptorName: creates name for offset of resource descriptor\r
                    )  \r
    \r
                // Index 10\r
                GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {62}  // Pin 14 of JP1 (GPIO_SC[62])\r
                // Index 11\r
                GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {62} \r
\r
                // Index 12\r
                GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {63}  // Pin 16 of JP1 (GPIO_SC[63])\r
                // Index 13\r
                GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {63} \r
    \r
                // Index 14\r
                GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {65}  // Pin 18 of JP1 (GPIO_SC[65])\r
                // Index 15\r
                GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {65} \r
    \r
                // Index 16\r
                GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {64}  // Pin 20 of JP1 (GPIO_SC[64])\r
                // Index 17\r
                GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {64} \r
    \r
                // Index 18\r
                GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {94}  // Pin 22 of JP1 (GPIO_SC[94])\r
                // Index 19\r
                GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {94} \r
    \r
                // Index 20\r
                GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {95}  // Pin 24 of JP1 (GPIO_SC[95])\r
                // Index 21\r
                GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {95} \r
    \r
                // Index 22\r
                GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {54}  // Pin 26 of JP1 (GPIO_SC[54])\r
                // Index 23\r
                GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {54}\r
            })\r
    \r
            Name(_DSD, Package() \r
            {\r
                ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),\r
                Package() \r
                {\r
                    // SPI Mapping\r
                    Package(2) { "bus-SPI-SPI0", Package() { 0 }},\r
\r
                    // TODO: Intel will need to provide the right value for SPI0 properties\r
                    Package(2) { "SPI0-MinClockInHz", 100000 },\r
                    Package(2) { "SPI0-MaxClockInHz", 15000000 },\r
                    // SupportedDataBitLengths takes a list of support data bit length\r
                    // Example : Package(2) { "SPI0-SupportedDataBitLengths", Package() { 8, 7, 16 }},\r
                    Package(2) { "SPI0-SupportedDataBitLengths", Package() { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 }},\r
                    // I2C Mapping\r
                    Package(2) { "bus-I2C-I2C5", Package() { 1 }},\r
                    // UART Mapping\r
                    Package(2) { "bus-UART-UART2", Package() { 2 }},\r
                    Package(2) { "bus-UART-UART1", Package() { 9 }},\r
                }\r
            })\r
        }\r
    }\r
}
Commit	Line	Data
b2499fe6 DW	1	/** @file\r
	2	SSDT for RhProxy Driver.\r
	3	\r
	4	Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
	5	This program and the accompanying materials\r
	6	are licensed and made available under the terms and conditions of the BSD License\r
	7	which accompanies this distribution. The full text of the license may be found at\r
	8	http://opensource.org/licenses/bsd-license.php\r
	9	\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	12	\r
	13	**/\r
	14	\r
	15	DefinitionBlock ("RHPX.aml", "SSDT", 1, "MSFT", "RHPROXY", 1)\r
	16	{\r
	17	Scope (\_SB)\r
	18	{\r
	19	//\r
	20	// Test peripheral device node for MinnowBoardMax\r
	21	//\r
	22	Device(RHPX)\r
	23	{\r
	24	Name(_HID, "MSFT8000")\r
	25	Name(_CID, "MSFT8000")\r
	26	Name(_UID, 1)\r
	27	\r
	28	Name(_CRS, ResourceTemplate() \r
	29	{ \r
	30	// Index 0 \r
	31	SPISerialBus( // Pin 5, 7, 9 , 11 of JP1 for SIO_SPI\r
	32	1, // Device selection\r
	33	PolarityLow, // Device selection polarity\r
	34	FourWireMode, // wiremode\r
	35	8, // databit len\r
	36	ControllerInitiated, // slave mode\r
	37	8000000, // Connection speed\r
	38	ClockPolarityLow, // Clock polarity\r
	39	ClockPhaseSecond, // clock phase\r
	40	"\\_SB.SPI1", // ResourceSource: SPI bus controller name\r
	41	0, // ResourceSourceIndex\r
	42	ResourceConsumer, // Resource usage\r
	43	JSPI, // DescriptorName: creates name for offset of resource descriptor\r
	44	) // Vendor Data \r
	45	\r
	46	// Index 1 \r
	47	I2CSerialBus( // Pin 13, 15 of JP1, for SIO_I2C5 (signal)\r
	48	0xFF, // SlaveAddress: bus address (TBD)\r
	49	, // SlaveMode: default to ControllerInitiated\r
	50	400000, // ConnectionSpeed: in Hz\r
	51	, // Addressing Mode: default to 7 bit\r
	52	"\\_SB.I2C6", // ResourceSource: I2C bus controller name (For MinnowBoard Max, hardware I2C5(0-based) is reported as ACPI I2C6(1-based))\r
	53	,\r
	54	,\r
	55	JI2C, // Descriptor Name: creates name for offset of resource descriptor\r
	56	) // VendorData\r
	57	\r
	58	// Index 2\r
	59	UARTSerialBus( // Pin 17, 19 of JP1, for SIO_UART2\r
	60	115200, // InitialBaudRate: in bits ber second\r
	61	, // BitsPerByte: default to 8 bits\r
	62	, // StopBits: Defaults to one bit\r
	63	0xfc, // LinesInUse: 8 1-bit flags to declare line enabled\r
	64	, // IsBigEndian: default to LittleEndian\r
65	, // Parity: Defaults to no parity\r
66	, // FlowControl: Defaults to no flow control\r
67	32, // ReceiveBufferSize\r
68	32, // TransmitBufferSize\r
69	"\\_SB.URT2", // ResourceSource: UART bus controller name\r
70	,\r
71	,\r
72	UAR2, // DescriptorName: creates name for offset of resource descriptor\r
73	) \r
74	\r
75	// Index 3\r
76	GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {0} // Pin 21 of JP1 (GPIO_S5[00])\r
77	// Index 4\r
78	GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {0} \r
79	\r
80	// Index 5\r
81	GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {1} // Pin 23 of JP1 (GPIO_S5[01])\r
82	// Index 6\r
83	GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {1}\r
84	\r
85	// Index 7\r
86	GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {2} // Pin 25 of JP1 (GPIO_S5[02])\r
87	// Index 8\r
88	GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {2} \r
89	\r
90	// Index 9\r
91	UARTSerialBus( // Pin 6, 8, 10, 12 of JP1, for SIO_UART1\r
92	115200, // InitialBaudRate: in bits ber second\r
93	, // BitsPerByte: default to 8 bits\r
94	, // StopBits: Defaults to one bit\r
95	0xfc, // LinesInUse: 8 1-bit flags to declare line enabled\r
96	, // IsBigEndian: default to LittleEndian\r
97	, // Parity: Defaults to no parity\r
98	FlowControlHardware, // FlowControl: Defaults to no flow control\r
99	32, // ReceiveBufferSize\r
100	32, // TransmitBufferSize\r
101	"\\_SB.URT1", // ResourceSource: UART bus controller name\r
102	,\r
103	,\r
104	UAR1, // DescriptorName: creates name for offset of resource descriptor\r
105	) \r
106	\r
107	// Index 10\r
108	GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {62} // Pin 14 of JP1 (GPIO_SC[62])\r
109	// Index 11\r
110	GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {62} \r
111	\r
112	// Index 12\r
113	GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {63} // Pin 16 of JP1 (GPIO_SC[63])\r
114	// Index 13\r
115	GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {63} \r
116	\r
117	// Index 14\r
118	GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {65} // Pin 18 of JP1 (GPIO_SC[65])\r
119	// Index 15\r
120	GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {65} \r
121	\r
122	// Index 16\r
123	GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {64} // Pin 20 of JP1 (GPIO_SC[64])\r
124	// Index 17\r
125	GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {64} \r
126	\r
127	// Index 18\r
128	GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {94} // Pin 22 of JP1 (GPIO_SC[94])\r
129	// Index 19\r
130	GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {94} \r
131	\r
132	// Index 20\r
133	GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {95} // Pin 24 of JP1 (GPIO_SC[95])\r
134	// Index 21\r
135	GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {95} \r
136	\r
137	// Index 22\r
138	GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {54} // Pin 26 of JP1 (GPIO_SC[54])\r
139	// Index 23\r
140	GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {54}\r
141	})\r
142	\r
143	Name(_DSD, Package() \r
144	{\r
145	ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),\r
146	Package() \r
147	{\r
148	// SPI Mapping\r
149	Package(2) { "bus-SPI-SPI0", Package() { 0 }},\r
150	\r
151	// TODO: Intel will need to provide the right value for SPI0 properties\r
49a228ca DW	152	Package(2) { "SPI0-MinClockInHz", 100000 },\r
49a228ca DW	153	Package(2) { "SPI0-MaxClockInHz", 15000000 },\r
b2499fe6 DW	154	// SupportedDataBitLengths takes a list of support data bit length\r
b2499fe6 DW	155	// Example : Package(2) { "SPI0-SupportedDataBitLengths", Package() { 8, 7, 16 }},\r
49a228ca DW	156	Package(2) { "SPI0-SupportedDataBitLengths", Package() { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 }},\r
49a228ca DW	157	// I2C Mapping\r
b2499fe6 DW	158	Package(2) { "bus-I2C-I2C5", Package() { 1 }},\r
	159	// UART Mapping\r
	160	Package(2) { "bus-UART-UART2", Package() { 2 }},\r
	161	Package(2) { "bus-UART-UART1", Package() { 9 }},\r
	162	}\r
	163	})\r
	164	}\r
	165	}\r
	166	}