projects / mirror_edk2.git / blame
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|---|---|---|
| 3cbfba02 DW |
1 | /**************************************************************************;\r |
| 2 | ;* *;\r | |
| 3 | ;* *;\r | |
| 4 | ;* Intel Corporation - ACPI Reference Code for the Sandy Bridge *;\r | |
| 5 | ;* Family of Customer Reference Boards. *;\r | |
| 6 | ;* *;\r | |
| 7 | ;* *;\r | |
| 8 | ;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *;\r | |
| 9 | ;\r | |
| 10 | ; This program and the accompanying materials are licensed and made available under\r | |
| 11 | ; the terms and conditions of the BSD License that accompanies this distribution.\r | |
| 12 | ; The full text of the license may be found at\r | |
| 13 | ; http://opensource.org/licenses/bsd-license.php.\r | |
| 14 | ;\r | |
| 15 | ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 16 | ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 17 | ;\r | |
| 18 | ;* *;\r | |
| 19 | ;* *;\r | |
| 20 | ;**************************************************************************/\r | |
| 21 | \r | |
| 22 | Name(PMBS, 0x400) // ASL alias for ACPI I/O base address.\r | |
| 23 | Name(SMIP, 0xb2) // I/O port to trigger SMI\r | |
| 24 | Name(GPBS, 0x500) // GPIO Register Block address\r | |
| 25 | Name(APCB, 0xfec00000) // Default I/O APIC(s) memory start address, 0x0FEC00000 - default, 0 - I/O APIC's disabled\r | |
| 26 | Name(APCL, 0x1000) // I/O APIC(s) memory decoded range, 0x1000 - default, 0 - I/O APIC's not decoded\r | |
| 27 | Name(PFDR, 0xfed03034) // PMC Function Disable Register\r | |
| 28 | Name(PMCB, 0xfed03000) // PMC Base Address\r | |
| 29 | Name(PCLK, 0xfed03060) // PMC Clock Control Register\r | |
| 30 | Name(PUNB, 0xfed05000) // PUNIT Base Address\r | |
| 31 | Name(IBAS, 0xfed08000) // ILB Base Address\r | |
| 32 | Name(SRCB, 0xfed1c000) // RCBA (Root Complex Base Address)\r | |
| 33 | Name(SRCL, 0x1000) // RCBA length\r | |
| 34 | Name(HPTB, 0xfed00000) // Same as HPET_BASE_ADDRESS for ASL use\r | |
| 35 | Name(PEBS, 0xe0000000) // PCIe Base\r | |
| 36 | Name(PELN, 0x10000000) //\r | |
| 37 | Name(FMBL, 0x1) // Platform Flavor - Mobile flavor for ASL code.\r | |
| 38 | Name(FDTP, 0x2) // Platform Flavor - Desktop flavor for ASL code.\r | |
| 39 | Name(SDGV, 0x1c) // UHCI Controller HOST_ALERT's bit offset within the GPE block. GPIO[0:15] corresponding to GPE[16:31]\r | |
| 40 | Name(PEHP, 0x1) // _OSC: Pci Express Native Hot Plug Control\r | |
| 41 | Name(SHPC, 0x0) // _OSC: Standard Hot Plug Controller (SHPC) Native Hot Plug control\r | |
| 42 | Name(PEPM, 0x1) // _OSC: Pci Express Native Power Management Events control\r | |
| 43 | Name(PEER, 0x1) // _OSC: Pci Express Advanced Error Reporting control\r | |
| 44 | Name(PECS, 0x1) // _OSC: Pci Express Capability Structure control\r | |
| 45 | \r |