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1 | \r |
2 | /*++\r | |
3 | \r | |
4 | Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved\r | |
5 | \r | |
6 | This program and the accompanying materials are licensed and made available under\r | |
7 | the terms and conditions of the BSD License that accompanies this distribution.\r | |
8 | The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php.\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | \r | |
15 | Module Name:\r | |
16 | \r | |
17 | VlvPolicy.h\r | |
18 | \r | |
19 | Abstract:\r | |
20 | \r | |
21 | Interface definition details between ValleyView MRC and platform drivers during PEI phase.\r | |
22 | \r | |
23 | --*/\r | |
24 | \r | |
25 | #ifndef _VLV_POLICY_PPI_H_\r | |
26 | #define _VLV_POLICY_PPI_H_\r | |
27 | \r | |
28 | //\r | |
29 | // MRC Policy provided by platform for PEI phase {7D84B2C2-22A1-4372-B12C-EBB232D3A6A3}\r | |
30 | //\r | |
31 | #define VLV_POLICY_PPI_GUID \\r | |
32 | { \\r | |
33 | 0x7D84B2C2, 0x22A1, 0x4372, 0xB1, 0x2C, 0xEB, 0xB2, 0x32, 0xD3, 0xA6, 0xA3 \\r | |
34 | }\r | |
35 | \r | |
36 | //\r | |
37 | // Extern the GUID for protocol users.\r | |
38 | //\r | |
39 | extern EFI_GUID gVlvPolicyPpiGuid;\r | |
40 | \r | |
41 | //\r | |
42 | // PPI revision number\r | |
43 | // Any backwards compatible changes to this PPI will result in an update in the revision number\r | |
44 | // Major changes will require publication of a new PPI\r | |
45 | //\r | |
46 | #define MRC_PLATFORM_POLICY_PPI_REVISION 1\r | |
47 | \r | |
48 | #ifndef MAX_SOCKETS\r | |
49 | #define MAX_SOCKETS 4\r | |
50 | #endif\r | |
51 | \r | |
52 | #define S3_TIMING_DATA_LEN 9\r | |
53 | #define S3_READ_TRAINING_DATA_LEN 16\r | |
54 | #define S3_WRITE_TRAINING_DATA_LEN 12\r | |
55 | \r | |
56 | #ifndef S3_RESTORE_DATA_LEN\r | |
57 | #define S3_RESTORE_DATA_LEN (S3_TIMING_DATA_LEN + S3_READ_TRAINING_DATA_LEN + S3_WRITE_TRAINING_DATA_LEN)\r | |
58 | #endif // S3_RESTORE_DATA_LEN\r | |
59 | #pragma pack(1)\r | |
60 | //\r | |
61 | // MRC Platform Data Structure\r | |
62 | //\r | |
63 | typedef struct {\r | |
64 | UINT8 SpdAddressTable[MAX_SOCKETS];\r | |
65 | UINT8 TSonDimmSmbusAddress[MAX_SOCKETS];\r | |
66 | \r | |
67 | UINT16 SmbusBar;\r | |
68 | UINT32 IchRcba;\r | |
69 | UINT32 WdbBaseAddress; // Write Data Buffer area (WC caching mode)\r | |
70 | UINT32 WdbRegionSize;\r | |
71 | UINT32 SmBusAddress;\r | |
72 | UINT8 UserBd;\r | |
73 | UINT8 PlatformType;\r | |
74 | UINT8 FastBoot;\r | |
75 | UINT8 DynSR;\r | |
76 | } VLV_PLATFORM_DATA;\r | |
77 | \r | |
78 | \r | |
79 | typedef struct {\r | |
80 | UINT16 MmioSize;\r | |
81 | UINT16 GttSize;\r | |
82 | UINT8 IgdDvmt50PreAlloc;\r | |
83 | UINT8 PrimaryDisplay;\r | |
84 | UINT8 PAVPMode;\r | |
85 | UINT8 ApertureSize;\r | |
86 | } GT_CONFIGURATION;\r | |
87 | \r | |
88 | typedef struct {\r | |
89 | UINT8 EccSupport;\r | |
90 | UINT16 DdrFreqLimit;\r | |
91 | UINT8 MaxTolud;\r | |
92 | } MEMORY_CONFIGURATION;\r | |
93 | \r | |
94 | \r | |
95 | //\r | |
96 | // MRC Platform Policiy PPI\r | |
97 | //\r | |
98 | typedef struct _VLV_POLICY_PPI {\r | |
99 | UINT8 Revision;\r | |
100 | VLV_PLATFORM_DATA PlatformData;\r | |
101 | GT_CONFIGURATION GtConfig;\r | |
102 | MEMORY_CONFIGURATION MemConfig;\r | |
103 | VOID *S3DataPtr; // was called MRC_PARAMS_SAVE_RESTORE\r | |
104 | UINT8 ISPEn; //ISP (IUNIT) Device Enabled\r | |
105 | UINT8 ISPPciDevConfig; //ISP (IUNIT) Device Config: 0->B0/D2/F0 for Window OS, 1->B0D3/F0 for Linux OS\r | |
106 | } VLV_POLICY_PPI;\r | |
107 | \r | |
108 | #pragma pack()\r | |
109 | \r | |
110 | #endif // _VLV_POLICY_PPI_H_\r |