projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3cbfba02 DW |
1 | \r |
| 2 | /*++\r | |
| 3 | \r | |
| 4 | Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved\r | |
| 5 | \r | |
| 7ede8060 | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 3cbfba02 DW |
7 | \r |
| 8 | \r | |
| 9 | Module Name:\r | |
| 10 | \r | |
| 11 | VlvPolicy.h\r | |
| 12 | \r | |
| 13 | Abstract:\r | |
| 14 | \r | |
| 15 | Interface definition details between ValleyView MRC and platform drivers during PEI phase.\r | |
| 16 | \r | |
| 17 | --*/\r | |
| 18 | \r | |
| 19 | #ifndef _VLV_POLICY_PPI_H_\r | |
| 20 | #define _VLV_POLICY_PPI_H_\r | |
| 21 | \r | |
| 22 | //\r | |
| 23 | // MRC Policy provided by platform for PEI phase {7D84B2C2-22A1-4372-B12C-EBB232D3A6A3}\r | |
| 24 | //\r | |
| 25 | #define VLV_POLICY_PPI_GUID \\r | |
| 26 | { \\r | |
| 27 | 0x7D84B2C2, 0x22A1, 0x4372, 0xB1, 0x2C, 0xEB, 0xB2, 0x32, 0xD3, 0xA6, 0xA3 \\r | |
| 28 | }\r | |
| 29 | \r | |
| 30 | //\r | |
| 31 | // Extern the GUID for protocol users.\r | |
| 32 | //\r | |
| 33 | extern EFI_GUID gVlvPolicyPpiGuid;\r | |
| 34 | \r | |
| 35 | //\r | |
| 36 | // PPI revision number\r | |
| 37 | // Any backwards compatible changes to this PPI will result in an update in the revision number\r | |
| 38 | // Major changes will require publication of a new PPI\r | |
| 39 | //\r | |
| 40 | #define MRC_PLATFORM_POLICY_PPI_REVISION 1\r | |
| 41 | \r | |
| 42 | #ifndef MAX_SOCKETS\r | |
| 43 | #define MAX_SOCKETS 4\r | |
| 44 | #endif\r | |
| 45 | \r | |
| 46 | #define S3_TIMING_DATA_LEN 9\r | |
| 47 | #define S3_READ_TRAINING_DATA_LEN 16\r | |
| 48 | #define S3_WRITE_TRAINING_DATA_LEN 12\r | |
| 49 | \r | |
| 50 | #ifndef S3_RESTORE_DATA_LEN\r | |
| 51 | #define S3_RESTORE_DATA_LEN (S3_TIMING_DATA_LEN + S3_READ_TRAINING_DATA_LEN + S3_WRITE_TRAINING_DATA_LEN)\r | |
| 52 | #endif // S3_RESTORE_DATA_LEN\r | |
| 53 | #pragma pack(1)\r | |
| 54 | //\r | |
| 55 | // MRC Platform Data Structure\r | |
| 56 | //\r | |
| 57 | typedef struct {\r | |
| 58 | UINT8 SpdAddressTable[MAX_SOCKETS];\r | |
| 59 | UINT8 TSonDimmSmbusAddress[MAX_SOCKETS];\r | |
| 60 | \r | |
| 61 | UINT16 SmbusBar;\r | |
| 62 | UINT32 IchRcba;\r | |
| 63 | UINT32 WdbBaseAddress; // Write Data Buffer area (WC caching mode)\r | |
| 64 | UINT32 WdbRegionSize;\r | |
| 65 | UINT32 SmBusAddress;\r | |
| 66 | UINT8 UserBd;\r | |
| 67 | UINT8 PlatformType;\r | |
| 68 | UINT8 FastBoot;\r | |
| 69 | UINT8 DynSR;\r | |
| 70 | } VLV_PLATFORM_DATA;\r | |
| 71 | \r | |
| 72 | \r | |
| 73 | typedef struct {\r | |
| 74 | UINT16 MmioSize;\r | |
| 75 | UINT16 GttSize;\r | |
| 76 | UINT8 IgdDvmt50PreAlloc;\r | |
| 77 | UINT8 PrimaryDisplay;\r | |
| 78 | UINT8 PAVPMode;\r | |
| 79 | UINT8 ApertureSize;\r | |
| 80 | } GT_CONFIGURATION;\r | |
| 81 | \r | |
| 82 | typedef struct {\r | |
| 83 | UINT8 EccSupport;\r | |
| 84 | UINT16 DdrFreqLimit;\r | |
| 85 | UINT8 MaxTolud;\r | |
| 86 | } MEMORY_CONFIGURATION;\r | |
| 87 | \r | |
| 88 | \r | |
| 89 | //\r | |
| 90 | // MRC Platform Policiy PPI\r | |
| 91 | //\r | |
| 92 | typedef struct _VLV_POLICY_PPI {\r | |
| 93 | UINT8 Revision;\r | |
| 94 | VLV_PLATFORM_DATA PlatformData;\r | |
| 95 | GT_CONFIGURATION GtConfig;\r | |
| 96 | MEMORY_CONFIGURATION MemConfig;\r | |
| 97 | VOID *S3DataPtr; // was called MRC_PARAMS_SAVE_RESTORE\r | |
| 98 | UINT8 ISPEn; //ISP (IUNIT) Device Enabled\r | |
| 99 | UINT8 ISPPciDevConfig; //ISP (IUNIT) Device Config: 0->B0/D2/F0 for Window OS, 1->B0D3/F0 for Linux OS\r | |
| 100 | } VLV_POLICY_PPI;\r | |
| 101 | \r | |
| 102 | #pragma pack()\r | |
| 103 | \r | |
| 104 | #endif // _VLV_POLICY_PPI_H_\r |