projects / mirror_edk2.git / blame
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1 | /*-----------------------------------------------------------------------------\r |
| 2 | -------------------------------------------------------------------------------\r | |
| 3 | \r | |
| 4 | \r | |
| 5 | Intel Silvermont Processor Power Management BIOS Reference Code\r | |
| 6 | \r | |
| 7 | Copyright (c) 2006 - 2014, Intel Corporation\r | |
| 8 | \r | |
| 7ede8060 | 9 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 3cbfba02 DW |
10 | \r |
| 11 | \r | |
| 12 | Filename: CPU1CST.ASL\r | |
| 13 | \r | |
| 14 | Revision: Refer to Readme\r | |
| 15 | \r | |
| 16 | Date: Refer to Readme\r | |
| 17 | \r | |
| 18 | --------------------------------------------------------------------------------\r | |
| 19 | -------------------------------------------------------------------------------\r | |
| 20 | \r | |
| 21 | This Processor Power Management BIOS Source Code is furnished under license\r | |
| 22 | and may only be used or copied in accordance with the terms of the license.\r | |
| 23 | The information in this document is furnished for informational use only, is\r | |
| 24 | subject to change without notice, and should not be construed as a commitment\r | |
| 25 | by Intel Corporation. Intel Corporation assumes no responsibility or liability\r | |
| 26 | for any errors or inaccuracies that may appear in this document or any\r | |
| 27 | software that may be provided in association with this document.\r | |
| 28 | \r | |
| 29 | Except as permitted by such license, no part of this document may be\r | |
| 30 | reproduced, stored in a retrieval system, or transmitted in any form or by\r | |
| 31 | any means without the express written consent of Intel Corporation.\r | |
| 32 | \r | |
| 33 | WARNING: You are authorized and licensed to install and use this BIOS code\r | |
| 34 | ONLY on an IST PC. This utility may damage any system that does not\r | |
| 35 | meet these requirements.\r | |
| 36 | \r | |
| 37 | An IST PC is a computer which\r | |
| 38 | (1) Is capable of seamlessly and automatically transitioning among\r | |
| 39 | multiple performance states (potentially operating at different\r | |
| 40 | efficiency ratings) based upon power source changes, END user\r | |
| 41 | preference, processor performance demand, and thermal conditions; and\r | |
| 42 | (2) Includes an Intel Pentium II processors, Intel Pentium III\r | |
| 43 | processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4\r | |
| 44 | Processor-M, Intel Pentium M Processor, or any other future Intel\r | |
| 45 | processors that incorporates the capability to transition between\r | |
| 46 | different performance states by altering some, or any combination of,\r | |
| 47 | the following processor attributes: core voltage, core frequency, bus\r | |
| 48 | frequency, number of processor cores available, or any other attribute\r | |
| 49 | that changes the efficiency (instructions/unit time-power) at which the\r | |
| 50 | processor operates.\r | |
| 51 | \r | |
| 52 | -------------------------------------------------------------------------------\r | |
| 53 | -------------------------------------------------------------------------------\r | |
| 54 | \r | |
| 55 | NOTES:\r | |
| 56 | (1) <TODO> - IF the trap range and port definitions do not match those\r | |
| 57 | specified by this reference code, this file must be modified IAW the\r | |
| 58 | individual implmentation.\r | |
| 59 | \r | |
| 60 | --------------------------------------------------------------------------------\r | |
| 61 | ------------------------------------------------------------------------------*/\r | |
| 62 | \r | |
| 63 | \r | |
| 64 | DefinitionBlock (\r | |
| 65 | "APCST.aml",\r | |
| 66 | "SSDT",\r | |
| 67 | 1,\r | |
| 68 | "PmRef",\r | |
| 69 | "ApCst",\r | |
| 70 | 0x3000\r | |
| 71 | )\r | |
| 72 | {\r | |
| 73 | External(\_PR.CPU1, DeviceObj)\r | |
| 74 | External(\_PR.CPU2, DeviceObj)\r | |
| 75 | External(\_PR.CPU3, DeviceObj)\r | |
| 76 | External(\_PR.CPU0._CST)\r | |
| 77 | \r | |
| 78 | Scope(\_PR.CPU1)\r | |
| 79 | {\r | |
| 80 | Method(_CST,0)\r | |
| 81 | {\r | |
| 82 | //\r | |
| 83 | // Return P0's _CST object.\r | |
| 84 | //\r | |
| 85 | Return(\_PR.CPU0._CST)\r | |
| 86 | }\r | |
| 87 | }\r | |
| 88 | \r | |
| 89 | Scope(\_PR.CPU2)\r | |
| 90 | {\r | |
| 91 | Method(_CST,0)\r | |
| 92 | {\r | |
| 93 | //\r | |
| 94 | // Return P0's _CST object.\r | |
| 95 | //\r | |
| 96 | Return(\_PR.CPU0._CST)\r | |
| 97 | }\r | |
| 98 | }\r | |
| 99 | \r | |
| 100 | Scope(\_PR.CPU3)\r | |
| 101 | {\r | |
| 102 | Method(_CST,0)\r | |
| 103 | {\r | |
| 104 | //\r | |
| 105 | // Return P0's _CST object.\r | |
| 106 | //\r | |
| 107 | Return(\_PR.CPU0._CST)\r | |
| 108 | }\r | |
| 109 | }\r | |
| 110 | } // End of Definition Block\r |