[mirror_edk2.git] / Vlv2DeviceRefCodePkg / ValleyView2Soc / CPU / PowerManagement / AcpiTables / Ssdt / Cpu0Cst.asl

\r
/*-----------------------------------------------------------------------------\r
-------------------------------------------------------------------------------\r
\r
\r
 Intel Silvermont Processor Power Management BIOS Reference Code\r
\r
 Copyright (c) 2006 - 2014, Intel Corporation\r
\r
  This program and the accompanying materials are licensed and made available under\r
  the terms and conditions of the BSD License that accompanies this distribution.\r
  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php.\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
\r
 Filename:    CPU0CST.ASL\r
\r
 Revision:    Refer to Readme\r
\r
 Date:        Refer to Readme\r
\r
--------------------------------------------------------------------------------\r
-------------------------------------------------------------------------------\r
\r
 This Processor Power Management BIOS Source Code is furnished under license\r
 and may only be used or copied in accordance with the terms of the license.\r
 The information in this document is furnished for informational use only, is\r
 subject to change without notice, and should not be construed as a commitment\r
 by Intel Corporation. Intel Corporation assumes no responsibility or liability\r
 for any errors or inaccuracies that may appear in this document or any\r
 software that may be provided in association with this document.\r
\r
 Except as permitted by such license, no part of this document may be\r
 reproduced, stored in a retrieval system, or transmitted in any form or by\r
 any means without the express written consent of Intel Corporation.\r
\r
 WARNING: You are authorized and licensed to install and use this BIOS code\r
 ONLY on an IST PC. This utility may damage any system that does not\r
 meet these requirements.\r
\r
    An IST PC is a computer which\r
    (1) Is capable of seamlessly and automatically transitioning among\r
    multiple performance states (potentially operating at different\r
    efficiency ratings) based upon power source changes, END user\r
    preference, processor performance demand, and thermal conditions; and\r
    (2) Includes an Intel Pentium II processors, Intel Pentium III\r
    processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4\r
    Processor-M, Intel Pentium M Processor, or any other future Intel\r
    processors that incorporates the capability to transition between\r
    different performance states by altering some, or any combination of,\r
    the following processor attributes: core voltage, core frequency, bus\r
    frequency, number of processor cores available, or any other attribute\r
    that changes the efficiency (instructions/unit time-power) at which the\r
    processor operates.\r
\r
-------------------------------------------------------------------------------\r
-------------------------------------------------------------------------------\r
\r
NOTES:\r
    (1) <TODO> - IF the trap range and port definitions do not match those\r
    specified by this reference code, this file must be modified IAW the\r
    individual implmentation.\r
\r
--------------------------------------------------------------------------------\r
------------------------------------------------------------------------------*/\r
\r
\r
DefinitionBlock (\r
    "CPU0CST.aml",\r
    "SSDT",\r
    1,\r
    "PmRef",\r
    "Cpu0Cst",\r
    0x3001\r
    )\r
{\r
    External(\_PR.CPU0, DeviceObj)\r
    External(PWRS)\r
    External(CFGD)\r
    External(PDC0)\r
\r
    Scope(\_PR.CPU0)\r
    {\r
        OperationRegion (DEB0, SystemIO, 0x80, 1)    //DBG\r
        Field (DEB0, ByteAcc,NoLock,Preserve)        //DBG\r
        { DBG8, 8,}                    //DBG\r
\r
        Method (_CST, 0)\r
        {\r
            Store(0x60,DBG8) //DBG\r
\r
            // IF CMP is supported, but independent C-States beyond C1 are\r
            // not supported; return C1 Halt and rely on BIOS based software\r
            // coordination\r
            //\r
            //   CFGD[24] = CMP support\r
            //   PDCx[4]  = 0 - OS does not support ind. C2/C3 in MP systems\r
            //\r
            // Note:  SMI will be generated when both processor enter the\r
            // Halt state.\r
            //\r
            If(LAnd(And(CFGD,0x01000000), LNot(And(PDC0,0x10))))\r
            {\r
                Store(0x61,DBG8) //DBG\r
                Return(Package() {\r
                    1,\r
                    Package()\r
                    {   // C1 halt, but with BIOS coordination\r
                        ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},\r
                        1,\r
                        157,\r
                        1000\r
                    }\r
                })\r
            }\r
\r
            // IF MWAIT extensions are supported, use them.\r
            //\r
            //  IF C6 capable/enabled AND Battery\r
            //        Report MWAIT C1, C2, C6 w/ BM_STS avoidance\r
            //  ELSE IF C4 capable/enabled AND Battery\r
            //        Report MWAIT C1, C2, C4 w/ BM_STS avoidance\r
            //  ELSE IF C3 capable/enabled\r
            //      Report MWAIT C1, C2, C3 w/ BM_STS avoidance\r
            //  ELSE IF C2 capable/enabled\r
            //        Report MWAIT C1, C2\r
            //  ELSE\r
            //        Report MWAIT C1\r
            //\r
            //   CFGD[21] = 1 - MWAIT extensions supported\r
            //   CFGD[13] = 1 - C7  Capable/Enabled\r
            //   CFGD[12] = 1 - C6S Capable/Enabled\r
            //   CFGD[11] = 1 - C6  Capable/Enabled\r
            //   CFGD[7]  = 1 - C4  Capable/Enabled\r
            //   CFGD[5]  = 1 - C3  Capable/Enabled\r
            //   PDCx[9]  = 1 - OS  supports MWAIT extensions\r
            //   PDCx[8]  = 1 - OS  supports MWAIT for C1\r
            //            (Inferred from PDCx[9] = 1.)\r
            //   PDCx[4]  = 1 - OS supports independent C2/C3 in MP systems\r
            //    or\r
            //   NOT CMP  (Inferred from previous check.)\r
            //\r
            If(LAnd(And(CFGD, 0x200000), And(PDC0,0x200)))\r
            {\r
                //\r
                // <TODO> The implementor may wish to only report C1-C2\r
                // when on AC power.  In this case, the IF clause below can\r
                // be modified to something like:\r
                //\r
                // "If(LAnd(And(CFGD,0x200), LNot(PWRS)))"\r
                //\r
                // Which uses the power state of the system (PWRS) to\r
                // determine whether to allow deepers states.\r
                //\r
                //   IF C7 supported AND on battery\r
                //    report MWAIT C1, C6, C7\r
                //\r
                //   CFGD[13] = C7  Capable/Enabled\r
                //   CFGD[11] = C6  Capable/Enabled\r
                //\r
              If(LAnd(And(CFGD,0x2000),And(CFGD,0x40000000)))\r
                {\r
                    Store(0x77,DBG8) //DBG\r
                    Return( Package()\r
                    {\r
                        3,\r
                        Package()\r
                        {   // C1, MWAIT\r
                            ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},\r
                            1,\r
                            1,\r
                            1000\r
                        },\r
                        Package()\r
                        {\r
                            // C6, MWAIT Extension with Incremental L2 Shrink\r
                            // ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)},\r
                            // C6, MWAIT Extension with No L2 Shrink\r
                            ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)},\r
                            2,\r
                            500,\r
                            10\r
                        },\r
                        Package()\r
                        {\r
                            // C7, MWAIT Extension with Full L2 Shrink\r
                            ResourceTemplate(){Register(FFixedHW, 1, 2, 0x64, 1)},\r
                            3,\r
                            1500,   //PnP setting, 1.5 ms for worst-case exit latency\r
                            10\r
                        }\r
                    })\r
                }\r
\r
\r
             If(LAnd(And(CFGD,0x2000),LNot(And(CFGD,0x40000000))))\r
                {\r
                    Store(0x67,DBG8) //DBG\r
                    Return( Package()\r
                    {\r
                        3,\r
                        Package()\r
                        {   // C1, MWAIT\r
                            ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},\r
                            1,\r
                            1,\r
                            1000\r
                        },\r
                        Package()\r
                        {\r
                            // C6, MWAIT Extension with Incremental L2 Shrink\r
                            // ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)},\r
                            // C6 = C6NS, MWAIT Extension with No L2 Shrink\r
                            ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)},\r
                            2,\r
                            500,\r
                            10\r
                        },\r
                        Package()\r
                        {\r
\r
                            ResourceTemplate(){Register(FFixedHW, 1, 2, 0x52, 1)},\r
                            3,\r
                            1500,   //PnP setting, 1.5 ms for worst-case exit latency\r
                            10\r
                        }\r
                    })\r
                }\r
\r
                If(And(CFGD,0x800)) // Setup Max C-State = C6\r
                {\r
                    Store(0x76,DBG8) //DBG\r
                    Return( Package()\r
                    {\r
                        2,\r
                        Package()\r
                        {   // C1, MWAIT\r
                            ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},\r
                            1,\r
                            1,\r
                            1000\r
                        },\r
                        Package()\r
                        {\r
                            // C6, MWAIT Extension with Incremental L2 Shrink\r
                            // ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)},\r
                            // C6, MWAIT Extension with No L2 Shrink\r
                            ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)},\r
                            2,\r
                            500,\r
                            10\r
                        }\r
                    })\r
                }\r
                //\r
                // IF no deeper C-States are supported; report MWAIT C1.\r
                //\r
                Store(0x71,DBG8) //DBG\r
                Return(Package()\r
                {\r
                    1,\r
                    Package()\r
                    {   // C1, MWAIT\r
                        ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},\r
                        1,\r
                        1,\r
                        1000\r
                    }\r
                })\r
            }\r
\r
\r
        }\r
    }\r
}\r
\r
\r
Commit	Line	Data
3cbfba02 DW	1	\r
	2	/*-----------------------------------------------------------------------------\r
	3	-------------------------------------------------------------------------------\r
	4	\r
	5	\r
	6	Intel Silvermont Processor Power Management BIOS Reference Code\r
	7	\r
	8	Copyright (c) 2006 - 2014, Intel Corporation\r
	9	\r
	10	This program and the accompanying materials are licensed and made available under\r
	11	the terms and conditions of the BSD License that accompanies this distribution.\r
	12	The full text of the license may be found at\r
	13	http://opensource.org/licenses/bsd-license.php.\r
	14	\r
	15	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	16	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	17	\r
	18	\r
	19	Filename: CPU0CST.ASL\r
	20	\r
	21	Revision: Refer to Readme\r
	22	\r
	23	Date: Refer to Readme\r
	24	\r
	25	--------------------------------------------------------------------------------\r
	26	-------------------------------------------------------------------------------\r
	27	\r
	28	This Processor Power Management BIOS Source Code is furnished under license\r
	29	and may only be used or copied in accordance with the terms of the license.\r
	30	The information in this document is furnished for informational use only, is\r
	31	subject to change without notice, and should not be construed as a commitment\r
	32	by Intel Corporation. Intel Corporation assumes no responsibility or liability\r
	33	for any errors or inaccuracies that may appear in this document or any\r
	34	software that may be provided in association with this document.\r
	35	\r
	36	Except as permitted by such license, no part of this document may be\r
	37	reproduced, stored in a retrieval system, or transmitted in any form or by\r
	38	any means without the express written consent of Intel Corporation.\r
	39	\r
	40	WARNING: You are authorized and licensed to install and use this BIOS code\r
	41	ONLY on an IST PC. This utility may damage any system that does not\r
	42	meet these requirements.\r
	43	\r
	44	An IST PC is a computer which\r
	45	(1) Is capable of seamlessly and automatically transitioning among\r
	46	multiple performance states (potentially operating at different\r
	47	efficiency ratings) based upon power source changes, END user\r
	48	preference, processor performance demand, and thermal conditions; and\r
	49	(2) Includes an Intel Pentium II processors, Intel Pentium III\r
	50	processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4\r
	51	Processor-M, Intel Pentium M Processor, or any other future Intel\r
	52	processors that incorporates the capability to transition between\r
	53	different performance states by altering some, or any combination of,\r
	54	the following processor attributes: core voltage, core frequency, bus\r
	55	frequency, number of processor cores available, or any other attribute\r
	56	that changes the efficiency (instructions/unit time-power) at which the\r
	57	processor operates.\r
	58	\r
	59	-------------------------------------------------------------------------------\r
	60	-------------------------------------------------------------------------------\r
	61	\r
	62	NOTES:\r
	63	(1) <TODO> - IF the trap range and port definitions do not match those\r
	64	specified by this reference code, this file must be modified IAW the\r
65	individual implmentation.\r
66	\r
67	--------------------------------------------------------------------------------\r
68	------------------------------------------------------------------------------*/\r
69	\r
70	\r
71	DefinitionBlock (\r
72	"CPU0CST.aml",\r
73	"SSDT",\r
74	1,\r
75	"PmRef",\r
76	"Cpu0Cst",\r
77	0x3001\r
78	)\r
79	{\r
80	External(\_PR.CPU0, DeviceObj)\r
81	External(PWRS)\r
82	External(CFGD)\r
83	External(PDC0)\r
84	\r
85	Scope(\_PR.CPU0)\r
86	{\r
87	OperationRegion (DEB0, SystemIO, 0x80, 1) //DBG\r
88	Field (DEB0, ByteAcc,NoLock,Preserve) //DBG\r
89	{ DBG8, 8,} //DBG\r
90	\r
91	Method (_CST, 0)\r
92	{\r
93	Store(0x60,DBG8) //DBG\r
94	\r
95	// IF CMP is supported, but independent C-States beyond C1 are\r
96	// not supported; return C1 Halt and rely on BIOS based software\r
97	// coordination\r
98	//\r
99	// CFGD[24] = CMP support\r
100	// PDCx[4] = 0 - OS does not support ind. C2/C3 in MP systems\r
101	//\r
102	// Note: SMI will be generated when both processor enter the\r
103	// Halt state.\r
104	//\r
105	If(LAnd(And(CFGD,0x01000000), LNot(And(PDC0,0x10))))\r
106	{\r
107	Store(0x61,DBG8) //DBG\r
108	Return(Package() {\r
109	1,\r
110	Package()\r
111	{ // C1 halt, but with BIOS coordination\r
112	ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},\r
113	1,\r
114	157,\r
115	1000\r
116	}\r
117	})\r
118	}\r
119	\r
120	// IF MWAIT extensions are supported, use them.\r
121	//\r
122	// IF C6 capable/enabled AND Battery\r
123	// Report MWAIT C1, C2, C6 w/ BM_STS avoidance\r
124	// ELSE IF C4 capable/enabled AND Battery\r
125	// Report MWAIT C1, C2, C4 w/ BM_STS avoidance\r
126	// ELSE IF C3 capable/enabled\r
127	// Report MWAIT C1, C2, C3 w/ BM_STS avoidance\r
128	// ELSE IF C2 capable/enabled\r
129	// Report MWAIT C1, C2\r
130	// ELSE\r
131	// Report MWAIT C1\r
132	//\r
133	// CFGD[21] = 1 - MWAIT extensions supported\r
134	// CFGD[13] = 1 - C7 Capable/Enabled\r
135	// CFGD[12] = 1 - C6S Capable/Enabled\r
136	// CFGD[11] = 1 - C6 Capable/Enabled\r
137	// CFGD[7] = 1 - C4 Capable/Enabled\r
138	// CFGD[5] = 1 - C3 Capable/Enabled\r
139	// PDCx[9] = 1 - OS supports MWAIT extensions\r
140	// PDCx[8] = 1 - OS supports MWAIT for C1\r
141	// (Inferred from PDCx[9] = 1.)\r
142	// PDCx[4] = 1 - OS supports independent C2/C3 in MP systems\r
143	// or\r
144	// NOT CMP (Inferred from previous check.)\r
145	//\r
146	If(LAnd(And(CFGD, 0x200000), And(PDC0,0x200)))\r
147	{\r
148	//\r
149	// <TODO> The implementor may wish to only report C1-C2\r
150	// when on AC power. In this case, the IF clause below can\r
151	// be modified to something like:\r
152	//\r
153	// "If(LAnd(And(CFGD,0x200), LNot(PWRS)))"\r
154	//\r
155	// Which uses the power state of the system (PWRS) to\r
156	// determine whether to allow deepers states.\r
157	//\r
158	// IF C7 supported AND on battery\r
159	// report MWAIT C1, C6, C7\r
160	//\r
161	// CFGD[13] = C7 Capable/Enabled\r
162	// CFGD[11] = C6 Capable/Enabled\r
163	//\r
164	If(LAnd(And(CFGD,0x2000),And(CFGD,0x40000000)))\r
165	{\r
166	Store(0x77,DBG8) //DBG\r
167	Return( Package()\r
168	{\r
169	3,\r
170	Package()\r
171	{ // C1, MWAIT\r
172	ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},\r
173	1,\r
174	1,\r
175	1000\r
176	},\r
177	Package()\r
178	{\r
179	// C6, MWAIT Extension with Incremental L2 Shrink\r
180	// ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)},\r
181	// C6, MWAIT Extension with No L2 Shrink\r
182	ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)},\r
183	2,\r
184	500,\r
185	10\r
186	},\r
187	Package()\r
188	{\r
189	// C7, MWAIT Extension with Full L2 Shrink\r
190	ResourceTemplate(){Register(FFixedHW, 1, 2, 0x64, 1)},\r
191	3,\r
192	1500, //PnP setting, 1.5 ms for worst-case exit latency\r
193	10\r
194	}\r
195	})\r
196	}\r
197	\r
198	\r
199	If(LAnd(And(CFGD,0x2000),LNot(And(CFGD,0x40000000))))\r
200	{\r
201	Store(0x67,DBG8) //DBG\r
202	Return( Package()\r
203	{\r
204	3,\r
205	Package()\r
206	{ // C1, MWAIT\r
207	ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},\r
208	1,\r
209	1,\r
210	1000\r
211	},\r
212	Package()\r
213	{\r
214	// C6, MWAIT Extension with Incremental L2 Shrink\r
215	// ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)},\r
216	// C6 = C6NS, MWAIT Extension with No L2 Shrink\r
217	ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)},\r
218	2,\r
219	500,\r
220	10\r
221	},\r
222	Package()\r
223	{\r
224	\r
225	ResourceTemplate(){Register(FFixedHW, 1, 2, 0x52, 1)},\r
226	3,\r
227	1500, //PnP setting, 1.5 ms for worst-case exit latency\r
228	10\r
229	}\r
230	})\r
231	}\r
232	\r
233	If(And(CFGD,0x800)) // Setup Max C-State = C6\r
234	{\r
235	Store(0x76,DBG8) //DBG\r
236	Return( Package()\r
237	{\r
238	2,\r
239	Package()\r
240	{ // C1, MWAIT\r
241	ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},\r
242	1,\r
243	1,\r
244	1000\r
245	},\r
246	Package()\r
247	{\r
248	// C6, MWAIT Extension with Incremental L2 Shrink\r
249	// ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)},\r
250	// C6, MWAIT Extension with No L2 Shrink\r
251	ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)},\r
252	2,\r
253	500,\r
254	10\r
255	}\r
256	})\r
257	}\r
258	//\r
259	// IF no deeper C-States are supported; report MWAIT C1.\r
260	//\r
261	Store(0x71,DBG8) //DBG\r
262	Return(Package()\r
263	{\r
264	1,\r
265	Package()\r
266	{ // C1, MWAIT\r
267	ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},\r
268	1,\r
269	1,\r
270	1000\r
271	}\r
272	})\r
273	}\r
274	\r
275	\r
276	}\r
277	}\r
278	}\r
279	\r
280	\r