projects / mirror_edk2.git / blame
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1 | /*-----------------------------------------------------------------------------\r |
| 2 | -------------------------------------------------------------------------------\r | |
| 3 | \r | |
| 4 | \r | |
| 5 | Intel Silvermont Processor Power Management BIOS Reference Code\r | |
| 6 | \r | |
| 7 | Copyright (c) 2006 - 2014, Intel Corporation\r | |
| 8 | \r | |
| 7ede8060 | 9 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 3cbfba02 DW |
10 | \r |
| 11 | \r | |
| 12 | Filename: CPU0TST.ASL\r | |
| 13 | \r | |
| 14 | Revision: Refer to Readme\r | |
| 15 | \r | |
| 16 | Date: Refer to Readme\r | |
| 17 | \r | |
| 18 | --------------------------------------------------------------------------------\r | |
| 19 | -------------------------------------------------------------------------------\r | |
| 20 | \r | |
| 21 | This Processor Power Management BIOS Source Code is furnished under license\r | |
| 22 | and may only be used or copied in accordance with the terms of the license.\r | |
| 23 | The information in this document is furnished for informational use only, is\r | |
| 24 | subject to change without notice, and should not be construed as a commitment\r | |
| 25 | by Intel Corporation. Intel Corporation assumes no responsibility or liability\r | |
| 26 | for any errors or inaccuracies that may appear in this document or any\r | |
| 27 | software that may be provided in association with this document.\r | |
| 28 | \r | |
| 29 | Except as permitted by such license, no part of this document may be\r | |
| 30 | reproduced, stored in a retrieval system, or transmitted in any form or by\r | |
| 31 | any means without the express written consent of Intel Corporation.\r | |
| 32 | \r | |
| 33 | WARNING: You are authorized and licensed to install and use this BIOS code\r | |
| 34 | ONLY on an IST PC. This utility may damage any system that does not\r | |
| 35 | meet these requirements.\r | |
| 36 | \r | |
| 37 | An IST PC is a computer which\r | |
| 38 | (1) Is capable of seamlessly and automatically transitioning among\r | |
| 39 | multiple performance states (potentially operating at different\r | |
| 40 | efficiency ratings) based upon power source changes, end user\r | |
| 41 | preference, processor performance demand, and thermal conditions; and\r | |
| 42 | (2) Includes an Intel Pentium II processors, Intel Pentium III\r | |
| 43 | processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4\r | |
| 44 | Processor-M, Intel Pentium M Processor, or any other future Intel\r | |
| 45 | processors that incorporates the capability to transition between\r | |
| 46 | different performance states by altering some, or any combination of,\r | |
| 47 | the following processor attributes: core voltage, core frequency, bus\r | |
| 48 | frequency, number of processor cores available, or any other attribute\r | |
| 49 | that changes the efficiency (instructions/unit time-power) at which the\r | |
| 50 | processor operates.\r | |
| 51 | \r | |
| 52 | -------------------------------------------------------------------------------\r | |
| 53 | -------------------------------------------------------------------------------\r | |
| 54 | \r | |
| 55 | NOTES:\r | |
| 56 | (1) <TODO> - IF the trap range and port definitions do not match those\r | |
| 57 | specified by this reference code, this file must be modified IAW the\r | |
| 58 | individual implmentation.\r | |
| 59 | \r | |
| 60 | --------------------------------------------------------------------------------\r | |
| 61 | ------------------------------------------------------------------------------*/\r | |
| 62 | \r | |
| 63 | DefinitionBlock(\r | |
| 64 | "CPU0TST.aml",\r | |
| 65 | "SSDT",\r | |
| 66 | 0x01,\r | |
| 67 | "PmRef",\r | |
| 68 | "Cpu0Tst",\r | |
| 69 | 0x3000\r | |
| 70 | )\r | |
| 71 | {\r | |
| 72 | External(\_PR.CPU0, DeviceObj)\r | |
| 73 | External(PDC0)\r | |
| 74 | External(CFGD)\r | |
| 75 | External(_PSS)\r | |
| 76 | \r | |
| 77 | Scope(\_PR.CPU0)\r | |
| 78 | {\r | |
| 79 | Name(_TPC, 0) // All T-States are available\r | |
| 80 | \r | |
| 81 | //\r | |
| 82 | // T-State Control/Status interface\r | |
| 83 | //\r | |
| 84 | Method(_PTC, 0)\r | |
| 85 | {\r | |
| 86 | //\r | |
| 87 | // IF OSPM is capable of direct access to MSR\r | |
| 88 | // Report MSR interface\r | |
| 89 | // ELSE\r | |
| 90 | // Report I/O interface\r | |
| 91 | //\r | |
| 92 | // PDCx[2] = OSPM is capable of direct access to On\r | |
| 93 | // Demand throttling MSR\r | |
| 94 | //\r | |
| 95 | If(And(PDC0, 0x0004)) {\r | |
| 96 | Return(Package() {\r | |
| 97 | ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},\r | |
| 98 | ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}\r | |
| 99 | })\r | |
| 100 | }\r | |
| 101 | \r | |
| 102 | }\r | |
| 103 | \r | |
| 104 | // _TSS package for I/O port based T-State control\r | |
| 105 | // "Power" fields are replaced with real values by the first\r | |
| 106 | // call of _TSS method.\r | |
| 107 | //\r | |
| 108 | Name(TSSI, Package() {\r | |
| 109 | Package(){100, 1000, 0, 0x00, 0},\r | |
| 110 | Package(){ 88, 875, 0, 0x0F, 0},\r | |
| 111 | Package(){ 75, 750, 0, 0x0E, 0},\r | |
| 112 | Package(){ 63, 625, 0, 0x0D, 0},\r | |
| 113 | Package(){ 50, 500, 0, 0x0C, 0},\r | |
| 114 | Package(){ 38, 375, 0, 0x0B, 0},\r | |
| 115 | Package(){ 25, 250, 0, 0x0A, 0},\r | |
| 116 | Package(){ 13, 125, 0, 0x09, 0}\r | |
| 117 | })\r | |
| 118 | \r | |
| 119 | // _TSS package for MSR based T-State control\r | |
| 120 | // "Power" fields are replaced with real values by the first\r | |
| 121 | // call of _TSS method.\r | |
| 122 | //\r | |
| 123 | Name(TSSM, Package() {\r | |
| 124 | Package(){100, 1000, 0, 0x00, 0},\r | |
| 125 | Package(){ 88, 875, 0, 0x1E, 0},\r | |
| 126 | Package(){ 75, 750, 0, 0x1C, 0},\r | |
| 127 | Package(){ 63, 625, 0, 0x1A, 0},\r | |
| 128 | Package(){ 50, 500, 0, 0x18, 0},\r | |
| 129 | Package(){ 38, 375, 0, 0x16, 0},\r | |
| 130 | Package(){ 25, 250, 0, 0x14, 0},\r | |
| 131 | Package(){ 13, 125, 0, 0x12, 0}\r | |
| 132 | })\r | |
| 133 | \r | |
| 134 | Name(TSSF, 0) // Flag for TSSI/TSSM initialization\r | |
| 135 | \r | |
| 136 | Method(_TSS, 0)\r | |
| 137 | {\r | |
| 138 | // Update "Power" fields of TSSI/TSSM with the LFM\r | |
| 139 | // power data IF _PSS is available\r | |
| 140 | //\r | |
| 141 | IF (LAnd(LNot(TSSF),CondRefOf(_PSS)))\r | |
| 142 | {\r | |
| 143 | Store(_PSS, Local0)\r | |
| 144 | Store(SizeOf(Local0), Local1) // _PSS size\r | |
| 145 | Decrement(Local1) // Index of LFM\r | |
| 146 | Store(DerefOf(Index(DerefOf(Index(Local0,Local1)),1)), Local2) // LFM Power\r | |
| 147 | \r | |
| 148 | Store(0, Local3)\r | |
| 149 | While(LLess(Local3, SizeOf(TSSI)))\r | |
| 150 | {\r | |
| 151 | Store(Divide(Multiply(Local2, Subtract(8, Local3)), 8),\r | |
| 152 | Local4) // Power for this TSSI/TSSM entry\r | |
| 153 | Store(Local4,Index(DerefOf(Index(TSSI,Local3)),1))\r | |
| 154 | Store(Local4,Index(DerefOf(Index(TSSM,Local3)),1))\r | |
| 155 | Increment(Local3)\r | |
| 156 | }\r | |
| 157 | Store(Ones, TSSF) // TSSI/TSSM are updated\r | |
| 158 | }\r | |
| 159 | //\r | |
| 160 | // IF OSPM is capable of direct access to MSR\r | |
| 161 | // Report TSSM\r | |
| 162 | // ELSE\r | |
| 163 | // Report TSSI\r | |
| 164 | //\r | |
| 165 | If(And(PDC0, 0x0004))\r | |
| 166 | {\r | |
| 167 | Return(TSSM)\r | |
| 168 | }\r | |
| 169 | Return(TSSI)\r | |
| 170 | }\r | |
| 171 | \r | |
| 172 | Method(_TDL, 0)\r | |
| 173 | {\r | |
| 174 | Store ("Cpu0: _TDL Called", Debug)\r | |
| 175 | Name ( LFMI, 0)\r | |
| 176 | Store (SizeOf(TSSM), LFMI)\r | |
| 177 | Decrement(LFMI) // Index of LFM entry in TSSM\r | |
| 178 | Return(LFMI)\r | |
| 179 | }\r | |
| 180 | \r | |
| 181 | //\r | |
| 182 | // T-State Dependency\r | |
| 183 | //\r | |
| 184 | Method(_TSD, 0)\r | |
| 185 | {\r | |
| 186 | //\r | |
| 187 | // IF four cores are supported/enabled && !(direct access to MSR)\r | |
| 188 | // Report 4 processors and SW_ANY as the coordination type\r | |
| 189 | // ELSE IF two cores are supported/enabled && !(direct access to MSR)\r | |
| 190 | // Report 2 processors and SW_ANY as the coordination type\r | |
| 191 | // ELSE\r | |
| 192 | // Report 1 processor and SW_ALL as the coordination type\r | |
| 193 | //\r | |
| 194 | // CFGD[23] = Four cores enabled\r | |
| 195 | // CFGD[24] = Two or more cores enabled\r | |
| 196 | // PDCx[2] = OSPM is capable of direct access to On\r | |
| 197 | // Demand throttling MSR\r | |
| 198 | //\r | |
| 199 | If(LAnd(And(CFGD,0x0800000),LNot(And(PDC0,4))))\r | |
| 200 | {\r | |
| 201 | Return(Package(){ // SW_ANY\r | |
| 202 | Package(){\r | |
| 203 | 5, // # entries.\r | |
| 204 | 0, // Revision.\r | |
| 205 | 0, // Domain #.\r | |
| 206 | 0xFD, // Coord Type- SW_ANY\r | |
| 207 | 4 // # processors.\r | |
| 208 | }\r | |
| 209 | })\r | |
| 210 | }\r | |
| 211 | If(LAnd(And(CFGD,0x1000000),LNot(And(PDC0,4))))\r | |
| 212 | {\r | |
| 213 | Return(Package(){ // SW_ANY\r | |
| 214 | Package(){\r | |
| 215 | 5, // # entries.\r | |
| 216 | 0, // Revision.\r | |
| 217 | 0, // Domain #.\r | |
| 218 | 0xFD, // Coord Type- SW_ANY\r | |
| 219 | 2 // # processors.\r | |
| 220 | }\r | |
| 221 | })\r | |
| 222 | }\r | |
| 223 | Return(Package(){ // SW_ALL\r | |
| 224 | Package(){\r | |
| 225 | 5, // # entries.\r | |
| 226 | 0, // Revision.\r | |
| 227 | 0, // Domain #.\r | |
| 228 | 0xFC, // Coord Type- SW_ALL\r | |
| 229 | 1 // # processors.\r | |
| 230 | }\r | |
| 231 | })\r | |
| 232 | }\r | |
| 233 | }\r | |
| 234 | } // End of Definition Block\r | |
| 235 | \r |