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[mirror_edk2.git] / Vlv2DeviceRefCodePkg / ValleyView2Soc / NorthCluster / Include / PlatformBaseAddresses.h
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1/*++\r
2\r
3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r
4\r
5 This program and the accompanying materials are licensed and made available under\r
6 the terms and conditions of the BSD License that accompanies this distribution.\r
7 The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php.\r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13\r
14\r
15\r
16\r
17Module Name:\r
18\r
19 PlatformBaseAddresses.h\r
20\r
21Abstract:\r
22\r
23\r
24\r
25Revision History\r
26\r
27++*/\r
28\r
29\r
30#ifndef _PLATFORM_BASE_ADDRESSES_H\r
31#define _PLATFORM_BASE_ADDRESSES_H\r
32\r
33//\r
34// Define some fixed platform device location information\r
35//\r
36\r
37//\r
38// Define platform base\r
39//\r
40\r
41//\r
42// SIO\r
43//\r
44#define SIO_BASE_ADDRESS 0x0680\r
45#define SIO_MONITORING_BASE_ADDRESS 0x0290\r
46#define SIO_BASE_MASK 0xFFF0\r
47#define WINDBOND_ECIR_BASE_ADDRESS 0x0810\r
48#define SIO_MAILBOX_BASE_ADDRESS 0x0360 // Used by EC controller\r
49#define SIO_EC_CHANNEL2 0x62 // Used by EC controller for offset 0x62 and 0x66\r
50\r
51\r
52//\r
53// South Cluster\r
54//\r
55#define ACPI_BASE_ADDRESS 0x0400\r
56#define GPIO_BASE_ADDRESS 0x0500\r
57#define SMBUS_BUS_DEV_FUNC 0x1F0300\r
58#define SMBUS_BASE_ADDRESS 0xEFA0 // SMBus IO Base Address\r
59#define SPI_BASE_ADDRESS 0xFED01000 // SPI Memory Base Address\r
60#define PMC_BASE_ADDRESS 0xFED03000 // PMC Memory Base Address\r
61#define SMBM_BASE_ADDRESS 0xFED04000 // SMBus Memory Base Address\r
62#define IO_BASE_ADDRESS 0xFED0C000 // IO Memory Base Address\r
63#define ILB_BASE_ADDRESS 0xFED08000 // ILB Memory Base Address\r
64#define HPET_BASE_ADDRESS 0xFED00000 // HPET Base Address\r
65#define RCBA_BASE_ADDRESS 0xFED1C000 // Root Complex Base Address\r
66#define MPHY_BASE_ADDRESS 0xFEF00000 // MPHY Memory Base Address\r
67#define PUNIT_BASE_ADDRESS 0xFED05000 // PUnit Memory Base Address\r
68\r
69//\r
70// GPIO GROUP OFFSET\r
71//\r
72#define GPIO_SCORE_OFFSET 0x0000\r
73#define GPIO_NCORE_OFFSET 0x1000\r
74#define GPIO_SSUS_OFFSET 0x2000\r
75\r
76//\r
77// MCH/CPU\r
78//\r
79#define DMI_BASE_ADDRESS 0xFED18000 // 4K, similar to IIO_RCBA // modify from bearlake -- cchew10\r
80#define EP_BASE_ADDRESS 0xFED19000\r
81#define MC_MMIO_BASE 0xFED14000 // Base Address for MMIO registers\r
82\r
83//\r
84// TPM\r
85//\r
86#define TPM_BASE_ADDRESS 0xFED40000 // Base address for TPM\r
87\r
88//\r
89// Local and I/O APIC addresses.\r
90//\r
91#define IO_APIC_ADDRESS 0xFEC00000\r
92#define IIO_IOAPIC_ADDRESS 0xFEC90000\r
93#define LOCAL_APIC_ADDRESS 0xFEE00000\r
94\r
95\r
96#endif\r
97\r
98\r