projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3cbfba02 DW |
1 | /*++\r |
| 2 | \r | |
| 3 | Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r | |
| 4 | \r | |
| 7ede8060 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 3cbfba02 DW |
6 | \r |
| 7 | \r | |
| 8 | \r | |
| 9 | \r | |
| 10 | \r | |
| 11 | Module Name:\r | |
| 12 | \r | |
| 13 | PlatformBaseAddresses.h\r | |
| 14 | \r | |
| 15 | Abstract:\r | |
| 16 | \r | |
| 17 | \r | |
| 18 | \r | |
| 19 | Revision History\r | |
| 20 | \r | |
| 21 | ++*/\r | |
| 22 | \r | |
| 23 | \r | |
| 24 | #ifndef _PLATFORM_BASE_ADDRESSES_H\r | |
| 25 | #define _PLATFORM_BASE_ADDRESSES_H\r | |
| 26 | \r | |
| 27 | //\r | |
| 28 | // Define some fixed platform device location information\r | |
| 29 | //\r | |
| 30 | \r | |
| 31 | //\r | |
| 32 | // Define platform base\r | |
| 33 | //\r | |
| 34 | \r | |
| 35 | //\r | |
| 36 | // SIO\r | |
| 37 | //\r | |
| 38 | #define SIO_BASE_ADDRESS 0x0680\r | |
| 39 | #define SIO_MONITORING_BASE_ADDRESS 0x0290\r | |
| 40 | #define SIO_BASE_MASK 0xFFF0\r | |
| 41 | #define WINDBOND_ECIR_BASE_ADDRESS 0x0810\r | |
| 42 | #define SIO_MAILBOX_BASE_ADDRESS 0x0360 // Used by EC controller\r | |
| 43 | #define SIO_EC_CHANNEL2 0x62 // Used by EC controller for offset 0x62 and 0x66\r | |
| 44 | \r | |
| 45 | \r | |
| 46 | //\r | |
| 47 | // South Cluster\r | |
| 48 | //\r | |
| 49 | #define ACPI_BASE_ADDRESS 0x0400\r | |
| 50 | #define GPIO_BASE_ADDRESS 0x0500\r | |
| 51 | #define SMBUS_BUS_DEV_FUNC 0x1F0300\r | |
| 52 | #define SMBUS_BASE_ADDRESS 0xEFA0 // SMBus IO Base Address\r | |
| 53 | #define SPI_BASE_ADDRESS 0xFED01000 // SPI Memory Base Address\r | |
| 54 | #define PMC_BASE_ADDRESS 0xFED03000 // PMC Memory Base Address\r | |
| 55 | #define SMBM_BASE_ADDRESS 0xFED04000 // SMBus Memory Base Address\r | |
| 56 | #define IO_BASE_ADDRESS 0xFED0C000 // IO Memory Base Address\r | |
| 57 | #define ILB_BASE_ADDRESS 0xFED08000 // ILB Memory Base Address\r | |
| 58 | #define HPET_BASE_ADDRESS 0xFED00000 // HPET Base Address\r | |
| 59 | #define RCBA_BASE_ADDRESS 0xFED1C000 // Root Complex Base Address\r | |
| 60 | #define MPHY_BASE_ADDRESS 0xFEF00000 // MPHY Memory Base Address\r | |
| 61 | #define PUNIT_BASE_ADDRESS 0xFED05000 // PUnit Memory Base Address\r | |
| 62 | \r | |
| 63 | //\r | |
| 64 | // GPIO GROUP OFFSET\r | |
| 65 | //\r | |
| 66 | #define GPIO_SCORE_OFFSET 0x0000\r | |
| 67 | #define GPIO_NCORE_OFFSET 0x1000\r | |
| 68 | #define GPIO_SSUS_OFFSET 0x2000\r | |
| 69 | \r | |
| 70 | //\r | |
| 71 | // MCH/CPU\r | |
| 72 | //\r | |
| 73 | #define DMI_BASE_ADDRESS 0xFED18000 // 4K, similar to IIO_RCBA // modify from bearlake -- cchew10\r | |
| 74 | #define EP_BASE_ADDRESS 0xFED19000\r | |
| 75 | #define MC_MMIO_BASE 0xFED14000 // Base Address for MMIO registers\r | |
| 76 | \r | |
| 77 | //\r | |
| 78 | // TPM\r | |
| 79 | //\r | |
| 80 | #define TPM_BASE_ADDRESS 0xFED40000 // Base address for TPM\r | |
| 81 | \r | |
| 82 | //\r | |
| 83 | // Local and I/O APIC addresses.\r | |
| 84 | //\r | |
| 85 | #define IO_APIC_ADDRESS 0xFEC00000\r | |
| 86 | #define IIO_IOAPIC_ADDRESS 0xFEC90000\r | |
| 87 | #define LOCAL_APIC_ADDRESS 0xFEE00000\r | |
| 88 | \r | |
| 89 | \r | |
| 90 | #endif\r | |
| 91 | \r | |
| 92 | \r |