Vlv2TbltDevicePkg/Vlv2DeviceRefCodePkg:
[mirror_edk2.git] / Vlv2DeviceRefCodePkg / ValleyView2Soc / NorthCluster / Include / VlvCommonDefinitions.h
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1\r
2/*++\r
3\r
4Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r
5\r
6 This program and the accompanying materials are licensed and made available under\r
7 the terms and conditions of the BSD License that accompanies this distribution.\r
8 The full text of the license may be found at\r
9 http://opensource.org/licenses/bsd-license.php.\r
10\r
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14\r
15\r
16Module Name:\r
17\r
18 VlvCommonDefinitions.h\r
19\r
20Abstract:\r
21\r
22 Macros to simplify and abstract the interface to PCI configuration.\r
23\r
24--*/\r
25\r
26///\r
27/// PCI CONFIGURATION MAP REGISTER OFFSETS\r
28///\r
29#ifndef PCI_VID\r
30#define PCI_VID 0x0000 ///< Vendor ID Register\r
31#define PCI_DID 0x0002 ///< Device ID Register\r
32#define PCI_CMD 0x0004 ///< PCI Command Register\r
33#define PCI_STS 0x0006 ///< PCI Status Register\r
34#define PCI_RID 0x0008 ///< Revision ID Register\r
35#define PCI_IFT 0x0009 ///< Interface Type\r
36#define PCI_SCC 0x000A ///< Sub Class Code Register\r
37#define PCI_BCC 0x000B ///< Base Class Code Register\r
38#define PCI_CLS 0x000C ///< Cache Line Size\r
39#define PCI_PMLT 0x000D ///< Primary Master Latency Timer\r
40#define PCI_HDR 0x000E ///< Header Type Register\r
41#define PCI_BIST 0x000F ///< Built in Self Test Register\r
42#define PCI_BAR0 0x0010 ///< Base Address Register 0\r
43#define PCI_BAR1 0x0014 ///< Base Address Register 1\r
44#define PCI_BAR2 0x0018 ///< Base Address Register 2\r
45#define PCI_PBUS 0x0018 ///< Primary Bus Number Register\r
46#define PCI_SBUS 0x0019 ///< Secondary Bus Number Register\r
47#define PCI_SUBUS 0x001A ///< Subordinate Bus Number Register\r
48#define PCI_SMLT 0x001B ///< Secondary Master Latency Timer\r
49#define PCI_BAR3 0x001C ///< Base Address Register 3\r
50#define PCI_IOBASE 0x001C ///< I/O base Register\r
51#define PCI_IOLIMIT 0x001D ///< I/O Limit Register\r
52#define PCI_SECSTATUS 0x001E ///< Secondary Status Register\r
53#define PCI_BAR4 0x0020 ///< Base Address Register 4\r
54#define PCI_MEMBASE 0x0020 ///< Memory Base Register\r
55#define PCI_MEMLIMIT 0x0022 ///< Memory Limit Register\r
56#define PCI_BAR5 0x0024 ///< Base Address Register 5\r
57#define PCI_PRE_MEMBASE 0x0024 ///< Prefetchable memory Base register\r
58#define PCI_PRE_MEMLIMIT 0x0026 ///< Prefetchable memory Limit register\r
59#define PCI_PRE_MEMBASE_U 0x0028 ///< Prefetchable memory base upper 32 bits\r
60#define PCI_PRE_MEMLIMIT_U 0x002C ///< Prefetchable memory limit upper 32 bits\r
61#define PCI_SVID 0x002C ///< Subsystem Vendor ID\r
62#define PCI_SID 0x002E ///< Subsystem ID\r
63#define PCI_IOBASE_U 0x0030 ///< I/O base Upper Register\r
64#define PCI_IOLIMIT_U 0x0032 ///< I/O Limit Upper Register\r
65#define PCI_CAPP 0x0034 ///< Capabilities Pointer\r
66#define PCI_EROM 0x0038 ///< Expansion ROM Base Address\r
67#define PCI_INTLINE 0x003C ///< Interrupt Line Register\r
68#define PCI_INTPIN 0x003D ///< Interrupt Pin Register\r
69#define PCI_MAXGNT 0x003E ///< Max Grant Register\r
70#define PCI_BRIDGE_CNTL 0x003E ///< Bridge Control Register\r
71#define PCI_MAXLAT 0x003F ///< Max Latency Register\r
72#endif\r
73//\r
74// Bit Difinitions\r
75//\r
76#ifndef BIT0\r
77#define BIT0 0x0001\r
78#define BIT1 0x0002\r
79#define BIT2 0x0004\r
80#define BIT3 0x0008\r
81#define BIT4 0x0010\r
82#define BIT5 0x0020\r
83#define BIT6 0x0040\r
84#define BIT7 0x0080\r
85#define BIT8 0x0100\r
86#define BIT9 0x0200\r
87#define BIT10 0x0400\r
88#define BIT11 0x0800\r
89#define BIT12 0x1000\r
90#define BIT13 0x2000\r
91#define BIT14 0x4000\r
92#define BIT15 0x8000\r
93#define BIT16 0x00010000\r
94#define BIT17 0x00020000\r
95#define BIT18 0x00040000\r
96#define BIT19 0x00080000\r
97#define BIT20 0x00100000\r
98#define BIT21 0x00200000\r
99#define BIT22 0x00400000\r
100#define BIT23 0x00800000\r
101#define BIT24 0x01000000\r
102#define BIT25 0x02000000\r
103#define BIT26 0x04000000\r
104#define BIT27 0x08000000\r
105#define BIT28 0x10000000\r
106#define BIT29 0x20000000\r
107#define BIT30 0x40000000\r
108#define BIT31 0x80000000\r
109#endif\r
110\r
111#ifndef _PCIACCESS_H_INCLUDED_\r
112#define _PCIACCESS_H_INCLUDED_\r
113#ifndef PCI_EXPRESS_BASE_ADDRESS\r
114 #define PCI_EXPRESS_BASE_ADDRESS 0xE0000000\r
115#endif\r
116\r
117#ifndef MmPciAddress\r
118#define MmPciAddress( Segment, Bus, Device, Function, Register ) \\r
119 ( (UINTN)PCI_EXPRESS_BASE_ADDRESS + \\r
120 (UINTN)(Bus << 20) + \\r
121 (UINTN)(Device << 15) + \\r
122 (UINTN)(Function << 12) + \\r
123 (UINTN)(Register) \\r
124 )\r
125#endif\r
126\r
127//\r
128// UINT64\r
129//\r
130#define MmPci64Ptr( Segment, Bus, Device, Function, Register ) \\r
131 ( (volatile UINT64 *)MmPciAddress( Segment, Bus, Device, Function, Register ) )\r
132\r
133#define MmPci64( Segment, Bus, Device, Function, Register ) \\r
134 *MmPci64Ptr( Segment, Bus, Device, Function, Register )\r
135\r
136#define MmPci64Or( Segment, Bus, Device, Function, Register, OrData ) \\r
137 MmPci64( Segment, Bus, Device, Function, Register ) = \\r
138 (UINT64) ( \\r
139 MmPci64( Segment, Bus, Device, Function, Register ) | \\r
140 (UINT64)(OrData) \\r
141 )\r
142\r
143#define MmPci64And( Segment, Bus, Device, Function, Register, AndData ) \\r
144 MmPci64( Segment, Bus, Device, Function, Register ) = \\r
145 (UINT64) ( \\r
146 MmPci64( Segment, Bus, Device, Function, Register ) & \\r
147 (UINT64)(AndData) \\r
148 )\r
149\r
150#define MmPci64AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \\r
151 MmPci64( Segment, Bus, Device, Function, Register ) = \\r
152 (UINT64) ( \\r
153 ( MmPci64( Segment, Bus, Device, Function, Register ) & \\r
154 (UINT64)(AndData) \\r
155 ) | \\r
156 (UINT64)(OrData) \\r
157 )\r
158\r
159//\r
160// UINT32\r
161//\r
162\r
163#define MmPci32Ptr( Segment, Bus, Device, Function, Register ) \\r
164 ( (volatile UINT32 *) MmPciAddress( Segment, Bus, Device, Function, Register ) )\r
165\r
166#define MmPci32( Segment, Bus, Device, Function, Register ) \\r
167 *MmPci32Ptr( Segment, Bus, Device, Function, Register )\r
168\r
169#define MmPci32Or( Segment, Bus, Device, Function, Register, OrData ) \\r
170 MmPci32( Segment, Bus, Device, Function, Register ) = \\r
171 (UINT32) ( \\r
172 MmPci32( Segment, Bus, Device, Function, Register ) | \\r
173 (UINT32)(OrData) \\r
174 )\r
175\r
176#define MmPci32And( Segment, Bus, Device, Function, Register, AndData ) \\r
177 MmPci32( Segment, Bus, Device, Function, Register ) = \\r
178 (UINT32) ( \\r
179 MmPci32( Segment, Bus, Device, Function, Register ) & \\r
180 (UINT32)(AndData) \\r
181 )\r
182\r
183#define MmPci32AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \\r
184 MmPci32( Segment, Bus, Device, Function, Register ) = \\r
185 (UINT32) ( \\r
186 ( MmPci32( Segment, Bus, Device, Function, Register ) & \\r
187 (UINT32)(AndData) \\r
188 ) | \\r
189 (UINT32)(OrData) \\r
190 )\r
191\r
192//\r
193// UINT16\r
194//\r
195\r
196#define MmPci16Ptr( Segment, Bus, Device, Function, Register ) \\r
197 ( (volatile UINT16 *)MmPciAddress( Segment, Bus, Device, Function, Register ) )\r
198\r
199#define MmPci16( Segment, Bus, Device, Function, Register ) \\r
200 *MmPci16Ptr( Segment, Bus, Device, Function, Register )\r
201\r
202#define MmPci16Or( Segment, Bus, Device, Function, Register, OrData ) \\r
203 MmPci16( Segment, Bus, Device, Function, Register ) = \\r
204 (UINT16) ( \\r
205 MmPci16( Segment, Bus, Device, Function, Register ) | \\r
206 (UINT16)(OrData) \\r
207 )\r
208\r
209#define MmPci16And( Segment, Bus, Device, Function, Register, AndData ) \\r
210 MmPci16( Segment, Bus, Device, Function, Register ) = \\r
211 (UINT16) ( \\r
212 MmPci16( Segment, Bus, Device, Function, Register ) & \\r
213 (UINT16)(AndData) \\r
214 )\r
215\r
216#define MmPci16AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \\r
217 MmPci16( Segment, Bus, Device, Function, Register ) = \\r
218 (UINT16) ( \\r
219 ( MmPci16( Segment, Bus, Device, Function, Register ) & \\r
220 (UINT16)(AndData) \\r
221 ) | \\r
222 (UINT16)(OrData) \\r
223 )\r
224\r
225//\r
226// UINT8\r
227//\r
228\r
229#define MmPci8Ptr( Segment, Bus, Device, Function, Register ) \\r
230 ( (volatile UINT8 *)MmPciAddress( Segment, Bus, Device, Function, Register ) )\r
231\r
232#define MmPci8( Segment, Bus, Device, Function, Register ) \\r
233 *MmPci8Ptr( Segment, Bus, Device, Function, Register )\r
234\r
235#define MmPci8Or( Segment, Bus, Device, Function, Register, OrData ) \\r
236 MmPci8( Segment, Bus, Device, Function, Register ) = \\r
237 (UINT8) ( \\r
238 MmPci8( Segment, Bus, Device, Function, Register ) | \\r
239 (UINT8)(OrData) \\r
240 )\r
241\r
242#define MmPci8And( Segment, Bus, Device, Function, Register, AndData ) \\r
243 MmPci8( Segment, Bus, Device, Function, Register ) = \\r
244 (UINT8) ( \\r
245 MmPci8( Segment, Bus, Device, Function, Register ) & \\r
246 (UINT8)(AndData) \\r
247 )\r
248\r
249#define MmPci8AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \\r
250 MmPci8( Segment, Bus, Device, Function, Register ) = \\r
251 (UINT8) ( \\r
252 ( MmPci8( Segment, Bus, Device, Function, Register ) & \\r
253 (UINT8)(AndData) \\r
254 ) | \\r
255 (UINT8)(OrData) \\r
256 )\r
257\r
258#endif\r