projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3cbfba02 DW |
1 | /*++\r |
| 2 | \r | |
| 3 | Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r | |
| 4 | \r | |
| 7ede8060 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 3cbfba02 DW |
6 | \r |
| 7 | \r | |
| 8 | --*/\r | |
| 9 | \r | |
| 10 | \r | |
| 11 | /*++\r | |
| 12 | Module Name:\r | |
| 13 | \r | |
| 14 | SDCard.h\r | |
| 15 | \r | |
| 16 | Abstract:\r | |
| 17 | \r | |
| 18 | Header file for Industry SD Card 2.0 spec.\r | |
| 19 | \r | |
| 20 | --*/\r | |
| 21 | \r | |
| 22 | #ifndef _SD_CARD_H\r | |
| 23 | #define _SD_CARD_H\r | |
| 24 | \r | |
| 25 | #include "Mmc.h"\r | |
| 26 | \r | |
| 27 | #pragma pack(1)\r | |
| 28 | \r | |
| 29 | #define CHECK_PATTERN 0xAA\r | |
| 30 | \r | |
| 31 | #define ACMD6 6\r | |
| 32 | #define ACMD13 13\r | |
| 33 | #define ACMD23 23\r | |
| 34 | #define ACMD41 41\r | |
| 35 | #define ACMD42 42\r | |
| 36 | #define ACMD51 51\r | |
| 37 | \r | |
| 38 | \r | |
| 39 | #define SWITCH_FUNC CMD6\r | |
| 40 | #define SEND_IF_COND CMD8\r | |
| 41 | \r | |
| 42 | \r | |
| 43 | #define SET_BUS_WIDTH ACMD6\r | |
| 44 | #define SD_STATUS ACMD13\r | |
| 45 | #define SET_WR_BLK_ERASE_COUNT ACMD23\r | |
| 46 | #define SD_SEND_OP_COND ACMD41\r | |
| 47 | #define SET_CLR_CARD_DETECT ACMD42\r | |
| 48 | #define SEND_SCR ACMD51\r | |
| 49 | \r | |
| 50 | \r | |
| 51 | \r | |
| 52 | #define SD_BUS_WIDTH_1 0\r | |
| 53 | #define SD_BUS_WIDTH_4 2\r | |
| 54 | \r | |
| 55 | \r | |
| 56 | \r | |
| 57 | #define FREQUENCY_SD_PP (25 * 1000 * 1000)\r | |
| 58 | #define FREQUENCY_SD_PP_HIGH (50 * 1000 * 1000)\r | |
| 59 | \r | |
| 60 | \r | |
| 61 | #define SD_SPEC_10 0\r | |
| 62 | #define SD_SPEC_11 1\r | |
| 63 | #define SD_SPEC_20 2\r | |
| 64 | \r | |
| 65 | \r | |
| 66 | #define VOLTAGE_27_36 0x1\r | |
| 67 | \r | |
| 68 | typedef struct {\r | |
| 69 | UINT8 NotUsed: 1; // 1 [0:0]\r | |
| 70 | UINT8 CRC: 7; // CRC [7:1]\r | |
| 71 | UINT8 ECC: 2; // ECC code [9:8]\r | |
| 72 | UINT8 FILE_FORMAT: 2; // File format [11:10]\r | |
| 73 | UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12]\r | |
| 74 | UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]\r | |
| 75 | UINT8 COPY: 1; // Copy flag (OTP) [14:14]\r | |
| 76 | UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15]\r | |
| 77 | UINT16 Reserved0: 5; // 0 [20:16]\r | |
| 78 | UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21]\r | |
| 79 | UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22]\r | |
| 80 | UINT16 R2W_FACTOR: 3; // Write speed factor [28:26]\r | |
| 81 | UINT16 DEFAULT_ECC: 2; // Manufacturer default ECC [30:29]\r | |
| 82 | UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31]\r | |
| 83 | UINT16 WP_GRP_SIZE: 7; // Write protect group size [38:32]\r | |
| 84 | UINT16 SECTOR_SIZE: 7; // Erase sector size [45:39]\r | |
| 85 | UINT16 ERASE_BLK_EN: 1; // Erase single block enable [46:46]\r | |
| 86 | UINT16 Reserved1: 1; // 0 [47:47]\r | |
| 87 | \r | |
| 88 | UINT32 C_SIZE: 22; // Device size [69:48]\r | |
| 89 | UINT32 Reserved2: 6; // 0 [75:70]\r | |
| 90 | UINT32 DSR_IMP: 1; // DSR implemented [76:76]\r | |
| 91 | UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77]\r | |
| 92 | UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78]\r | |
| 93 | UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79]\r | |
| 94 | \r | |
| 95 | UINT16 READ_BL_LEN: 4; // Max. read data block length [83:80]\r | |
| 96 | UINT16 CCC: 12; // Card command classes [95:84]\r | |
| 97 | UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96]\r | |
| 98 | UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]\r | |
| 99 | UINT8 TAAC ; // Data read access-time 1 [119:112]\r | |
| 100 | UINT8 Reserved3: 6; // 0 [125:120]\r | |
| 101 | UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126]\r | |
| 102 | } CSD_SDV2;\r | |
| 103 | \r | |
| 104 | typedef struct {\r | |
| 105 | UINT32 Reserved0;\r | |
| 106 | UINT32 Reserved1: 16;\r | |
| 107 | UINT32 SD_BUS_WIDTH: 4;\r | |
| 108 | UINT32 SD_SECURITY: 3;\r | |
| 109 | UINT32 DATA_STAT_AFTER_ERASE: 1;\r | |
| 110 | UINT32 SD_SPEC: 4;\r | |
| 111 | UINT32 SCR_STRUCT: 4;\r | |
| 112 | } SCR;\r | |
| 113 | \r | |
| 114 | \r | |
| 115 | typedef struct {\r | |
| 116 | UINT8 Reserved0[50];\r | |
| 117 | UINT8 ERASE_OFFSET: 2;\r | |
| 118 | UINT8 ERASE_TIMEOUT: 6;\r | |
| 119 | UINT16 ERASE_SIZE;\r | |
| 120 | UINT8 Reserved1: 4;\r | |
| 121 | UINT8 AU_SIZE: 4;\r | |
| 122 | UINT8 PERFORMANCE_MOVE;\r | |
| 123 | UINT8 SPEED_CLASS;\r | |
| 124 | UINT32 SIZE_OF_PROTECTED_AREA;\r | |
| 125 | UINT32 SD_CARD_TYPE: 16;\r | |
| 126 | UINT32 Reserved2: 13;\r | |
| 127 | UINT32 SECURED_MODE: 1;\r | |
| 128 | UINT32 DAT_BUS_WIDTH: 2;\r | |
| 129 | } SD_STATUS_REG;\r | |
| 130 | \r | |
| 131 | \r | |
| 132 | \r | |
| 133 | typedef struct {\r | |
| 134 | UINT8 Reserved0[34];\r | |
| 135 | UINT16 Group1BusyStatus;\r | |
| 136 | UINT16 Group2BusyStatus;\r | |
| 137 | UINT16 Group3BusyStatus;\r | |
| 138 | UINT16 Group4BusyStatus;\r | |
| 139 | UINT16 Group5BusyStatus;\r | |
| 140 | UINT16 Group6BusyStatus;\r | |
| 141 | UINT8 DataStructureVersion;\r | |
| 142 | UINT8 Group21Status;\r | |
| 143 | UINT8 Group43Status;\r | |
| 144 | UINT8 Group65Status;\r | |
| 145 | UINT16 Group1Function;\r | |
| 146 | UINT16 Group2Function;\r | |
| 147 | UINT16 Group3Function;\r | |
| 148 | UINT16 Group4Function;\r | |
| 149 | UINT16 Group5Function;\r | |
| 150 | UINT16 Group6Function;\r | |
| 151 | UINT16 MaxCurrent;\r | |
| 152 | } SWITCH_STATUS;\r | |
| 153 | \r | |
| 154 | \r | |
| 155 | #pragma pack()\r | |
| 156 | #endif\r | |
| 157 | \r |