Add code to identify D0 stepping ValleyView SoC.

[mirror_edk2.git] / Vlv2DeviceRefCodePkg / ValleyView2Soc / SouthCluster / Include / PchCommonDefinitions.h

/*++\r
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Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved\r
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  This program and the accompanying materials are licensed and made available under\r
  the terms and conditions of the BSD License that accompanies this distribution.\r
  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php.\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
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Module Name:\r
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  PchCommonDefinitions.h\r
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Abstract:\r
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  This header file provides common definitions for PCH\r
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--*/\r
#ifndef _PCH_COMMON_DEFINITIONS_H_\r
#define _PCH_COMMON_DEFINITIONS_H_\r
\r
//\r
//  MMIO access macros\r
//\r
#define PchMmioAddress(BaseAddr, Register)  ((UINTN) BaseAddr + (UINTN) (Register))\r
\r
//\r
// 32 bit MMIO access\r
//\r
#define PchMmio32Ptr(BaseAddr, Register)  ((volatile UINT32 *) PchMmioAddress (BaseAddr, Register))\r
\r
#define PchMmio32(BaseAddr, Register)     *PchMmio32Ptr (BaseAddr, Register)\r
\r
#define PchMmio32Or(BaseAddr, Register, OrData) \\r
  PchMmio32 (BaseAddr, Register) = (UINT32) \\r
    (PchMmio32 (BaseAddr, Register) | (UINT32) (OrData))\r
\r
#define PchMmio32And(BaseAddr, Register, AndData) \\r
  PchMmio32 (BaseAddr, Register) = (UINT32) \\r
    (PchMmio32 (BaseAddr, Register) & (UINT32) (AndData))\r
\r
#define PchMmio32AndThenOr(BaseAddr, Register, AndData, OrData) \\r
  PchMmio32 (BaseAddr, Register) = (UINT32) \\r
    ((PchMmio32 (BaseAddr, Register) & (UINT32) (AndData)) | (UINT32) (OrData))\r
\r
//\r
// 16 bit MMIO access\r
//\r
#define PchMmio16Ptr(BaseAddr, Register)  ((volatile UINT16 *) PchMmioAddress (BaseAddr, Register))\r
\r
#define PchMmio16(BaseAddr, Register)     *PchMmio16Ptr (BaseAddr, Register)\r
\r
#define PchMmio16Or(BaseAddr, Register, OrData) \\r
  PchMmio16 (BaseAddr, Register) = (UINT16) \\r
    (PchMmio16 (BaseAddr, Register) | (UINT16) (OrData))\r
\r
#define PchMmio16And(BaseAddr, Register, AndData) \\r
  PchMmio16 (BaseAddr, Register) = (UINT16) \\r
    (PchMmio16 (BaseAddr, Register) & (UINT16) (AndData))\r
\r
#define PchMmio16AndThenOr(BaseAddr, Register, AndData, OrData) \\r
  PchMmio16 (BaseAddr, Register) = (UINT16) \\r
    ((PchMmio16 (BaseAddr, Register) & (UINT16) (AndData)) | (UINT16) (OrData))\r
\r
//\r
// 8 bit MMIO access\r
//\r
#define PchMmio8Ptr(BaseAddr, Register) ((volatile UINT8 *) PchMmioAddress (BaseAddr, Register))\r
\r
#define PchMmio8(BaseAddr, Register)    *PchMmio8Ptr (BaseAddr, Register)\r
\r
#define PchMmio8Or(BaseAddr, Register, OrData) \\r
  PchMmio8 (BaseAddr, Register) = (UINT8) \\r
    (PchMmio8 (BaseAddr, Register) | (UINT8) (OrData))\r
\r
#define PchMmio8And(BaseAddr, Register, AndData) \\r
  PchMmio8 (BaseAddr, Register) = (UINT8) \\r
    (PchMmio8 (BaseAddr, Register) & (UINT8) (AndData))\r
\r
#define PchMmio8AndThenOr(BaseAddr, Register, AndData, OrData) \\r
  PchMmio8 (BaseAddr, Register) = (UINT8) \\r
    ((PchMmio8 (BaseAddr, Register) & (UINT8) (AndData)) | (UINT8) (OrData))\r
\r
//\r
// Memory Mapped PCI Access macros\r
//\r
#define PCH_PCI_EXPRESS_BASE_ADDRESS  0xE0000000\r
//\r
// PCI Device MM Base\r
//\r
#define PchPciDeviceMmBase(Bus, Device, Function) \\r
    ( \\r
      (UINTN) PCH_PCI_EXPRESS_BASE_ADDRESS + (UINTN) (Bus << 20) + (UINTN) (Device << 15) + (UINTN) \\r
        (Function << 12) \\r
    )\r
\r
//\r
// PCI Device MM Address\r
//\r
#define PchPciDeviceMmAddress(Segment, Bus, Device, Function, Register) \\r
    ( \\r
      (UINTN) PCH_PCI_EXPRESS_BASE_ADDRESS + (UINTN) (Bus << 20) + (UINTN) (Device << 15) + (UINTN) \\r
        (Function << 12) + (UINTN) (Register) \\r
    )\r
\r
//\r
// 32 bit PCI access\r
//\r
#define PchMmPci32Ptr(Segment, Bus, Device, Function, Register) \\r
    ((volatile UINT32 *) PchPciDeviceMmAddress (Segment, Bus, Device, Function, Register))\r
\r
#define PchMmPci32(Segment, Bus, Device, Function, Register)  *PchMmPci32Ptr (Segment, Bus, Device, Function, Register)\r
\r
#define PchMmPci32Or(Segment, Bus, Device, Function, Register, OrData) \\r
  PchMmPci32 ( \\r
  Segment, \\r
  Bus, \\r
  Device, \\r
  Function, \\r
  Register \\r
  ) = (UINT32) (PchMmPci32 (Segment, Bus, Device, Function, Register) | (UINT32) (OrData))\r
\r
#define PchMmPci32And(Segment, Bus, Device, Function, Register, AndData) \\r
  PchMmPci32 ( \\r
  Segment, \\r
  Bus, \\r
  Device, \\r
  Function, \\r
  Register \\r
  ) = (UINT32) (PchMmPci32 (Segment, Bus, Device, Function, Register) & (UINT32) (AndData))\r
\r
#define PchMmPci32AndThenOr(Segment, Bus, Device, Function, Register, AndData, OrData) \\r
  PchMmPci32 ( \\r
  Segment, \\r
  Bus, \\r
  Device, \\r
  Function, \\r
  Register \\r
  ) = (UINT32) ((PchMmPci32 (Segment, Bus, Device, Function, Register) & (UINT32) (AndData)) | (UINT32) (OrData))\r
\r
//\r
// 16 bit PCI access\r
//\r
#define PchMmPci16Ptr(Segment, Bus, Device, Function, Register) \\r
    ((volatile UINT16 *) PchPciDeviceMmAddress (Segment, Bus, Device, Function, Register))\r
\r
#define PchMmPci16(Segment, Bus, Device, Function, Register)  *PchMmPci16Ptr (Segment, Bus, Device, Function, Register)\r
\r
#define PchMmPci16Or(Segment, Bus, Device, Function, Register, OrData) \\r
  PchMmPci16 ( \\r
  Segment, \\r
  Bus, \\r
  Device, \\r
  Function, \\r
  Register \\r
  ) = (UINT16) (PchMmPci16 (Segment, Bus, Device, Function, Register) | (UINT16) (OrData))\r
\r
#define PchMmPci16And(Segment, Bus, Device, Function, Register, AndData) \\r
  PchMmPci16 ( \\r
  Segment, \\r
  Bus, \\r
  Device, \\r
  Function, \\r
  Register \\r
  ) = (UINT16) (PchMmPci16 (Segment, Bus, Device, Function, Register) & (UINT16) (AndData))\r
\r
#define PchMmPci16AndThenOr(Segment, Bus, Device, Function, Register, AndData, OrData) \\r
  PchMmPci16 ( \\r
  Segment, \\r
  Bus, \\r
  Device, \\r
  Function, \\r
  Register \\r
  ) = (UINT16) ((PchMmPci16 (Segment, Bus, Device, Function, Register) & (UINT16) (AndData)) | (UINT16) (OrData))\r
\r
//\r
// 8 bit PCI access\r
//\r
#define PchMmPci8Ptr(Segment, Bus, Device, Function, Register) \\r
    ((volatile UINT8 *) PchPciDeviceMmAddress (Segment, Bus, Device, Function, Register))\r
\r
#define PchMmPci8(Segment, Bus, Device, Function, Register) *PchMmPci8Ptr (Segment, Bus, Device, Function, Register)\r
\r
#define PchMmPci8Or(Segment, Bus, Device, Function, Register, OrData) \\r
  PchMmPci8 ( \\r
  Segment, \\r
  Bus, \\r
  Device, \\r
  Function, \\r
  Register \\r
  ) = (UINT8) (PchMmPci8 (Segment, Bus, Device, Function, Register) | (UINT8) (OrData))\r
\r
#define PchMmPci8And(Segment, Bus, Device, Function, Register, AndData) \\r
  PchMmPci8 ( \\r
  Segment, \\r
  Bus, \\r
  Device, \\r
  Function, \\r
  Register \\r
  ) = (UINT8) (PchMmPci8 (Segment, Bus, Device, Function, Register) & (UINT8) (AndData))\r
\r
#define PchMmPci8AndThenOr(Segment, Bus, Device, Function, Register, AndData, OrData) \\r
  PchMmPci8 ( \\r
  Segment, \\r
  Bus, \\r
  Device, \\r
  Function, \\r
  Register \\r
  ) = (UINT8) ((PchMmPci8 (Segment, Bus, Device, Function, Register) & (UINT8) (AndData)) | (UINT8) (OrData))\r
\r
#endif\r