projects / mirror_edk2.git / blame
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|---|---|---|
| 3cbfba02 DW |
1 | /**\r |
| 2 | \r | |
| 3 | Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved\r | |
| 4 | \r | |
| 5 | This program and the accompanying materials are licensed and made available under\r | |
| 6 | the terms and conditions of the BSD License that accompanies this distribution.\r | |
| 7 | The full text of the license may be found at\r | |
| 8 | http://opensource.org/licenses/bsd-license.php.\r | |
| 9 | \r | |
| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 12 | \r | |
| 13 | \r | |
| 14 | \r | |
| 15 | @file\r | |
| 16 | PchRegsHda.h\r | |
| 17 | \r | |
| 18 | @brief\r | |
| 19 | Register names for PCH High Definition Audio device.\r | |
| 20 | \r | |
| 21 | Conventions:\r | |
| 22 | \r | |
| 23 | - Prefixes:\r | |
| 24 | Definitions beginning with "R_" are registers\r | |
| 25 | Definitions beginning with "B_" are bits within registers\r | |
| 26 | Definitions beginning with "V_" are meaningful values of bits within the registers\r | |
| 27 | Definitions beginning with "S_" are register sizes\r | |
| 28 | Definitions beginning with "N_" are the bit position\r | |
| 29 | - In general, PCH registers are denoted by "_PCH_" in register names\r | |
| 30 | - Registers / bits that are different between PCH generations are denoted by\r | |
| 31 | "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"\r | |
| 32 | - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"\r | |
| 33 | at the end of the register/bit names\r | |
| 34 | - Registers / bits of new devices introduced in a PCH generation will be just named\r | |
| 35 | as "_PCH_" without <generation_name> inserted.\r | |
| 36 | \r | |
| 37 | **/\r | |
| 38 | #ifndef _PCH_REGS_HDA_H_\r | |
| 39 | #define _PCH_REGS_HDA_H_\r | |
| 40 | \r | |
| 41 | ///\r | |
| 42 | /// Azalia Controller Registers (D27:F0)\r | |
| 43 | ///\r | |
| 44 | #define PCI_DEVICE_NUMBER_PCH_AZALIA 27\r | |
| 45 | #define PCI_FUNCTION_NUMBER_PCH_AZALIA 0\r | |
| 46 | \r | |
| 47 | #define R_PCH_HDA_PCS 0x54 // Power Management Control and Status\r | |
| 48 | #define B_PCH_HDA_PCS_DATA 0xFF000000 // Data, does not apply\r | |
| 49 | #define B_PCH_HDA_PCS_CCE BIT23 // Bus Power Control Enable, does not apply\r | |
| 50 | #define B_PCH_HDA_PCS_PMES BIT15 // PME Status\r | |
| 51 | #define B_PCH_HDA_PCS_PMEE BIT8 // PME Enable\r | |
| 52 | #define B_PCH_HDA_PCS_PS (BIT1 | BIT0) // Power State - D0/D3 Hot\r | |
| 53 | #define V_PCH_HDA_PCS_PS0 0x00\r | |
| 54 | #define V_PCH_HDA_PCS_PS3 0x03\r | |
| 55 | \r | |
| 56 | #endif\r |