projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3cbfba02 DW |
1 | /**\r |
| 2 | \r | |
| 3 | Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved\r | |
| 4 | \r | |
| 5 | This program and the accompanying materials are licensed and made available under\r | |
| 6 | the terms and conditions of the BSD License that accompanies this distribution.\r | |
| 7 | The full text of the license may be found at\r | |
| 8 | http://opensource.org/licenses/bsd-license.php.\r | |
| 9 | \r | |
| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 12 | \r | |
| 13 | \r | |
| 14 | \r | |
| 15 | @file\r | |
| 16 | PchRegsPcie.h\r | |
| 17 | \r | |
| 18 | @brief\r | |
| 19 | Register names for VLV PCI-E root port devices\r | |
| 20 | \r | |
| 21 | Conventions:\r | |
| 22 | \r | |
| 23 | - Prefixes:\r | |
| 24 | Definitions beginning with "R_" are registers\r | |
| 25 | Definitions beginning with "B_" are bits within registers\r | |
| 26 | Definitions beginning with "V_" are meaningful values of bits within the registers\r | |
| 27 | Definitions beginning with "S_" are register sizes\r | |
| 28 | Definitions beginning with "N_" are the bit position\r | |
| 29 | - In general, PCH registers are denoted by "_PCH_" in register names\r | |
| 30 | - Registers / bits that are different between PCH generations are denoted by\r | |
| 31 | "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"\r | |
| 32 | - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"\r | |
| 33 | at the end of the register/bit names\r | |
| 34 | - Registers / bits of new devices introduced in a PCH generation will be just named\r | |
| 35 | as "_PCH_" without <generation_name> inserted.\r | |
| 36 | \r | |
| 37 | --*/\r | |
| 38 | #ifndef _PCH_REGS_PCIE_H_\r | |
| 39 | #define _PCH_REGS_PCIE_H_\r | |
| 40 | \r | |
| 41 | #define PCH_PCIE_MAX_ROOT_PORTS 4\r | |
| 42 | \r | |
| 43 | ///\r | |
| 44 | /// VLV PCI Express Root Ports (D28:F0~F3)\r | |
| 45 | ///\r | |
| 46 | #define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS 28\r | |
| 47 | #define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1 0\r | |
| 48 | #define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2 1\r | |
| 49 | #define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3 2\r | |
| 50 | #define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4 3\r | |
| 51 | \r | |
| 52 | #define R_PCH_PCIE_ID 0x00 // Identifiers\r | |
| 53 | #define B_PCH_PCIE_ID_DID 0xFFFF0000 // Device ID\r | |
| 54 | #define V_PCH_PCIE_DEVICE_ID_0 0x0F48 // PCIE Root Port #1\r | |
| 55 | #define V_PCH_PCIE_DEVICE_ID_1 0x0F4A // PCIE Root Port #2\r | |
| 56 | #define V_PCH_PCIE_DEVICE_ID_2 0x0F4C // PCIE Root Port #3\r | |
| 57 | #define V_PCH_PCIE_DEVICE_ID_3 0x0F4E // PCIE Root Port #4\r | |
| 58 | #define B_PCH_PCIE_ID_VID 0x0000FFFF // Vendor ID\r | |
| 59 | #define V_PCH_PCIE_VENDOR_ID V_PCH_INTEL_VENDOR_ID\r | |
| 60 | \r | |
| 61 | \r | |
| 62 | #define R_PCH_PCIE_BNUM_SLT 0x18 // Bus Numbers; Secondary Latency Timer\r | |
| 63 | #define B_PCH_PCIE_BNUM_SLT_SLT 0xFF000000 // Secondary Latency Timer\r | |
| 64 | #define B_PCH_PCIE_BNUM_SLT_SBBN 0x00FF0000 // Subordinate Bus Number\r | |
| 65 | #define B_PCH_PCIE_BNUM_SLT_SCBN 0x0000FF00 // Secondary Bus Number\r | |
| 66 | #define B_PCH_PCIE_BNUM_SLT_PBN 0x000000FF // Primary Bus Number\r | |
| 67 | #define R_PCH_PCIE_CAPP 0x34 // Capabilities List Pointer\r | |
| 68 | #define B_PCH_PCIE_CAPP 0xFF // Capabilities Pointer\r | |
| 69 | \r | |
| 70 | #define R_PCH_PCIE_SLCTL_SLSTS 0x58 // Slot Control; Slot Status\r | |
| 71 | #define S_PCH_PCIE_SLCTL_SLSTS 4\r | |
| 72 | #define B_PCH_PCIE_SLCTL_SLSTS_DLLSC BIT24 // Data Link Layer State Changed\r | |
| 73 | #define B_PCH_PCIE_SLCTL_SLSTS_PDS BIT22 // Presence Detect State\r | |
| 74 | #define B_PCH_PCIE_SLCTL_SLSTS_MS BIT21 // MRL Sensor State\r | |
| 75 | #define B_PCH_PCIE_SLCTL_SLSTS_PDC BIT19 // Presence Detect Changed\r | |
| 76 | #define B_PCH_PCIE_SLCTL_SLSTS_MSC BIT18 // MRL Sensor Changed\r | |
| 77 | #define B_PCH_PCIE_SLCTL_SLSTS_PFD BIT17 // Power Fault Detected\r | |
| 78 | #define B_PCH_PCIE_SLCTL_SLSTS_DLLSCE BIT12 // Data Link Layer State Changed Enable\r | |
| 79 | #define B_PCH_PCIE_SLCTL_SLSTS_PCC BIT10 // Power Controller Control\r | |
| 80 | #define B_PCH_PCIE_SLCTL_SLSTS_HPE BIT5 // Hot Plug Interrupt Enable\r | |
| 81 | #define B_PCH_PCIE_SLCTL_SLSTS_CCE BIT4 // Command Completed Interrupt Enable\r | |
| 82 | #define B_PCH_PCIE_SLCTL_SLSTS_PDE BIT3 // Presence Detect Changed Enable\r | |
| 83 | \r | |
| 84 | #define R_PCH_PCIE_SVID 0x94 // Subsystem Vendor IDs\r | |
| 85 | #define S_PCH_PCIE_SVID 4\r | |
| 86 | #define B_PCH_PCIE_SVID_SID 0xFFFF0000 // Subsystem Identifier\r | |
| 87 | #define B_PCH_PCIE_SVID_SVID 0x0000FFFF // Subsystem Vendor Identifier\r | |
| 88 | \r | |
| 89 | #endif\r |