Add code to identify D0 stepping ValleyView SoC.
[mirror_edk2.git] / Vlv2DeviceRefCodePkg / ValleyView2Soc / SouthCluster / Include / PchRegs / PchRegsPcu.h
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1/*++\r
2\r
3Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved\r
4\r
5 This program and the accompanying materials are licensed and made available under\r
6 the terms and conditions of the BSD License that accompanies this distribution.\r
7 The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php.\r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13\r
14\r
15Module Name:\r
16\r
17 PchRegsPcu.h\r
18\r
19Abstract:\r
20\r
21 Register names for VLV PCU device.\r
22\r
23 Conventions:\r
24\r
25 - Prefixes:\r
26 Definitions beginning with "R_" are registers\r
27 Definitions beginning with "B_" are bits within registers\r
28 Definitions beginning with "V_" are meaningful values of bits within the registers\r
29 Definitions beginning with "S_" are register sizes\r
30 Definitions beginning with "N_" are the bit position\r
31 - In general, PCH registers are denoted by "_PCH_" in register names\r
32 - Registers / bits that are different between PCH generations are denoted by\r
33 "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"\r
34 - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"\r
35 at the end of the register/bit names\r
36 - Registers / bits of new devices introduced in a PCH generation will be just named\r
37 as "_PCH_" without <generation_name> inserted.\r
38\r
39--*/\r
40#ifndef _PCH_REGS_LPC_H_\r
41#define _PCH_REGS_LPC_H_\r
42\r
43//\r
44// VLV PCU Registers (D31:F0)\r
45//\r
46#define PCI_DEVICE_NUMBER_PCH_LPC 31\r
47#define PCI_FUNCTION_NUMBER_PCH_LPC 0\r
48\r
49// Silicon Steppings\r
50typedef enum {\r
51 PchA0 = 0,\r
52 PchA1 = 1,\r
53 PchB0 = 2,\r
54 PchB1 = 3,\r
55 PchB2 = 4,\r
56 PchB3 = 5,\r
57 PchC0 = 6,\r
58 PchD0 = 7,\r
59 PchSteppingMax\r
60} PCH_STEPPING;\r
61\r
62#define R_PCH_LPC_REG_ID 0x00 // Identifiers Register\r
63#define B_PCH_LPC_DEVICE_ID 0xFFFF0000 // Device Identification\r
64#define B_PCH_LPC_VENDOR_ID 0x0000FFFF // Vendor Identification\r
65#define V_PCH_LPC_VENDOR_ID V_PCH_INTEL_VENDOR_ID // Vendor ID for Intel\r
66//\r
67// General VLV PCU Device ID\r
68//\r
69#define V_PCH_LPC_DEVICE_ID_0 0x0F1C\r
70#define V_PCH_LPC_DEVICE_ID_1 0x0F1D\r
71#define V_PCH_LPC_DEVICE_ID_2 0x0F1E\r
72#define V_PCH_LPC_DEVICE_ID_3 0x0F1F\r
73\r
74#define R_PCH_LPC_COMMAND 0x04 // Command\r
75#define B_PCH_LPC_COMMAND_ID BIT10 // Interrupt Disable\r
76#define B_PCH_LPC_COMMAND_FBE BIT9 // Fast Back to Back Enable\r
77#define B_PCH_LPC_COMMAND_SERR_EN BIT8 // SERR# Enable\r
78#define B_PCH_LPC_COMMAND_WCC BIT7 // Wait Cycle Control\r
79#define B_PCH_LPC_COMMAND_PER BIT6 // Parity Error Response Enable\r
80#define B_PCH_LPC_COMMAND_VPS BIT5 // VGA Palette Snoop\r
81#define B_PCH_LPC_COMMAND_MWIE BIT4 // Memory Write and Invalidate Enable\r
82#define B_PCH_LPC_COMMAND_SCE BIT3 // Special Cycle Enable\r
83#define B_PCH_LPC_COMMAND_BME BIT2 // Bus Master Enable\r
84#define B_PCH_LPC_COMMAND_MSE BIT1 // Memory Space Enable\r
85#define B_PCH_LPC_COMMAND_IOSE BIT0 // I/O Space Enable\r
86\r
87#define R_PCH_LPC_DEV_STS 0x06 // Status\r
88#define B_PCH_LPC_DEV_STS_DPE BIT15 // Detected Parity Error\r
89#define B_PCH_LPC_DEV_STS_SSE BIT14 // Signaled System Error\r
90#define B_PCH_LPC_DEV_STS_RMA BIT13 // Received Master Abort\r
91#define B_PCH_LPC_DEV_STS_RTA BIT12 // Received Target Abort\r
92#define B_PCH_LPC_DEV_STS_STA BIT11 // Signaled Target Abort\r
93#define B_PCH_LPC_DEV_STS_DEVT_STS (BIT10 | BIT9) // DEVSEL# Timing Status\r
94#define B_PCH_LPC_DEV_STS_MDPED BIT8 // Data Parity Error\r
95#define B_PCH_LPC_DEV_STS_FB2B BIT7 // Fast Back to Back Capable\r
96#define B_PCH_LPC_DEV_STS_66MHZ_CAP BIT5 // 66 MHz capable\r
97#define B_PCH_LPC_DEV_STS_CAP_LIST BIT4 // Capabilities List\r
98#define B_PCH_LPC_DEV_STS_INT_STS BIT3 // Interrupt Status\r
99\r
100#define R_PCH_LPC_RID_CC 0x08 // Revision ID & Class Code\r
101#define B_PCH_LPC_RID_CC_BCC 0xFF000000 // Base Class Code\r
102#define B_PCH_LPC_RID_CC_SCC 0x00FF0000 // Sub-Class Code\r
103#define B_PCH_LPC_RID_CC_PI 0x0000FF00 // Programming Interface\r
104#define B_PCH_LPC_RID_CC_RID 0x000000FF // Revision ID\r
105\r
106// Silicon Steppings\r
107\r
108#define V_PCH_LPC_RID_0 0x01 // A0 Stepping (17 x 17)\r
109#define V_PCH_LPC_RID_1 0x02 // A0 Stepping (25 x 27)\r
110#define V_PCH_LPC_RID_2 0x03 // A1 Stepping (17 x 17)\r
111#define V_PCH_LPC_RID_3 0x04 // A1 Stepping (25 x 27)\r
112#define V_PCH_LPC_RID_4 0x05 // B0 Stepping (17 x 17)\r
113#define V_PCH_LPC_RID_5 0x06 // B0 Stepping (25 x 27)\r
114#define V_PCH_LPC_RID_6 0x07 // B1 Stepping (17 x 17)\r
115#define V_PCH_LPC_RID_7 0x08 // B1 Stepping (25 x 27)\r
116#define V_PCH_LPC_RID_8 0x09 // B2 Stepping (17 x 17)\r
117#define V_PCH_LPC_RID_9 0x0A // B2 Stepping (25 x 27)\r
118#define V_PCH_LPC_RID_A 0x0B // B3 Stepping (17 x 17)\r
119#define V_PCH_LPC_RID_B 0x0C // B3 Stepping (25 x 27)\r
120#define V_PCH_LPC_RID_C 0x0D // C0 Stepping (17 x 17)\r
121#define V_PCH_LPC_RID_D 0x0E // C0 Stepping (25 x 27)\r
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122#define V_PCH_LPC_RID_E 0x10 // D0 Stepping (17 x 17)\r
123#define V_PCH_LPC_RID_F 0x11 // D0 Stepping (25 x 27)\r
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124\r
125#define R_PCH_LPC_MLT 0x0D // Master Latency Timer\r
126#define B_PCH_LPC_MLT_MLC 0xF8 // Master Latency Count\r
127\r
128#define R_PCH_LPC_HEADTYP 0x0E // Header Type\r
129#define B_PCH_LPC_HEADTYP_MFD BIT7 // Multi-function Device\r
130#define B_PCH_LPC_HEADTYP_HT 0x7F // Header Type\r
131\r
132#define R_PCH_LPC_SS 0x2C // Subsystem ID & Vendor ID\r
133#define B_PCH_LPC_SS_SSID 0xFFFF0000 // Subsystem ID\r
134#define B_PCH_LPC_SS_SSVID 0x0000FFFF // Subsystem Vendor ID\r
135\r
136#define R_PCH_LPC_CAP_LIST 0x34 // Capability List\r
137#define B_PCH_LPC_CAP_LIST_CP 0xFF // Capability Pointer\r
138\r
139#define R_PCH_LPC_ACPI_BASE 0x40 // ABASE, 16bit\r
140#define B_PCH_LPC_ACPI_BASE_BAR 0x0000FF80 // Base Address, 128 Bytes\r
141#define B_PCH_LPC_ACPI_BASE_EN BIT1 // Enable Bit\r
142#define B_PCH_LPC_ACPI_BASE_MEMI BIT0 // Memory Space Indication\r
143\r
144#define R_PCH_LPC_PMC_BASE 0x44 // PBASE, 32bit, 512 Bytes\r
145#define B_PCH_LPC_PMC_BASE_BAR 0xFFFFFE00 // Base Address\r
146#define B_PCH_LPC_PMC_BASE_PREF BIT3 // Prefetchable\r
147#define B_PCH_LPC_PMC_BASE_ADDRNG BIT2 // Address Range\r
148#define B_PCH_LPC_PMC_BASE_EN BIT1 // Enable Bit\r
149#define B_PCH_LPC_PMC_BASE_MEMI BIT0 // Memory Space Indication\r
150\r
151#define R_PCH_LPC_GPIO_BASE 0x48 // GBASE, 16bit\r
152#define B_PCH_LPC_GPIO_BASE_BAR 0xFF00 // Base Address, 256 Bytes\r
153#define B_PCH_LPC_GPIO_BASE_EN BIT1 // Enable Bit\r
154#define B_PCH_LPC_GPIO_BASE_MEMI BIT0 // Memory Space Indication\r
155\r
156#define R_PCH_LPC_IO_BASE 0x4C // IOBASE, 32bit\r
157#define B_PCH_LPC_IO_BASE_BAR 0xFFFFC000 // Base Address, 16 KiloBytes\r
158#define B_PCH_LPC_IO_BASE_PREF BIT3 // Prefetchable\r
159#define B_PCH_LPC_IO_BASE_ADDRNG BIT2 // Address Range\r
160#define B_PCH_LPC_IO_BASE_EN BIT1 // Enable Bit\r
161#define B_PCH_LPC_IO_BASE_MEMI BIT0 // Memory Space Indication\r
162\r
163#define R_PCH_LPC_ILB_BASE 0x50 // IBASE, 32bit\r
164#define B_PCH_LPC_ILB_BASE_BAR 0xFFFFFE00 // Base Address, 512 bytes\r
165#define B_PCH_LPC_ILB_BASE_PREF BIT3 // Prefetchable\r
166#define B_PCH_LPC_ILB_BASE_ADDRNG BIT2 // Address Range\r
167#define B_PCH_LPC_ILB_BASE_EN BIT1 // Enable Bit\r
168#define B_PCH_LPC_ILB_BASE_MEMI BIT0 // Memory Space Indication\r
169\r
170#define R_PCH_LPC_SPI_BASE 0x54 // SBASE, 32bit\r
171#define B_PCH_LPC_SPI_BASE_BAR 0xFFFFFE00 // Base Address, 512 bytes\r
172#define B_PCH_LPC_SPI_BASE_PREF BIT3 // Prefetchable\r
173#define B_PCH_LPC_SPI_BASE_ADDRNG BIT2 // Address Range\r
174#define B_PCH_LPC_SPI_BASE_EN BIT1 // Enable Bit\r
175#define B_PCH_LPC_SPI_BASE_MEMI BIT0 // Memory Space Indicator\r
176\r
177#define R_PCH_LPC_MPHY_BASE 0x58 // MPBASE, 32bit\r
178#define B_PCH_LPC_MPHY_BASE_BAR 0xFFF00000 // Base Address, 1 MegaByte\r
179#define B_PCH_LPC_MPHY_BASE_PREF BIT3 // Prefetchable\r
180#define B_PCH_LPC_MPHY_BASE_ADDRNG BIT2 // Address Range\r
181#define B_PCH_LPC_MPHY_BASE_EN BIT1 // Enable Bit\r
182#define B_PCH_LPC_MPHY_BASE_MEMI BIT0 // Memory Space Indicator\r
183\r
184#define R_PCH_LPC_PUNIT_BASE 0x5C // PUBASE, 32bit\r
185#define B_PCH_LPC_PUNIT_BASE_BAR 0xFFFFF800 // Base Address, 2K bytes\r
186#define B_PCH_LPC_PUNIT_BASE_PREF BIT3 // Prefetchable\r
187#define B_PCH_LPC_PUNIT_BASE_ADDRNG BIT2 // Address Range\r
188#define B_PCH_LPC_PUNIT_BASE_EN BIT1 // Enable Bit\r
189#define B_PCH_LPC_PUNIT_BASE_MEMI BIT0 // Memory Space Indicator\r
190\r
191#define R_PCH_LPC_UART_CTRL 0x80 // UART Control\r
192#define B_PCH_LPC_UART_CTRL_COM1_EN BIT0 // COM1 Enable\r
193\r
194#define R_PCH_LPC_FWH_BIOS_DEC 0xD8 // BIOS Decode Enable\r
195#define B_PCH_LPC_FWH_BIOS_DEC_EF8 BIT15 // F8-FF Enable\r
196#define B_PCH_LPC_FWH_BIOS_DEC_EF0 BIT14 // F0-F8 Enable\r
197#define B_PCH_LPC_FWH_BIOS_DEC_EE8 BIT13 // E8-EF Enable\r
198#define B_PCH_LPC_FWH_BIOS_DEC_EE0 BIT12 // E0-E8 Enable\r
199#define B_PCH_LPC_FWH_BIOS_DEC_ED8 BIT11 // D8-DF Enable\r
200#define B_PCH_LPC_FWH_BIOS_DEC_ED0 BIT10 // D0-D8 Enable\r
201#define B_PCH_LPC_FWH_BIOS_DEC_EC8 BIT9 // C8-CF Enable\r
202#define B_PCH_LPC_FWH_BIOS_DEC_EC0 BIT8 // C0-C8 Enable\r
203#define B_PCH_LPC_FWH_BIOS_DEC_LFE BIT7 // Legacy F Segment Enable\r
204#define B_PCH_LPC_FWH_BIOS_DEC_LEE BIT6 // Legacy E Segment Enable\r
205#define B_PCH_LPC_FWH_BIOS_DEC_E70 BIT3 // 70-7F Enable\r
206#define B_PCH_LPC_FWH_BIOS_DEC_E60 BIT2 // 60-6F Enable\r
207#define B_PCH_LPC_FWH_BIOS_DEC_E50 BIT1 // 50-5F Enable\r
208#define B_PCH_LPC_FWH_BIOS_DEC_E40 BIT0 // 40-4F Enable\r
209\r
210#define R_PCH_LPC_FDCAP 0xE0 // Feature Detection Capability ID\r
211#define B_PCH_LPC_FDCAP_NEXT 0xFF00 // Next Capability\r
212#define B_PCH_LPC_FDCAP_CAPID 0x00FF // Capability ID\r
213\r
214#define R_PCH_LPC_FDLEN 0xE2 // Feature Detection Capability Length\r
215#define B_PCH_LPC_FDLEN_CAPLEN 0xFF // Capability Length\r
216\r
217#define R_PCH_LPC_FDVER 0xE3 // Feature Detection Capability Version\r
218#define B_PCH_LPC_FDVER_VSCID 0xF0 // Vendor Specific Capability ID\r
219#define B_PCH_LPC_FDVER_CAPVER 0x0F // Capability Version\r
220\r
221#define R_PCH_LPC_FVECTIDX 0xE4 // Feature Vector Index\r
222\r
223#define R_PCH_LPC_FVECTD 0xE8 // Feature Vector Data\r
224\r
225#define R_PCH_LPC_RCBA 0xF0 // RCBA, 32bit\r
226#define B_PCH_LPC_RCBA_BAR 0xFFFFFC00 // Base Address, 1 KiloByte\r
227#define B_PCH_LPC_RCBA_EN BIT0 // Enable Bit\r
228\r
229#define R_PCH_LPC_ULT_OBS 0xF4 // ULT Observability\r
230#define B_PCH_LPC_ULT_OBS_WNUM 0x3FF000 // Reserved Wafer Number\r
231#define B_PCH_LPC_ULT_OBS_XLOC 0xFC0 // Reserved X Loc\r
232#define B_PCH_LPC_ULT_OBS_YLOC 0x3F // Reserved Y Loc\r
233\r
234#define R_PCH_LPC_MAN_ID 0xF8 // Manufacturer ID\r
235#define B_PCH_LPC_MAN_ID_DPID 0xF000000 // Dot Portion of Process ID\r
236#define B_PCH_LPC_MAN_ID_MSID 0xFF0000 // Manufacturing Stepping Identifier\r
237#define B_PCH_LPC_MAN_ID_MID 0xFF00 // Manufacturing Identifier\r
238#define B_PCH_LPC_MAN_ID_PPID 0xFF // Process Portion of Process ID\r
239\r
240#define R_PCH_LPC_CGC 0xFC // Clock Gating Control\r
241#define B_PCH_LPC_CGC_SBLCG BIT9 // IOSF-SB Local Clock Gating Disable\r
242#define B_PCH_LPC_CGC_SBTCG BIT8 // IOSF-SB Trunk Clock Gating (Request) Disable\r
243#define B_PCH_LPC_CGC_PRILCG BIT1 // IOSF-PRI Local Clock Gating Disable\r
244#define B_PCH_LPC_CGC_PRITCG BIT0 // IOSF-PRI Trunk Clock Gating (Request) Disable\r
245\r
246//\r
247// iLB Memory Space Registers (IBASE)\r
248//\r
249#define R_PCH_ILB_ACPI_CNT 0x00 // ACPI Control\r
250#define B_PCH_ILB_ACPI_CNT_SCI_IRQ_SEL (BIT2 | BIT1 | BIT0) // SCI IRQ Select\r
251#define V_PCH_ILB_ACPI_CNT_SCI_IRQ_9 0 // IRQ9\r
252#define V_PCH_ILB_ACPI_CNT_SCI_IRQ_10 BIT0 // IRQ10\r
253#define V_PCH_ILB_ACPI_CNT_SCI_IRQ_11 BIT1 // IRQ11\r
254#define V_PCH_ILB_ACPI_CNT_SCI_IRQ_20 BIT2 // IRQ20 (Only if APIC enabled)\r
255#define V_PCH_ILB_ACPI_CNT_SCI_IRQ_21 (BIT2 | BIT0) // IRQ21 (Only if APIC enabled)\r
256#define V_PCH_ILB_ACPI_CNT_SCI_IRQ_22 (BIT2 | BIT1) // IRQ22 (Only if APIC enabled)\r
257#define V_PCH_ILB_ACPI_CNT_SCI_IRQ_23 (BIT2 | BIT1 | BIT0) // IRQ23 (Only if APIC enabled)\r
258\r
259#define R_PCH_ILB_MC 0x04 // Miscellaneous Control\r
260#define B_PCH_ILB_MC_DRTC BIT3 // Disable RTC\r
261#define B_PCH_ILB_MC_D8259 BIT2 // Disable 8259\r
262#define B_PCH_ILB_MC_D8254 BIT1 // Disable 8254\r
263#define B_PCH_ILB_MC_AME BIT0 // Alternate Access Mode Enable\r
264\r
265#define R_PCH_ILB_PIRQA_ROUT 0x08 // PIRQA Routing Control\r
266#define R_PCH_ILB_PIRQB_ROUT 0x09 // PIRQB Routing Control\r
267#define R_PCH_ILB_PIRQC_ROUT 0x0A // PIRQC Routing Control\r
268#define R_PCH_ILB_PIRQD_ROUT 0x0B // PIRQD Routing Control\r
269#define R_PCH_ILB_PIRQE_ROUT 0x0C // PIRQE Routing Control\r
270#define R_PCH_ILB_PIRQF_ROUT 0x0D // PIRQF Routing Control\r
271#define R_PCH_ILB_PIRQG_ROUT 0x0E // PIRQG Routing Control\r
272#define R_PCH_ILB_PIRQH_ROUT 0x0F // PIRQH Routing Control\r
273//\r
274// Bit values are the same for R_PCH_ILB_PIRQA_ROUT to R_PCH_ILB_PIRQH_ROUT\r
275//\r
276#define B_PCH_ILB_PIRQX_ROUT_IRQEN BIT7 // Interrupt Routing Enable\r
277#define B_PCH_ILB_PIRQX_ROUT 0x0F // IRQ Routing\r
278#define V_PCH_ILB_PIRQX_ROUT_IRQ_3 0x03 // Route to IRQ3\r
279#define V_PCH_ILB_PIRQX_ROUT_IRQ_4 0x04 // Route to IRQ4\r
280#define V_PCH_ILB_PIRQX_ROUT_IRQ_5 0x05 // Route to IRQ5\r
281#define V_PCH_ILB_PIRQX_ROUT_IRQ_6 0x06 // Route to IRQ6\r
282#define V_PCH_ILB_PIRQX_ROUT_IRQ_7 0x07 // Route to IRQ7\r
283#define V_PCH_ILB_PIRQX_ROUT_IRQ_9 0x09 // Route to IRQ9\r
284#define V_PCH_ILB_PIRQX_ROUT_IRQ_10 0x0A // Route to IRQ10\r
285#define V_PCH_ILB_PIRQX_ROUT_IRQ_11 0x0B // Route to IRQ11\r
286#define V_PCH_ILB_PIRQX_ROUT_IRQ_12 0x0C // Route to IRQ12\r
287#define V_PCH_ILB_PIRQX_ROUT_IRQ_14 0x0E // Route to IRQ14\r
288#define V_PCH_ILB_PIRQX_ROUT_IRQ_15 0x0F // Route to IRQ15\r
289\r
290#define R_PCH_ILB_SERIRQ_CNT 0x10 // Serial IRQ Control\r
291#define B_PCH_ILB_SERIRQ_CNT_SIRQMD BIT7 // Mode\r
292\r
293#define R_PCH_ILB_ULKMC 0x14 // USB Legacy Keyboard / Mouse Control\r
294#define B_PCH_ILB_ULKMC_TRAPBY64W BIT11 // SMI Caused by Port 64 Write\r
295#define B_PCH_ILB_ULKMC_TRAPBY64R BIT10 // SMI Caused by Port 64 Read\r
296#define B_PCH_ILB_ULKMC_TRAPBY60W BIT9 // SMI Caused by Port 60 Write\r
297#define B_PCH_ILB_ULKMC_TRAPBY60R BIT8 // SMI Caused by Port 60 Read\r
298#define B_PCH_ILB_ULKMC_64WEN BIT3 // SMI on Port 64 Writes Enable\r
299#define B_PCH_ILB_ULKMC_64REN BIT2 // SMI on Port 64 Reads Enable\r
300#define B_PCH_ILB_ULKMC_60WEN BIT1 // SMI on Port 60 Writes Enable\r
301#define B_PCH_ILB_ULKMC_60REN BIT0 // SMI on Port 60 Reads Enable\r
302\r
303#define R_PCH_ILB_FWH_BIOS_SEL 0x18 // FWH ID Select\r
304#define B_PCH_ILB_FWH_BIOS_SEL_F8 0xF0000000 // F8-FF ID Select\r
305#define B_PCH_ILB_FWH_BIOS_SEL_F0 0x0F000000 // F0-F7 ID Select\r
306#define B_PCH_ILB_FWH_BIOS_SEL_E8 0x00F00000 // E8-EF ID Select\r
307#define B_PCH_ILB_FWH_BIOS_SEL_E0 0x000F0000 // E0-E7 ID Select\r
308#define B_PCH_ILB_FWH_BIOS_SEL_D8 0x0000F000 // D8-DF ID Select\r
309#define B_PCH_ILB_FWH_BIOS_SEL_D0 0x00000F00 // D0-D7 ID Select\r
310#define B_PCH_ILB_FWH_BIOS_SEL_C8 0x000000F0 // C8-CF ID Select\r
311#define B_PCH_ILB_FWH_BIOS_SEL_C0 0x0000000F // C0-C7 ID Select\r
312\r
313#define R_PCH_ILB_BIOS_CNTL 0x1C // BIOS Control\r
314#define S_PCH_ILB_BIOS_CNTL 4\r
315#define B_PCH_ILB_BIOS_CNTL_PFE BIT8 // Prefetch Enable\r
316#define B_PCH_ILB_BIOS_CNTL_LE BIT1 // Lock Enable\r
317#define N_PCH_ILB_BIOS_CNTL_LE 1\r
318#define B_PCH_ILB_BIOS_CNTL_WP BIT0 // Write Protect\r
319\r
320#define R_PCH_ILB_D0IR 0x20 // Device 0 Interrupt Route\r
321#define R_PCH_ILB_D1IR 0x22 // Device 1 Interrupt Route\r
322#define R_PCH_ILB_D2IR 0x24 // Device 2 Interrupt Route\r
323#define R_PCH_ILB_D3IR 0x26 // Device 3 Interrupt Route\r
324#define R_PCH_ILB_D4IR 0x28 // Device 4 Interrupt Route\r
325#define R_PCH_ILB_D5IR 0x2A // Device 5 Interrupt Route\r
326#define R_PCH_ILB_D6IR 0x2C // Device 6 Interrupt Route\r
327#define R_PCH_ILB_D7IR 0x2E // Device 7 Interrupt Route\r
328#define R_PCH_ILB_D8IR 0x30 // Device 8 Interrupt Route\r
329#define R_PCH_ILB_D9IR 0x32 // Device 9 Interrupt Route\r
330#define R_PCH_ILB_D10IR 0x34 // Device 10 Interrupt Route\r
331#define R_PCH_ILB_D11IR 0x36 // Device 11 Interrupt Route\r
332#define R_PCH_ILB_D12IR 0x38 // Device 12 Interrupt Route\r
333#define R_PCH_ILB_D13IR 0x3A // Device 13 Interrupt Route\r
334#define R_PCH_ILB_D14IR 0x3C // Device 14 Interrupt Route\r
335#define R_PCH_ILB_D15IR 0x3E // Device 15 Interrupt Route\r
336#define R_PCH_ILB_D16IR 0x40 // Device 16 Interrupt Route\r
337#define R_PCH_ILB_D17IR 0x42 // Device 17 Interrupt Route\r
338#define R_PCH_ILB_D18IR 0x44 // Device 18 Interrupt Route\r
339#define R_PCH_ILB_D19IR 0x46 // Device 19 Interrupt Route\r
340#define R_PCH_ILB_D20IR 0x48 // Device 20 Interrupt Route\r
341#define R_PCH_ILB_D21IR 0x4A // Device 21 Interrupt Route\r
342#define R_PCH_ILB_D22IR 0x4C // Device 22 Interrupt Route\r
343#define R_PCH_ILB_D23IR 0x4E // Device 23 Interrupt Route\r
344#define R_PCH_ILB_D24IR 0x50 // Device 24 Interrupt Route\r
345#define R_PCH_ILB_D25IR 0x52 // Device 25 Interrupt Route\r
346#define R_PCH_ILB_D26IR 0x54 // Device 26 Interrupt Route\r
347#define R_PCH_ILB_D27IR 0x56 // Device 27 Interrupt Route\r
348#define R_PCH_ILB_D28IR 0x58 // Device 28 Interrupt Route\r
349#define R_PCH_ILB_D29IR 0x5A // Device 29 Interrupt Route\r
350#define R_PCH_ILB_D30IR 0x5C // Device 30 Interrupt Route\r
351#define R_PCH_ILB_D31IR 0x5E // Device 31 Interrupt Route\r
352\r
353#define B_PCH_ILB_DXXIR_IDR_MASK (BIT14 | BIT13 | BIT12) // INTD Mask\r
354#define V_PCH_ILB_DXXIR_IDR_PIRQA 0 // INTD Mapping to IRQ A\r
355#define V_PCH_ILB_DXXIR_IDR_PIRQB BIT12 // INTD Mapping to IRQ B\r
356#define V_PCH_ILB_DXXIR_IDR_PIRQC BIT13 // INTD Mapping to IRQ C\r
357#define V_PCH_ILB_DXXIR_IDR_PIRQD (BIT13 | BIT12) // INTD Mapping to IRQ D\r
358#define V_PCH_ILB_DXXIR_IDR_PIRQE BIT14 // INTD Mapping to IRQ E\r
359#define V_PCH_ILB_DXXIR_IDR_PIRQF (BIT14 | BIT12) // INTD Mapping to IRQ F\r
360#define V_PCH_ILB_DXXIR_IDR_PIRQG (BIT14 | BIT13) // INTD Mapping to IRQ G\r
361#define V_PCH_ILB_DXXIR_IDR_PIRQH (BIT14 | BIT13 | BIT12) // INTD Mapping to IRQ H\r
362\r
363#define B_PCH_ILB_DXXIR_ICR_MASK (BIT10 | BIT9 | BIT8) // INTC Mask\r
364#define V_PCH_ILB_DXXIR_ICR_PIRQA 0 // INTC Mapping to IRQ A\r
365#define V_PCH_ILB_DXXIR_ICR_PIRQB BIT8 // INTC Mapping to IRQ B\r
366#define V_PCH_ILB_DXXIR_ICR_PIRQC BIT9 // INTC Mapping to IRQ C\r
367#define V_PCH_ILB_DXXIR_ICR_PIRQD (BIT9 | BIT8) // INTC Mapping to IRQ D\r
368#define V_PCH_ILB_DXXIR_ICR_PIRQE BIT10 // INTC Mapping to IRQ E\r
369#define V_PCH_ILB_DXXIR_ICR_PIRQF (BIT10 | BIT8) // INTC Mapping to IRQ F\r
370#define V_PCH_ILB_DXXIR_ICR_PIRQG (BIT10 | BIT9) // INTC Mapping to IRQ G\r
371#define V_PCH_ILB_DXXIR_ICR_PIRQH (BIT10 | BIT9 | BIT8) // INTC Mapping to IRQ H\r
372\r
373#define B_PCH_ILB_DXXIR_IBR_MASK (BIT6 | BIT5 | BIT4) // INTB Mask\r
374#define V_PCH_ILB_DXXIR_IBR_PIRQA 0 // INTB Mapping to IRQ A\r
375#define V_PCH_ILB_DXXIR_IBR_PIRQB BIT4 // INTB Mapping to IRQ B\r
376#define V_PCH_ILB_DXXIR_IBR_PIRQC BIT5 // INTB Mapping to IRQ C\r
377#define V_PCH_ILB_DXXIR_IBR_PIRQD (BIT5 | BIT4) // INTB Mapping to IRQ D\r
378#define V_PCH_ILB_DXXIR_IBR_PIRQE BIT6 // INTB Mapping to IRQ E\r
379#define V_PCH_ILB_DXXIR_IBR_PIRQF (BIT6 | BIT4) // INTB Mapping to IRQ F\r
380#define V_PCH_ILB_DXXIR_IBR_PIRQG (BIT6 | BIT5) // INTB Mapping to IRQ G\r
381#define V_PCH_ILB_DXXIR_IBR_PIRQH (BIT6 | BIT5 | BIT4) // INTB Mapping to IRQ H\r
382\r
383#define B_PCH_ILB_DXXIR_IAR_MASK (BIT2 | BIT1 | BIT0) // INTA Mask\r
384#define V_PCH_ILB_DXXIR_IAR_PIRQA 0 // INTA Mapping to IRQ A\r
385#define V_PCH_ILB_DXXIR_IAR_PIRQB BIT0 // INTA Mapping to IRQ B\r
386#define V_PCH_ILB_DXXIR_IAR_PIRQC BIT1 // INTA Mapping to IRQ C\r
387#define V_PCH_ILB_DXXIR_IAR_PIRQD (BIT1 | BIT0) // INTA Mapping to IRQ D\r
388#define V_PCH_ILB_DXXIR_IAR_PIRQE BIT2 // INTA Mapping to IRQ E\r
389#define V_PCH_ILB_DXXIR_IAR_PIRQF (BIT2 | BIT0) // INTA Mapping to IRQ F\r
390#define V_PCH_ILB_DXXIR_IAR_PIRQG (BIT2 | BIT1) // INTA Mapping to IRQ G\r
391#define V_PCH_ILB_DXXIR_IAR_PIRQH (BIT2 | BIT1 | BIT0) // INTA Mapping to IRQ H\r
392\r
393#define R_PCH_ILB_OIC 0x60 // Other Interrupt Controller\r
394#define B_PCH_ILB_OIC_SIRQEN BIT12 // Serial IRQ Enable\r
395#define B_PCH_ILB_OIC_AEN BIT8 // APIC Enable\r
396\r
397#define R_PCH_ILB_RTC_CONF 0x64 // RTC Control\r
398#define B_PCH_ILB_RTC_CONF_UCMOS_LOCK BIT1 // Upper 128 Byte Lock\r
399#define B_PCH_ILB_RTC_CONF_LCMOS_LOCK BIT0 // Lower 128 Byte Lock\r
400\r
401#define R_PCH_ILB_RTM 0x68 // RTC Test Mode\r
402#define B_PCH_ILB_RTM_RTM1 (BIT2 | BIT1 | BIT0)\r
403\r
404#define R_PCH_ILB_BCS 0x6C // BIOS Control Status\r
405#define B_PCH_ILB_BCS_SMIWPEN BIT1 // SMI WPD Enable\r
406#define B_PCH_ILB_BCS_SMIWPST BIT0 // SMI WPD Status\r
407\r
408#define R_PCH_ILB_LE 0x70 // LE\r
409#define B_PCH_ILB_LE_IRQ12C BIT1 // IRQ12 Cause\r
410#define B_PCH_ILB_LE_IRQ1C BIT0 // IRQ1 Cause\r
411\r
412#define R_PCH_ILB_RTCC 0x74 // RTC HIP Configuration\r
413#define B_PCH_ILB_RTCC_RTCB4 BIT6 // RTC Bias Resistor 4, Adds 480 Kohm\r
414#define B_PCH_ILB_RTCC_RTCB3 BIT5 // RTC Bias Resistor 3, Adds 240 Kohm\r
415#define B_PCH_ILB_RTCC_RTCB2 BIT4 // RTC Bias Resistor 2, Adds 120 Kohm\r
416#define B_PCH_ILB_RTCC_RTCB1 BIT3 // RTC Bias Resistor 1, Adds 60 Kohm\r
417#define B_PCH_ILB_RTCC_RTCB0 BIT2 // RTC Bias Resistor 0, Adds 30 Kohm\r
418#define B_PCH_ILB_RTCC_DSWEN BIT1 // Deep Sleep Well Enable\r
419#define B_PCH_ILB_RTCC_FEN BIT0 // Enable the Fast Oscillator Bypass Mode\r
420\r
421#define R_PCH_ILB_DEF0 0x78 // Defeature Register 0\r
422#define B_PCH_ILB_DEF0_SHRTSYNC BIT22 // Short Sync Abort Defeature\r
423#define B_PCH_ILB_DEF0_SDD BIT21 // Sub Decode Disable\r
424\r
425#define R_PCH_ILB_DEF1 0x7C // Defeature Register 1\r
426#define B_PCH_ILB_DEF1_TPMPF BIT10 // usb2leg_chknbit_TPM_PF\r
427#define B_PCH_ILB_DEF1_HPETDEF BIT8 // usb2leg_chknbit_hpet\r
428#define B_PCH_ILB_DEF1_ECWS BIT6 // 8254 Early CW Select\r
429#define B_PCH_ILB_DEF1_FOF BIT5 // 8254 Freeze on first on 1st rd wr11\r
430#define B_PCH_ILB_DEF1_FOAR BIT4 // 8254 Freeze_On_AnyRead\r
431#define B_PCH_ILB_DEF1_LMOO BIT3 // 8259 L2L0_Match_On_OCW2\r
432#define B_PCH_ILB_DEF1_DFP BIT2 // 8259 Disable_Freeze_Priority\r
433#define B_PCH_ILB_DEF1_EETI BIT1 // 8259 Extend_EdgeTrig_IRQ\r
434#define B_PCH_ILB_DEF1_DSAEOI BIT0 // 8259 Disable_Slave_AEOI\r
435\r
436#define R_PCH_ILB_GNMI 0x80 // NMI Register\r
437#define S_PCH_ILB_GNMI 4\r
438#define B_PCH_ILB_GNMI_NMI2SMIEN BIT6 // NMI to SMI Enable\r
439#define N_PCH_ILB_GNMI_NMI2SMIEN 6\r
440#define B_PCH_ILB_GNMI_NMI2SMIST BIT5 // NMI to SMI Status\r
441#define N_PCH_ILB_GNMI_NMI2SMIST 5\r
442#define B_PCH_ILB_GNMI_NMIN BIT4 // NMI NOW\r
443#define B_PCH_ILB_GNMI_NMINS BIT3 // NMI NOW Status\r
444#define B_PCH_ILB_GNMI_GNMIED BIT2 // GPIO NMI Edge Detection\r
445#define B_PCH_ILB_GNMI_GNMIE BIT1 // GPIO NMI Enable\r
446#define B_PCH_ILB_GNMI_GNMIS BIT0 // GPIO NMI Status\r
447\r
448#define R_PCH_ILB_LPCC 0x84 // LPC Control\r
449#define B_PCH_ILB_LPCC_LPCCLK_SLC BIT8 // iLPCCLK Mux Select\r
450#define B_PCH_ILB_LPCC_LPCCLK_FORCE_OFF BIT3\r
451#define B_PCH_ILB_LPCC_CLKRUN_EN BIT2 // LPC CLKRUN Protocol Enable\r
452#define B_PCH_ILB_LPCC_LPCCLK1EN BIT1 // Clock 1 Enable\r
453#define B_PCH_ILB_LPCC_LPCCLK0EN BIT0 // Clock 0 Enable\r
454\r
455#define R_PCH_ILB_IRQE 0x88 // IRQ Enable Control\r
456#define B_PCH_ILB_IRQE_IRQ4TO7EN (BIT7 | BIT6 | BIT5 | BIT4) // IRQ4 - IRQ7 Enable\r
457#define B_PCH_ILB_IRQE_UARTIRQEN_IRQ3 BIT3 // UART IRQ3 Enable\r
458\r
459//\r
460// ACPI and Legacy I/O Registers (ABASE)\r
461//\r
462#define R_PCH_ACPI_PM1_STS 0x00 // Power Management 1 Status\r
463#define S_PCH_ACPI_PM1_STS 2\r
464#define B_PCH_ACPI_PM1_STS_WAK BIT15 // Wake Status\r
465#define B_PCH_ACPI_PM1_STS_WAK_PCIE0 BIT14 // PCI Express 0 Wake Status\r
466#define B_PCH_ACPI_PM1_STS_USB_CLKLESS BIT13 // USB Clockless Status\r
467#define B_PCH_ACPI_PM1_STS_PRBTNOR BIT11 // Power Button Override Status\r
468#define B_PCH_ACPI_PM1_STS_RTC BIT10 // RTC Status\r
469#define B_PCH_ACPI_PM1_STS_PWRBTN BIT8 // Power Button Status\r
470#define B_PCH_ACPI_PM1_STS_GBL BIT5 // Global Status\r
471#define B_PCH_ACPI_PM1_STS_WAK_PCIE3 BIT4 // PCI Express 3 Wake Status\r
472#define B_PCH_ACPI_PM1_STS_WAK_PCIE2 BIT3 // PCI Express 2 Wake Status\r
473#define B_PCH_ACPI_PM1_STS_WAK_PCIE1 BIT2 // PCI Express 1 Wake Status\r
474#define B_PCH_ACPI_PM1_STS_TMROF BIT0 // Timer Overflow Status\r
475#define N_PCH_ACPI_PM1_STS_WAK 15\r
476#define N_PCH_ACPI_PM1_STS_PRBTNOR 11\r
477#define N_PCH_ACPI_PM1_STS_RTC 10\r
478#define N_PCH_ACPI_PM1_STS_PWRBTN 8\r
479#define N_PCH_ACPI_PM1_STS_GBL 5\r
480#define N_PCH_ACPI_PM1_STS_TMROF 0\r
481\r
482#define R_PCH_ACPI_PM1_EN 0x02 // Power Management 1 Enables\r
483#define S_PCH_ACPI_PM1_EN 2\r
484#define B_PCH_ACPI_PM1_WAK_DIS_PCIE0 BIT14 // PCI Express 0 Disable\r
485#define B_PCH_ACPI_PM1_EN_USB_CLKLESS BIT13 // USB Clockless Enable Bit\r
486#define B_PCH_ACPI_PM1_EN_RTC BIT10 // RTC Alarm Enable Bit\r
487#define B_PCH_ACPI_PM1_EN_PWRBTN BIT8 // Power Button Enable Bit\r
488#define B_PCH_ACPI_PM1_EN_GBL BIT5 // Global Enable Bit\r
489#define B_PCH_ACPI_PM1_WAK_DIS_PCIE3 BIT4 // PCI Express 3 Disable\r
490#define B_PCH_ACPI_PM1_WAK_DIS_PCIE2 BIT3 // PCI Express 2 Disable\r
491#define B_PCH_ACPI_PM1_WAK_DIS_PCIE1 BIT2 // PCI Express 1 Disable\r
492#define B_PCH_ACPI_PM1_EN_TMROF BIT0 // Timer Overflow Interrupt Enable Bit\r
493#define N_PCH_ACPI_PM1_EN_RTC 10\r
494#define N_PCH_ACPI_PM1_EN_PWRBTN 8\r
495#define N_PCH_ACPI_PM1_EN_GBL 5\r
496#define N_PCH_ACPI_PM1_EN_TMROF 0\r
497\r
498#define R_PCH_ACPI_PM1_CNT 0x04 // Power Management 1 Control\r
499#define S_PCH_ACPI_PM1_CNT 4\r
500#define B_PCH_ACPI_PM1_CNT_SLP_EN BIT13 // Sleep enable\r
501#define B_PCH_ACPI_PM1_CNT_SLP_TYP (BIT12 | BIT11 | BIT10) // Sleep Type\r
502#define V_PCH_ACPI_PM1_CNT_S0 0x00000000 // ON (S0)\r
503#define V_PCH_ACPI_PM1_CNT_S1 0x00000400 // Puts CPU in S1 state (S1)\r
504#define V_PCH_ACPI_PM1_CNT_S3 0x00001400 // Suspend-to-RAM (S3)\r
505#define V_PCH_ACPI_PM1_CNT_S4 0x00001800 // Suspend-to-Disk (S4)\r
506#define V_PCH_ACPI_PM1_CNT_S5 0x00001C00 // Soft Off (S5)\r
507#define B_PCH_ACPI_PM1_CNT_GBL_RLS BIT2\r
508#define B_PCH_ACPI_PM1_CNT_BM_RLD BIT1 // Treated as Scratchpad Bit\r
509#define B_PCH_ACPI_PM1_CNT_SCI_EN BIT0 // SCI Enable\r
510\r
511#define R_PCH_ACPI_PM1_TMR 0x08 // Power Management 1 Timer\r
512#define B_PCH_ACPI_PM1_TMR_VAL 0xFFFFFF // The timer value mask\r
513#define V_PCH_ACPI_PM1_TMR_MAX_VAL 0x1000000 // The timer is 24 bit overflow\r
514#define V_PCH_ACPI_PM1_TMR_FREQUENCY 3579545 // Timer Frequency\r
515#define V_PCH_ACPI_PM1_TMR_NUM_BITS 24 // Programmed to 24 not 32\r
516#define V_PCH_ACPI_PM1_TMR_MAX_BITS 32\r
517\r
518#define R_PCH_ACPI_GPE0a_STS 0x20 // General Purpose Event 0a Status\r
519#define S_PCH_ACPI_GPE0a_STS 4\r
520#define B_PCH_ACPI_GPE0a_STS_CORE_GPIO 0xFF000000 // CORE GPIO Status\r
521#define B_PCH_ACPI_GPE0a_STS_SUS_GPIO 0x00FF0000 // SUS GPIO Status\r
522#define B_PCH_ACPI_GPE0a_STS_PME_B0 BIT13 // Power Management Event Bus 0 Status\r
523#define B_PCH_ACPI_GPE0a_STS_BATLOW BIT10 // Battery Low Status\r
524#define B_PCH_ACPI_GPE0a_STS_PCI_EXP BIT9 // PCI Express Status\r
525#define B_PCH_ACPI_GPE0a_STS_GUNIT_SCI BIT5 // GUNIT SCI Status\r
526#define B_PCH_ACPI_GPE0a_STS_PUNIT_SCI BIT4 // PUNIT SCI Status\r
527#define B_PCH_ACPI_GPE0a_STS_SWGPE BIT2 // Software GPE Status\r
528#define B_PCH_ACPI_GPE0a_STS_HOT_PLUG BIT1 // Hot Plug Status\r
529#define N_PCH_ACPI_GPE0a_STS_PME_B0 13\r
530#define N_PCH_ACPI_GPE0a_STS_BATLOW 10\r
531#define N_PCH_ACPI_GPE0a_STS_PCI_EXP 9\r
532#define N_PCH_ACPI_GPE0a_STS_GUNIT_SCI 5\r
533#define N_PCH_ACPI_GPE0a_STS_PUNIT_SCI 4\r
534#define N_PCH_ACPI_GPE0a_STS_SWGPE 2\r
535#define N_PCH_ACPI_GPE0a_STS_HOT_PLUG 1\r
536\r
537#define R_PCH_ACPI_GPE0a_EN 0x28 // General Purpose Event 0a Enables\r
538#define S_PCH_ACPI_GPE0a_EN 4\r
539#define B_PCH_ACPI_GPE0a_EN_CORE_GPIO 0xFF000000 // CORE GPIO Enable\r
540#define B_PCH_ACPI_GPE0a_EN_SUS_GPIO 0x00FF0000 // SUS GPIO Enable\r
541#define B_PCH_ACPI_GPE0a_EN_PME_B0 BIT13 // Power Management Event Bus 0 Enable\r
542#define B_PCH_ACPI_GPE0a_EN_BATLOW BIT10 // Battery Low Enable\r
543#define B_PCH_ACPI_GPE0a_EN_PCI_EXP BIT9 // PCI Express Enable\r
544#define B_PCH_ACPI_GPE0a_EN_SWGPE BIT2 // Software GPE Enable\r
545#define B_PCH_ACPI_GPE0a_EN_HOT_PLUG BIT1 // Hot Plug Enable\r
546#define N_PCH_ACPI_GPE0a_EN_PME_B0 13\r
547#define N_PCH_ACPI_GPE0a_EN_BATLOW 10\r
548#define N_PCH_ACPI_GPE0a_EN_PCI_EXP 9\r
549#define N_PCH_ACPI_GPE0a_EN_SWGPE 2\r
550#define N_PCH_ACPI_GPE0a_EN_HOT_PLUG 1\r
551\r
552#define R_PCH_SMI_EN 0x30 // SMI Control and Enable\r
553#define S_PCH_SMI_EN 4\r
554#define B_PCH_SMI_EN_LEGACY_USB3 BIT31 // Legacy USB 3 Enable\r
555#define B_PCH_SMI_EN_INTEL_USB2 BIT18 // Intel USB 2 Enable\r
556#define B_PCH_SMI_EN_LEGACY_USB2 BIT17 // Legacy USB 2 Enable\r
557#define B_PCH_SMI_EN_PERIODIC BIT14 // Periodic Enable\r
558#define B_PCH_SMI_EN_TCO BIT13 // TCO Enable\r
559#define B_PCH_SMI_EN_BIOS_RLS BIT7 // BIOS RLS\r
560#define B_PCH_SMI_EN_SWSMI_TMR BIT6 // Software SMI Timer Enable\r
561#define B_PCH_SMI_EN_APMC BIT5 // APMC Enable\r
562#define B_PCH_SMI_EN_ON_SLP_EN BIT4 // SMI On Sleep Enable\r
563#define B_PCH_SMI_EN_BIOS BIT2 // BIOS Enable\r
564#define B_PCH_SMI_EN_EOS BIT1 // End of SMI\r
565#define B_PCH_SMI_EN_GBL_SMI BIT0 // Global SMI Enable\r
566#define N_PCH_SMI_EN_LEGACY_USB3 31\r
567#define N_PCH_SMI_EN_GPIO_UNLOCK 27\r
568#define N_PCH_SMI_EN_INTEL_USB2 18\r
569#define N_PCH_SMI_EN_LEGACY_USB2 17\r
570#define N_PCH_SMI_EN_PERIODIC 14\r
571#define N_PCH_SMI_EN_TCO 13\r
572#define N_PCH_SMI_EN_BIOS_RLS 7\r
573#define N_PCH_SMI_EN_SWSMI_TMR 6\r
574#define N_PCH_SMI_EN_APMC 5\r
575#define N_PCH_SMI_EN_ON_SLP_EN 4\r
576#define N_PCH_SMI_EN_BIOS 2\r
577#define N_PCH_SMI_EN_EOS 1\r
578#define N_PCH_SMI_EN_GBL_SMI 0\r
579\r
580#define R_PCH_SMI_STS 0x34 // SMI Status Register\r
581#define S_PCH_SMI_STS 4\r
582#define B_PCH_SMI_STS_LEGACY_USB3 BIT31 // Legacy USB 3 Status\r
583#define B_PCH_SMI_STS_GUNIT_SMI BIT29 // GUNIT SMI Status\r
584#define B_PCH_SMI_STS_PUNIT_SMI BIT28 // PUNIT SMI Status\r
585#define B_PCH_SMI_STS_SPI BIT26 // SPI SMI Status\r
586#define B_PCH_SMI_STS_PCI_EXP BIT20 // PCI Express SMI Status\r
587#define B_PCH_SMI_STS_INTEL_USB2 BIT18 // Intel USB 2 Status\r
588#define B_PCH_SMI_STS_LEGACY_USB2 BIT17 // Legacy USB 2 Status\r
589#define N_PCH_SMI_STS_TCO 13\r
590#define B_PCH_SMI_STS_SMBUS BIT16 // SMBUS SMI Status\r
591#define B_PCH_SMI_STS_ILB BIT15 // ILB SMI Status\r
592#define B_PCH_SMI_STS_PERIODIC BIT14 // Periodic Status\r
593#define B_PCH_SMI_STS_TCO BIT13 // TCO Status\r
594#define B_PCH_SMI_STS_GPE0 BIT9 // GPE0 Status\r
595#define B_PCH_SMI_STS_PM1_STS_REG BIT8 // PM1 Status Register\r
596#define B_PCH_SMI_STS_SWSMI_TMR BIT6 // Software SMI Timer Status\r
597#define B_PCH_SMI_STS_APM BIT5 // APM Status\r
598#define B_PCH_SMI_STS_ON_SLP_EN BIT4 // SMI On Sleep Enable Status\r
599#define B_PCH_SMI_STS_BIOS BIT2 // BIOS Status\r
600#define N_PCH_SMI_STS_LEGACY_USB3 31\r
601#define N_PCH_SMI_STS_SPI 26\r
602#define N_PCH_SMI_STS_PCI_EXP 20\r
603#define N_PCH_SMI_STS_INTEL_USB2 18\r
604#define N_PCH_SMI_STS_LEGACY_USB2 17\r
605#define N_PCH_SMI_STS_SMBUS 16\r
606#define N_PCH_SMI_STS_ILB 15\r
607#define N_PCH_SMI_STS_PERIODIC 14\r
608#define N_PCH_SMI_STS_TCO 13\r
609#define N_PCH_SMI_STS_GPE0 9\r
610#define N_PCH_SMI_STS_PM1_STS_REG 8\r
611#define N_PCH_SMI_STS_SWSMI_TMR 6\r
612#define N_PCH_SMI_STS_APM 5\r
613#define N_PCH_SMI_STS_ON_SLP_EN 4\r
614#define N_PCH_SMI_STS_BIOS 2\r
615\r
616#define R_PCH_ALT_GP_SMI_EN 0x38 // Alternate GPI SMI Enable\r
617#define S_PCH_ALT_GP_SMI_EN 2\r
618#define B_PCH_ALT_GP_SMI_EN_CORE_GPIO 0xFF00 // SUS GPIO SMI Enable\r
619#define B_PCH_ALT_GP_SMI_EN_SUS_GPIO 0x00FF // CORE GPIO SMI Enable\r
620\r
621#define R_PCH_ALT_GP_SMI_STS 0x3A // Alternate GPI SMI Status\r
622#define S_PCH_ALT_GP_SMI_STS 2\r
623#define B_PCH_ALT_GP_SMI_STS_CORE_GPIO 0xFF00 // SUS GPIO SMI Status\r
624#define B_PCH_ALT_GP_SMI_STS_SUS_GPIO 0x00FF // CORE GPIO SMI Status\r
625\r
626#define R_PCH_UPRWC 0x3C // USB Per-Port Registers Write Control\r
627#define S_PCH_UPRWC 2\r
628#define B_PCH_UPRWC_WR_EN_SMI_STS BIT8 // Write Enable Status\r
629#define B_PCH_UPRWC_WR_EN BIT1 // USB Per-Port Registers Write Enable\r
630#define B_PCH_UPRWC_WR_EN_SMI_EN BIT0 // Write Enable SMI Enable\r
631\r
632#define R_PCH_ACPI_GPE_CNTL 0x40 // General Purpose Event Control\r
633#define B_PCH_ACPI_GPE_CNTL_SWGPE_CTRL BIT17 // Software GPE Control\r
634#define B_PCH_ACPI_GPE_CNTL_PCIE3_SCI_EN BIT3\r
635#define B_PCH_ACPI_GPE_CNTL_PCIE2_SCI_EN BIT2\r
636#define B_PCH_ACPI_GPE_CNTL_PCIE1_SCI_EN BIT1\r
637#define B_PCH_ACPI_GPE_CNTL_PCIE0_SCI_EN BIT0\r
638\r
639#define R_PCH_ACPI_PM2_CNT 0x50 // PM2a Control Block\r
640#define B_PCH_ACPI_PM2_CNT_ARB_DIS BIT0 // Scratchpad Bit\r
641\r
642#define R_PCH_TCO_RLD 0x60 // TCO Reload\r
643#define B_PCH_TCO_RLD_VAL 0x3FF // TCO Timer Count Value\r
644\r
645#define R_PCH_TCO_STS 0x64 // TCO Timer Status\r
646#define S_PCH_TCO_STS 4\r
647#define B_PCH_TCO_STS_SECOND_TO BIT17 // Second Timeout Status\r
648#define B_PCH_TCO_STS_TIMEOUT BIT3 // Timeout\r
649#define N_PCH_TCO_STS_TIMEOUT 3\r
650\r
651#define R_PCH_TCO_CNT 0x68 // TCO Control\r
652#define S_PCH_TCO_CNT 2\r
653#define B_PCH_TCO_CNT_OS_POLICY (BIT21 | BIT20) // OS Policy\r
654#define B_PCH_TCO_CNT_LOCK BIT12 // TCO Enable Lock\r
655#define B_PCH_TCO_CNT_TMR_HLT BIT11 // TCO Timer Halt\r
656\r
657#define R_PCH_TCO_TMR 0x70 // TCO Timer\r
658#define B_PCH_TCO_TMR_TCO_TRLD 0x3FF0000\r
659\r
660//\r
661// PMC Memory Space Registers (PBASE)\r
662//\r
663#define R_PCH_PMC_PRSTS 0x00 // Power and Reset Status\r
664#define B_PCH_PMC_PRSTS_PRODID 0xFF000000 // Power Management Controller Product ID\r
665#define B_PCH_PMC_PRSTS_REVID 0x00FF0000 // Power Management Controller Revision ID\r
666#define B_PCH_PMC_PRSTS_PM_WD_TMR BIT15 // PMC Watchdog Timer Status\r
667#define B_PCH_PMC_PRSTS_CODE_COPIED_STS BIT11 // Patch Copied Over Status\r
668#define B_PCH_PMC_PRSTS_CODE_LOAD_TO BIT9 // Patch Load Timeout Status\r
669#define B_PCH_PMC_PRSTS_OP_STS BIT8 // PMC Operational Status\r
670#define B_PCH_PMC_PRSTS_SEC_GBLRST_STS BIT7 // SEC Global Reset Status\r
671#define B_PCH_PMC_PRSTS_SEC_WD_TMR_STS BIT6 // SEC Watchdog Timer Status\r
672#define B_PCH_PMC_PRSTS_WOL_OVR_WK_STS BIT5 // Wake On LAN Override Wake Status\r
673#define B_PCH_PMC_PRSTS_HOST_WAKE_STS BIT4 // PMC Host Wake Status\r
674\r
675#define R_PCH_PMC_PM_CFG 0x08 // Power Management Configuration\r
676#define B_PCH_PMC_PM_CFG_SPS BIT5 // Shutdown Policy Select\r
677#define B_PCH_PMC_PM_CFG_NO_REBOOT BIT4 // No Reboot Strap\r
678#define B_PCH_PMC_PM_CFG_SX_ENT_TO_EN BIT3 // S1 / 3 / 4 / 5 Entry Timeout Enable\r
679#define B_PCH_PMC_PM_CFG_TIMING_T581 (BIT1 | BIT0) // Timing t581\r
680\r
681#define R_PCH_PMC_PM_STS 0x0C // Power Management Status\r
682#define B_PCH_PMC_PM_STS_PMC_MSG_FULL BIT24 // PMC Message Full Status\r
683#define B_PCH_PMC_PM_STS_PMC_MSG_4_FULL BIT23 // PMC 4 Message Full Status\r
684#define B_PCH_PMC_PM_STS_PMC_MSG_3_FULL BIT22 // PMC 3 Message Full Status\r
685#define B_PCH_PMC_PM_STS_PMC_MSG_2_FULL BIT21 // PMC 2 Message Full Status\r
686#define B_PCH_PMC_PM_STS_PMC_MSG_1_FULL BIT20 // PMC 1 Message Full Status\r
687#define B_PCH_PMC_PM_STS_CODE_REQ BIT8 // Patch Request Status\r
688#define B_PCH_PMC_PM_STS_HPR_ENT_TO BIT2 // Host partition Reset Entry Timeout Status\r
689#define B_PCH_PMC_PM_STS_SX_ENT_TO BIT1 // S3 / 4 / 5 Entry Timeout Status\r
690\r
691#define R_PCH_PMC_MTPMC 0x10 // Message to PMC\r
692\r
693#define R_PCH_PMC_GEN_PMCON_1 0x20 // General PM Configuration 1\r
694#define B_PCH_PMC_GEN_PMCON_UART_EN BIT24 // UART Debug Port Enable\r
695#define B_PCH_PMC_GEN_PMCON_DRAM_INIT BIT23 // DRAM Initialization Scratchpad Bit\r
696#define B_PCH_PMC_GEN_PMCON_MEM_SR BIT21 // Memory Placed in Self-Refresh\r
697#define B_PCH_PMC_GEN_PMCON_SRS BIT20 // System Reset Status\r
698#define B_PCH_PMC_GEN_PMCON_CTS BIT19 // CPU Thermal Trip Status\r
699#define B_PCH_PMC_GEN_PMCON_MIN_SLP_S4 BIT18 // Minimum SLP_S4# Assertion Width Violation Status\r
700#define B_PCH_PMC_GEN_PMCON_PWROK_FLR BIT16 // PWROK Failure\r
701#define B_PCH_PMC_GEN_PMCON_PME_B0_S5_DIS BIT15 // PME B0 S5 Disable\r
702#define B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR BIT14 // SUS Well Power Failure\r
703#define B_PCH_PMC_GEN_PMCON_WOL_ENABLE_OVERRIDE BIT13 // WOL Enable Override\r
704#define B_PCH_PMC_GEN_PMCON_DISABLE_SX_STRETCH BIT12 // Disable SLP_X Scretching After SUS Well Power Up\r
705#define B_PCH_PMC_GEN_PMCON_SLP_S3_MAW (BIT11 | BIT10) // SLP_S3# Minimum Assertion Width\r
706#define V_PCH_PMC_GEN_PMCON_SLP_S3_MAW_60US 0x000 // 60 micro seconds\r
707#define V_PCH_PMC_GEN_PMCON_SLP_S3_MAW_1MS 0x400 // 1 milli second\r
708#define V_PCH_PMC_GEN_PMCON_SLP_S3_MAW_50MS 0x800 // 50 milli seconds\r
709#define V_PCH_PMC_GEN_PMCON_SLP_S3_MAW_2S 0xC00 // 2 seconds\r
710#define B_PCH_PMC_GEN_PMCON_GEN_RST_STS BIT9 // General Reset Status\r
711#define B_PCH_PMC_GEN_PMCON_RTC_RESERVED BIT8 // RTC Reserved\r
712#define B_PCH_PMC_GEN_PMCON_SWSMI_RTSL (BIT7 | BIT6) // SWSMI Rate Select\r
713#define V_PCH_PMC_GEN_PMCON_SWSMI_RTSL_64MS 0xC0 // 64ms +/- 4ms\r
714#define V_PCH_PMC_GEN_PMCON_SWSMI_RTSL_32MS 0x80 // 32ms +/- 4ms\r
715#define V_PCH_PMC_GEN_PMCON_SWSMI_RTSL_16MS 0x40 // 16ms +/- 4ms\r
716#define V_PCH_PMC_GEN_PMCON_SWSMI_RTSL_1_5MS 0x00 // 1.5ms +/- 0.6ms\r
717#define B_PCH_PMC_GEN_PMCON_SLP_S4_MAW (BIT5 | BIT4) // SLP_S4# Minimum Assertion Width\r
718#define V_PCH_PMC_GEN_PMCON_SLP_S4_MAW_1S 0x30 // 1 second\r
719#define V_PCH_PMC_GEN_PMCON_SLP_S4_MAW_2S 0x20 // 2 seconds\r
720#define V_PCH_PMC_GEN_PMCON_SLP_S4_MAW_3S 0x10 // 3 seconds\r
721#define V_PCH_PMC_GEN_PMCON_SLP_S4_MAW_4S 0x00 // 4 seconds\r
722#define B_PCH_PMC_GEN_PMCON_SLP_S4_ASE BIT3 // SLP_S4# Assertion Scretch Enable\r
723#define B_PCH_PMC_GEN_PMCON_RTC_PWR_STS BIT2 // RTC Power Status\r
724#define B_PCH_PMC_GEN_PMCON_AFTERG3_EN BIT0 // After G3 State Enable\r
725\r
726#define R_PCH_PMC_GEN_PMCON_2 0x24 // General PM Configuration 2\r
727#define B_PCH_PMC_GEN_PMCON_LOCK_S4_STRET_LD BIT18 // SLP_S3 / SLP_S4 Stretching Policy Lock-Down\r
728#define B_PCH_PMC_GEN_PMCON_BIOS_PCI_EXP_EN BIT10 // BIOS PCI Express Enable\r
729#define B_PCH_PMC_GEN_PMCON_PWRBTN_LVL BIT9 // Power Button Level\r
730#define B_PCH_PMC_GEN_PMCON_SMI_LOCK BIT4 // SMI Lock\r
731#define B_PCH_PMC_GEN_PMCON_PER_SMI_SEL (BIT1 | BIT0) // Period SMI Select\r
732#define V_PCH_PMC_GEN_PMCON_PER_SMI_64S 0x0000 // 64 seconds\r
733#define V_PCH_PMC_GEN_PMCON_PER_SMI_32S 0x0001 // 32 seconds\r
734#define V_PCH_PMC_GEN_PMCON_PER_SMI_16S 0x0002 // 16 seconds\r
735#define V_PCH_PMC_GEN_PMCON_PER_SMI_8S 0x0003 // 8 seconds\r
736\r
737#define R_PCH_PMC_MFPMC 0x28 // Message from PMC\r
738\r
739#define R_PCH_PMC_SEC_STS 0x2C // SEC Status\r
740#define B_PCH_PMC_SEC_STS_SEC (BIT3 | BIT2 | BIT1 | BIT0) // SEC Exclusion Cause\r
741\r
742#define R_PCH_PMC_CRID 0x30 // Configured Revision ID\r
743#define B_PCH_PMC_CRID_RID_SEL (BIT1 | BIT0) // Revision ID Select\r
744\r
745#define R_PCH_PMC_FUNC_DIS 0x34 // Function Disable Register\r
746#define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC7 BIT31 // LPSS2 I2C #7\r
747#define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC6 BIT30 // LPSS2 I2C #6\r
748#define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC5 BIT29 // LPSS2 I2C #5\r
749#define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC4 BIT28 // LPSS2 I2C #4\r
750#define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC3 BIT27 // LPSS2 I2C #3\r
751#define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC2 BIT26 // LPSS2 I2C #2\r
752#define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC1 BIT25 // LPSS2 I2C #1\r
753#define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC0 BIT24 // LPSS2 DMA Disable\r
754#define B_PCH_PMC_FUNC_DIS_PCI_EX_FUNC3 BIT23 // PCI Express Function 3 Disable\r
755#define B_PCH_PMC_FUNC_DIS_PCI_EX_FUNC2 BIT22 // PCI Express Function 2 Disable\r
756#define B_PCH_PMC_FUNC_DIS_PCI_EX_FUNC1 BIT21 // PCI Express Function 1 Disable\r
757#define B_PCH_PMC_FUNC_DIS_PCI_EX_FUNC0 BIT20 // PCI Express Function 0 Disable\r
758#define N_PCH_PMC_FUNC_DIS_PCI_EX_FUNC0 20\r
759#define B_PCH_PMC_FUNC_DIS_SEC BIT19 // SEC Disable\r
760#define B_PCH_PMC_FUNC_DIS_USB BIT18 // USB Disable\r
761#define B_PCH_PMC_FUNC_DIS_SATA BIT17 // SATA Disable\r
762#define B_PCH_PMC_FUNC_DIS_USH BIT15 // USH (USB3) Disable\r
763#define B_PCH_PMC_FUNC_DIS_OTG BIT14 // USB OTG Disable\r
764#define B_PCH_PMC_FUNC_DIS_LPE BIT13 // LPE Disable\r
765#define B_PCH_PMC_FUNC_DIS_AZALIA BIT12 // Azalia Disable\r
766#define B_PCH_PMC_FUNC_DIS_MIPI BIT11 // MIPI-HSI Disable\r
767#define B_PCH_PMC_FUNC_DIS_SDIO4 BIT11 // SCC SDIO #4 (Device 23, eMMC4.5) Disable\r
768#define B_PCH_PMC_FUNC_DIS_SDIO3 BIT10 // SCC SDIO #3 (Device 18, SD Card) Disable\r
769#define B_PCH_PMC_FUNC_DIS_SDIO2 BIT9 // SCC SDIO #2 (Device 17, SDIO) Disable\r
770#define B_PCH_PMC_FUNC_DIS_SDIO1 BIT8 // SCC SDIO #1 (Device 16, eMMC) Disable\r
771#define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC7 BIT7 // LPSS1 Spare #2 Disable\r
772#define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC6 BIT6 // LPSS1 Spare #1 Disable\r
773#define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC5 BIT5 // LPSS1 SPI Disable\r
774#define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC4 BIT4 // LPSS1 HS-UART #2 Disable\r
775#define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC3 BIT3 // LPSS1 HS-UART #1 Disable\r
776#define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC2 BIT2 // LPSS1 PWM #2 Disable\r
777#define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC1 BIT1 // LPSS1 PWM #1 Disable\r
778#define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC0 BIT0 // LPSS1 DMA Disable\r
779\r
780#define R_PCH_PMC_FUNC_DIS2 0x38 // Function Disable 2 Register\r
781#define B_PCH_PMC_FUNC_DIS2_USH_SS_PHY BIT2 // USH Super Speed PHY Disable\r
782#define B_PCH_PMC_FUNC_DIS2_OTG_SS_PHY BIT1 // OTG Super Speed PHY Disable\r
783#define B_PCH_PMC_FUNC_DIS2_SMBUS BIT0 // SMBus Disable\r
784\r
785#define R_PCH_PMC_PMIR 0x48 // Extended Test Mode Register (ETR)\r
786#define B_PCH_PMC_PMIR_CF9LOCK BIT31 // CF9h Lockdown\r
787#define B_PCH_PMC_PMIR_LTR_DEF BIT22 // LTR Default\r
788#define B_PCH_PMC_PMIR_IGNORE_HPET BIT21 // Ignore HPET Disable Check Before Going to S0i2\r
789#define B_PCH_PMC_PMIR_CF9GR BIT20 // CF9h Global Reset\r
790\r
791#define R_PCH_PMC_VLT 0x50 // Voltage Detect Register\r
792#define B_PCH_PMC_VLT_FUSES 0xFF // Voltage Detect Fuses\r
793\r
794#define R_PCH_PMC_GPI_ROUT 0x58 // GPI Rout\r
795#define B_PCH_PMC_GPI_ROUT_0 (BIT1 | BIT0)\r
796#define B_PCH_PMC_GPI_ROUT_1 (BIT3 | BIT2)\r
797#define B_PCH_PMC_GPI_ROUT_2 (BIT5 | BIT4)\r
798#define B_PCH_PMC_GPI_ROUT_3 (BIT7 | BIT6)\r
799#define B_PCH_PMC_GPI_ROUT_4 (BIT9 | BIT8)\r
800#define B_PCH_PMC_GPI_ROUT_5 (BIT11 | BIT10)\r
801#define B_PCH_PMC_GPI_ROUT_6 (BIT13 | BIT12)\r
802#define B_PCH_PMC_GPI_ROUT_7 (BIT15 | BIT14)\r
803#define B_PCH_PMC_GPI_ROUT_8 (BIT17 | BIT16)\r
804#define B_PCH_PMC_GPI_ROUT_9 (BIT19 | BIT18)\r
805#define B_PCH_PMC_GPI_ROUT_10 (BIT21 | BIT20)\r
806#define B_PCH_PMC_GPI_ROUT_11 (BIT23 | BIT22)\r
807#define B_PCH_PMC_GPI_ROUT_12 (BIT25 | BIT24)\r
808#define B_PCH_PMC_GPI_ROUT_13 (BIT27 | BIT26)\r
809#define B_PCH_PMC_GPI_ROUT_14 (BIT29 | BIT28)\r
810#define B_PCH_PMC_GPI_ROUT_15 (BIT31 | BIT30)\r
811\r
812#define R_PCH_PMC_PCC0 0x60 // Platform Clock Control 0\r
813#define B_PCH_PMC_PCC0_CLK_FREQ BIT2 // Clock Frequency\r
814#define B_PCH_PMC_PCC0_CLK_CTL (BIT1 | BIT0) // Clock Gating\r
815\r
816#define R_PCH_PMC_PCC1 0x64 // Platform Clock Control 1\r
817#define B_PCH_PMC_PCC1_CLK_FREQ BIT2 // Clock Frequency\r
818#define B_PCH_PMC_PCC1_CLK_CTL (BIT1 | BIT0) // Clock Gating\r
819\r
820#define R_PCH_PMC_PCC2 0x68 // Platform Clock Control 2\r
821#define B_PCH_PMC_PCC2_CLK_FREQ BIT2 // Clock Frequency\r
822#define B_PCH_PMC_PCC2_CLK_CTL (BIT1 | BIT0) // Clock Gating\r
823\r
824#define R_PCH_PMC_PCC3 0x6C // Platform Clock Control 3\r
825#define B_PCH_PMC_PCC3_CLK_FREQ BIT2 // Clock Frequency\r
826#define B_PCH_PMC_PCC3_CLK_CTL (BIT1 | BIT0) // Clock Gating\r
827\r
828#define R_PCH_PMC_PCC4 0x70 // Platform Clock Control 4\r
829#define B_PCH_PMC_PCC4_CLK_FREQ BIT2 // Clock Frequency\r
830#define B_PCH_PMC_PCC4_CLK_CTL (BIT1 | BIT0) // Clock Gating\r
831\r
832#define R_PCH_PMC_PCC5 0x74 // Platform Clock Control 5\r
833#define B_PCH_PMC_PCC5_CLK_FREQ BIT2 // Clock Frequency\r
834#define B_PCH_PMC_PCC5_CLK_CTL (BIT1 | BIT0) // Clock Gating\r
835\r
836#define R_PCH_PMC_S0IR_TMR 0x80 // S0I Ready Residency Timer\r
837#define B_PCH_PMC_S0IR_TMR_RTIME 0xFFFFFFFF // Time Spent in S0I Ready State\r
838\r
839#define R_PCH_PMC_S0I1_TMR 0x84 // S0I1 Ready Residency Timer\r
840#define B_PCH_PMC_S0I1_TMR_RTIME 0xFFFFFFFF // Time Spent in S0I1 Ready State\r
841\r
842#define R_PCH_PMC_S0I2_TMR 0x88 // S0I2 Ready Residency Timer\r
843#define B_PCH_PMC_S0I2_TMR_RTIME 0xFFFFFFFF // Time Spent in S0I2 Ready State\r
844\r
845#define R_PCH_PMC_S0I3_TMR 0x8C // S0I3 Ready Residency Timer\r
846#define B_PCH_PMC_S0I3_TMR_RTIME 0xFFFFFFFF // Time Spent in S0I3 Ready State\r
847\r
848#define R_PCH_PMC_S0_TMR 0x90 // S0 Residency Timer\r
849#define B_PCH_PMC_S0_TMR_RTIME 0xFFFFFFFF // Time Spent in S0 State\r
850\r
851#define R_PCH_PMC_PSS 0x98 // Power Island Power Status\r
852#define B_PCH_PMC_PSS_PG_STS 0x3FFFF // Power Gate Status of All Power Islands\r
853#define B_PCH_PMC_PSS_PG_STS_USB_SUS BIT17 // USB SUS\r
854#define B_PCH_PMC_PSS_PG_STS_USB BIT16 // USB\r
855#define B_PCH_PMC_PSS_PG_STS_OTG_VCCACLK BIT15 // OTG VCCACLK\r
856#define B_PCH_PMC_PSS_PG_STS_OTG VCCA BIT14 // OTG VCCA\r
857#define B_PCH_PMC_PSS_PG_STS_OTG_VCCS BIT13 // OTG VCCS\r
858#define B_PCH_PMC_PSS_PG_STS_OTG_CTL BIT12 // OTG Control\r
859#define B_PCH_PMC_PSS_PG_STS_USH_VCCA BIT11 // USH VCCA\r
860#define B_PCH_PMC_PSS_PG_STS_USH_VCCS BIT10 // USH VCCS\r
861#define B_PCH_PMC_PSS_PG_STS_USH_SUS BIT9 // USH SUS\r
862#define B_PCH_PMC_PSS_PG_STS_USH_CTL BIT8 // USH Control\r
863#define B_PCH_PMC_PSS_PG_STS_DFX BIT7 // DFX\r
864#define B_PCH_PMC_PSS_PG_STS_LPE BIT6 // LPE Audio\r
865#define B_PCH_PMC_PSS_PG_STS_LPSS BIT5 // LPSS\r
866#define B_PCH_PMC_PSS_PG_STS_PCIE BIT4 // PCIe\r
867#define B_PCH_PMC_PSS_PG_STS_HDA BIT2 // HDA\r
868#define B_PCH_PMC_PSS_PG_STS_SATA BIT1 // SATA\r
869\r
870#define R_PCH_PMC_D3_STS_0 0xA0 // D3 Status 0\r
871#define B_PCH_PMC_D3_STS_0_LPSS1F7 BIT31 // LPSS 1 Function 7\r
872#define B_PCH_PMC_D3_STS_0_LPSS1F6 BIT30 // LPSS 1 Function 6\r
873#define B_PCH_PMC_D3_STS_0_LPSS1F5 BIT29 // LPSS 1 Function 5\r
874#define B_PCH_PMC_D3_STS_0_LPSS1F4 BIT28 // LPSS 1 Function 4\r
875#define B_PCH_PMC_D3_STS_0_LPSS1F3 BIT27 // LPSS 1 Function 3\r
876#define B_PCH_PMC_D3_STS_0_LPSS1F2 BIT26 // LPSS 1 Function 2\r
877#define B_PCH_PMC_D3_STS_0_LPSS1F1 BIT25 // LPSS 1 Function 1\r
878#define B_PCH_PMC_D3_STS_0_LPSS1F0 BIT24 // LPSS 1 Function 0\r
879#define B_PCH_PMC_D3_STS_0_PCIEF3 BIT23 // PCIe Function 3\r
880#define B_PCH_PMC_D3_STS_0_PCIEF2 BIT22 // PCIe Function 2\r
881#define B_PCH_PMC_D3_STS_0_PCIEF1 BIT21 // PCIe Function 1\r
882#define B_PCH_PMC_D3_STS_0_PCIEF0 BIT20 // PCIe Function 0\r
883#define B_PCH_PMC_D3_STS_0_USB BIT18 // USB\r
884#define B_PCH_PMC_D3_STS_0_SATA BIT17 // SATA\r
885#define B_PCH_PMC_D3_STS_0_USH BIT15 // USH\r
886#define B_PCH_PMC_D3_STS_0_OTG BIT14 // OTG\r
887#define B_PCH_PMC_D3_STS_0_LPE BIT13 // LPE\r
888#define B_PCH_PMC_D3_STS_0_HDA BIT12 // HDA\r
889#define B_PCH_PMC_D3_STS_0_MIPI BIT11 // MIPI-HSI\r
890#define B_PCH_PMC_D3_STS_0_SCCF2 BIT10 // SCC Function 2\r
891#define B_PCH_PMC_D3_STS_0_SCCF1 BIT9 // SCC Function 1\r
892#define B_PCH_PMC_D3_STS_0_SCCF0 BIT8 // SCC Function 0\r
893#define B_PCH_PMC_D3_STS_0_LPSS0F7 BIT7 // LPSS 0 Function 7\r
894#define B_PCH_PMC_D3_STS_0_LPSS0F6 BIT6 // LPSS 0 Function 6\r
895#define B_PCH_PMC_D3_STS_0_LPSS0F5 BIT5 // LPSS 0 Function 5\r
896#define B_PCH_PMC_D3_STS_0_LPSS0F4 BIT4 // LPSS 0 Function 4\r
897#define B_PCH_PMC_D3_STS_0_LPSS0F3 BIT3 // LPSS 0 Function 3\r
898#define B_PCH_PMC_D3_STS_0_LPSS0F2 BIT2 // LPSS 0 Function 2\r
899#define B_PCH_PMC_D3_STS_0_LPSS0F1 BIT1 // LPSS 0 Function 1\r
900#define B_PCH_PMC_D3_STS_0_LPSS0F0 BIT0 // LPSS 0 Function 0\r
901\r
902#define R_PCH_PMC_D3_STS_1 0xA4 // D3 Status 1\r
903#define B_PCH_PMC_D3_STS_1_DFX BIT3 // DFX\r
904#define B_PCH_PMC_D3_STS_1_OTG_SS BIT2 // OTG SS\r
905#define B_PCH_PMC_D3_STS_1_USH_SS BIT1 // USH SS\r
906#define B_PCH_PMC_D3_STS_1_SMB BIT0 // SMBus\r
907#define R_PCH_PMC_D3_STDBY_STS_0 0xA8 // D3 Standby Status 0\r
908#define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F7 BIT31 // LPSS 1 Function 7\r
909#define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F6 BIT30 // LPSS 1 Function 6\r
910#define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F5 BIT29 // LPSS 1 Function 5\r
911#define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F4 BIT28 // LPSS 1 Function 4\r
912#define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F3 BIT27 // LPSS 1 Function 3\r
913#define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F2 BIT26 // LPSS 1 Function 2\r
914#define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F1 BIT25 // LPSS 1 Function 1\r
915#define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F0 BIT24 // LPSS 1 Function 0\r
916#define B_PCH_PMC_D3_STDBY_STS_0_PCIEF3 BIT23 // PCIe Function 3\r
917#define B_PCH_PMC_D3_STDBY_STS_0_PCIEF2 BIT22 // PCIe Function 2\r
918#define B_PCH_PMC_D3_STDBY_STS_0_PCIEF1 BIT21 // PCIe Function 1\r
919#define B_PCH_PMC_D3_STDBY_STS_0_PCIEF0 BIT20 // PCIe Function 0\r
920#define B_PCH_PMC_D3_STDBY_STS_0_USB BIT18 // USB\r
921#define B_PCH_PMC_D3_STDBY_STS_0_SATA BIT17 // SATA\r
922#define B_PCH_PMC_D3_STDBY_STS_0_USH BIT15 // USH\r
923#define B_PCH_PMC_D3_STDBY_STS_0_OTG BIT14 // OTG\r
924#define B_PCH_PMC_D3_STDBY_STS_0_LPE BIT13 // LPE\r
925#define B_PCH_PMC_D3_STDBY_STS_0_HDA BIT12 // HDA\r
926#define B_PCH_PMC_D3_STDBY_STS_0_MIPI BIT11 // MIPI-HSI\r
927#define B_PCH_PMC_D3_STDBY_STS_0_SCCF2 BIT10 // SCC Function 2\r
928#define B_PCH_PMC_D3_STDBY_STS_0_SCCF1 BIT9 // SCC Function 1\r
929#define B_PCH_PMC_D3_STDBY_STS_0_SCCF0 BIT8 // SCC Function 0\r
930#define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F7 BIT7 // LPSS 0 Function 7\r
931#define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F6 BIT6 // LPSS 0 Function 6\r
932#define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F5 BIT5 // LPSS 0 Function 5\r
933#define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F4 BIT4 // LPSS 0 Function 4\r
934#define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F3 BIT3 // LPSS 0 Function 3\r
935#define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F2 BIT2 // LPSS 0 Function 2\r
936#define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F1 BIT1 // LPSS 0 Function 1\r
937#define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F0 BIT0 // LPSS 0 Function 0\r
938\r
939#define R_PCH_PMC_D3_STDBY_STS_1 0xAC // D3 Standby Status 1\r
940#define B_PCH_PMC_D3_STDBY_STS_1_DFX BIT3 // DFX\r
941#define B_PCH_PMC_D3_STDBY_STS_1_OTG_SS BIT2 // OTG SS\r
942#define B_PCH_PMC_D3_STDBY_STS_1_USH_SS BIT1 // USH SS\r
943#define B_PCH_PMC_D3_STDBY_STS_1_SMB BIT0 // SMBus\r
944\r
945#define R_PCH_PMC_MTPMC1 0xB0 // Message to PMC 1\r
946\r
947#define R_PCH_PMC_MTPMC2 0xB4 // Message to PMC 2\r
948\r
949#define R_PCH_PMC_MTPMC3 0xB8 // Message to PMC 3\r
950\r
951#define R_PCH_PMC_MTPMC4 0xBC // Message to PMC 4\r
952\r
953//\r
954// IO Memory Space Registers (IOBASE)\r
955//\r
956#define R_PCH_CFIO_PAD_CONF0 0x00 // CFIO PAD_CONF0\r
957#define R_PCH_CFIO_PAD_CONF1 0x04 // CFIO PAD_CONF1\r
958#define R_PCH_CFIO_PAD_VAL 0x08 // CFIO PAD_VAL\r
959#define R_PCH_CFIO_PAD_DFT 0x0C // CFIO PAD_CFT\r
960\r
961//\r
962// GPIO Register Offsets from GBASE\r
963//\r
964#define R_PCH_GPIO_SC_USE_SEL 0x00 // GPIO South Usage Select [31:0]\r
965#define R_PCH_GPIO_SC_IO_SEL 0x04 // GPIO South Input / Output Select [31:0]\r
966#define R_PCH_GPIO_SC_LVL 0x08 // GPIO South Level for Input or Output [31:0]\r
967\r
968#define R_PCH_GPIO_SC_TPE 0x0C // GPIO South Trigger Positive Edge Enable [31:0]\r
969#define R_PCH_GPIO_SC_TNE 0x10 // GPIO South Trigger Negative Edge Enable [31:0]\r
970#define R_PCH_GPIO_SC_TS 0x14 // GPIO South Trigger Status [31:0]\r
971\r
972#define R_PCH_GPIO_SC_USE_SEL2 0x20 // GPIO South Usage Select 2 [63:32]\r
973#define R_PCH_GPIO_SC_IO_SEL2 0x24 // GPIO South Input / Output Select 2 [63:32]\r
974#define R_PCH_GPIO_SC_LVL2 0x28 // GPIO South Level for Input or Output 2 [63:32]\r
975\r
976#define R_PCH_GPIO_SC_TPE2 0x2C // GPIO South Trigger Positive Edge Enable 2 [63:32]\r
977#define R_PCH_GPIO_SC_TNE2 0x30 // GPIO South Trigger Negative Edge Enable 2 [63:32]\r
978#define R_PCH_GPIO_SC_TS2 0x34 // GPIO South Trigger Status 2 [63:32]\r
979\r
980#define R_PCH_GPIO_SC_USE_SEL3 0x40 // GPIO South Usage Select 3 [95:64]\r
981#define R_PCH_GPIO_SC_IO_SEL3 0x44 // GPIO South Input / Output Select 3 [95:64]\r
982#define R_PCH_GPIO_SC_LVL3 0x48 // GPIO South Level for Input or Output 3 [95:64]\r
983\r
984#define R_PCH_GPIO_SC_TPE3 0x4C // GPIO South Trigger Positive Edge Enable 3 [95:64]\r
985#define R_PCH_GPIO_SC_TNE3 0x50 // GPIO South Trigger Negative Edge Enable 3 [95:64]\r
986#define R_PCH_GPIO_SC_TS3 0x54 // GPIO South Trigger Status 3 [95:64]\r
987\r
988#define R_PCH_GPIO_SC_USE_SEL4 0x60 // GPIO South Usage Select 4 [127:96]\r
989#define R_PCH_GPIO_SC_IO_SEL4 0x64 // GPIO South Input / Output Select 4 [127:96]\r
990#define R_PCH_GPIO_SC_LVL4 0x68 // GPIO South Level for Input or Output 4 [127:96]\r
991\r
992#define R_PCH_GPIO_SC_TPE4 0x6C // GPIO South Trigger Positive Edge Enable 4 [127:96]\r
993#define R_PCH_GPIO_SC_TNE4 0x70 // GPIO South Trigger Negative Edge Enable 4 [127:96]\r
994#define R_PCH_GPIO_SC_TS4 0x74 // GPIO South Trigger Status 4 [127:96]\r
995\r
996#define R_PCH_GPIO_SUS_USE_SEL 0x80 // GPIO Suspend Use Select [31:0]\r
997#define R_PCH_GPIO_SUS_IO_SEL 0x84 // GPIO Suspend Input / Output Select [31:0]\r
998#define R_PCH_GPIO_SUS_LVL 0x88 // GPIO Suspend Level for Input or Output [31:0]\r
999\r
1000#define R_PCH_GPIO_SUS_TPE 0x8C // GPIO Suspend Trigger Positive Edge Enable [31:0]\r
1001#define R_PCH_GPIO_SUS_TNE 0x90 // GPIO Suspend Trigger Negative Edge Enable [31:0]\r
1002#define R_PCH_GPIO_SUS_TS 0x94 // GPIO Suspend Trigger Status [31:0]\r
1003\r
1004#define R_PCH_GPIO_SUS_WAKE_EN 0x98 // GPIO Suspend Wake Enable [31:0]\r
1005\r
1006#define R_PCH_GPIO_SUS_USE_SEL2 0x100 // GPIO Suspend Use Select 2 [42:32]\r
1007#define R_PCH_GPIO_SUS_IO_SEL2 0x104 // GPIO Suspend Input / Output Select 2 [42:32]\r
1008#define R_PCH_GPIO_SUS_LVL2 0x108 // GPIO Suspend Level for Input or Output 2 [42:32]\r
1009\r
1010#define R_PCH_GPIO_SUS_TPE2 0x10C // GPIO Suspend Trigger Positive Edge Enable [42:32]\r
1011#define R_PCH_GPIO_SUS_TNE2 0x110 // GPIO Suspend Trigger Negative Edge Enable [42:32]\r
1012#define R_PCH_GPIO_SUS_TS2 0x114 // GPIO Suspend Trigger Status [42:32]\r
1013\r
1014#define R_PCH_GPIO_SUS_WAKE_EN2 0x118 // GPIO Suspend Wake Enable 2 [42:32]\r
1015\r
1016//\r
1017// Fixed IO Space\r
1018//\r
1019\r
1020//\r
1021// Processor Interface Registers\r
1022//\r
1023#define R_PCH_NMI_SC 0x61 // NMI Status and Control\r
1024#define B_PCH_NMI_SC_SERR_NMI_STS BIT7 // SERR# NMI Status\r
1025#define B_PCH_NMI_SC_IOCHK_NMI_STS BIT6 // IOCHK NMI Status\r
1026#define B_PCH_NMI_SC_TMR2_OUT_STS BIT5 // Timer Counter 2 Status\r
1027#define B_PCH_NMI_SC_REF_TOGGLE BIT4 // Refresh Cycle toggle Status\r
1028#define B_PCH_NMI_SC_IOCHK_NMI_EN BIT3 // IOCHK NMI Enable\r
1029#define B_PCH_NMI_SC_PCI_SERR_EN BIT2 // SERR# NMI Enable\r
1030#define B_PCH_NMI_SC_SPKR_DAT_EN BIT1 // Speaker Data Enable\r
1031#define B_PCH_NMI_SC_TIM_CNT2_EN BIT0 // Timer Counter 2 Enable\r
1032\r
1033#define R_PCH_NMI_EN 0x70 // NMI Enable and Real Time Clock Index, Co-function with R_PCH_RTC_INDEX\r
1034#define B_PCH_NMI_EN_NMI_EN BIT7 // NMI Enable, must preserve this bit first before writing to IO port 0x70\r
1035\r
1036//\r
1037// RTC Registers\r
1038//\r
1039#define R_PCH_RTC_INDEX 0x70 // NMI Enable and Real Time Clock Index, Co-function with R_PCH_NMI_EN\r
1040#define R_PCH_RTC_TARGET 0x71 // Real-Time Clock Target Register\r
1041#define R_PCH_RTC_EXT_INDEX 0x72 // Extended RAM Index Register\r
1042#define R_PCH_RTC_EXT_TARGET 0x73 // Extended RAM Target Register\r
1043#define R_PCH_RTC_INDEX2 0x74 // Real-Time Clock Index Register\r
1044#define R_PCH_RTC_TARGET2 0x75 // Real-Time Clock Target Register\r
1045#define R_PCH_RTC_EXT_INDEX2 0x76 // Extended RAM Index Register\r
1046#define R_PCH_RTC_EXT_TARGET2 0x77 // Extended RAM Target Register\r
1047\r
1048#define R_PCH_RTC_SECONDS 0x00 // Seconds, Range 0..59\r
1049#define R_PCH_RTC_SECONDSALARM 0x01 // Seconds Alarm, Range 0..59\r
1050#define R_PCH_RTC_MINUTES 0x02 // Minutes, Range 0..59\r
1051#define R_PCH_RTC_MINUTESALARM 0x03 // Minutes Alarm, Range 0..59\r
1052#define R_PCH_RTC_HOURS 0x04 // Hours, Range 1..12 or 0..23 Bit 7 is AM/PM\r
1053#define R_PCH_RTC_HOURSALARM 0x05 // Hours Alarm, Range 1..12 or 0..23 Bit 7 is AM/PM\r
1054#define R_PCH_RTC_DAYOFWEEK 0x06 // Day of Week, Range 1..7\r
1055#define R_PCH_RTC_DAYOFMONTH 0x07 // Day of Month, Range 1..31\r
1056#define R_PCH_RTC_MONTH 0x08 // Month, Range 1..12\r
1057#define R_PCH_RTC_YEAR 0x09 // Year, Range 0..99\r
1058\r
1059#define R_PCH_RTC_REGISTERA 0x0A // RTC Register A\r
1060#define B_PCH_RTC_REGISTERA_UIP BIT7 // Update In Progress\r
1061#define B_PCH_RTC_REGISTERA_DV (BIT6 | BIT5 | BIT4) // Division Chain Select\r
1062#define V_PCH_RTC_REGISTERA_DV_NORM_OP 0x20 // Normal Operation\r
1063#define V_PCH_RTC_REGISTERA_DV_BYP_5 0x30 // Bypass 5 Stages (Test mode only)\r
1064#define V_PCH_RTC_REGISTERA_DV_BYP_10 0x40 // Bypass 10 Stages (Test mode only)\r
1065#define V_PCH_RTC_REGISTERA_DV_BYP_15 0x50 // Bypass 15 Stages (Test mode only)\r
1066#define V_PCH_RTC_REGISTERA_DV_DIV_RST1 0x60 // Divider Reset\r
1067#define V_PCH_RTC_REGISTERA_DV_DIV_RST2 0x70 // Divider Reset\r
1068#define B_PCH_RTC_REGISTERA_RS (BIT3 | BIT2 | BIT1 | BIT0) // Rate Select\r
1069#define V_PCH_RTC_REGISTERA_RS_INT_NV_TGL 0x00 // Interrupt Never Toggles\r
1070#define V_PCH_RTC_REGISTERA_RS_3P906MS1 0x01 // 3.90625 ms\r
1071#define V_PCH_RTC_REGISTERA_RS_7P812MS1 0x02 // 7.8125 ms\r
1072#define V_PCH_RTC_REGISTERA_RS_122P0US 0x03 // 122.070 us\r
1073#define V_PCH_RTC_REGISTERA_RS_244P1US 0x04 // 244.141 us\r
1074#define V_PCH_RTC_REGISTERA_RS_488P2US 0x05 // 488.281 us\r
1075#define V_PCH_RTC_REGISTERA_RS_976P5US 0x06 // 976.5625 us\r
1076#define V_PCH_RTC_REGISTERA_RS_1P953MS 0x07 // 1.953125 ms\r
1077#define V_PCH_RTC_REGISTERA_RS_3P906MS 0x08 // 3.90625 ms\r
1078#define V_PCH_RTC_REGISTERA_RS_7P812MS 0x09 // 7.8125 ms\r
1079#define V_PCH_RTC_REGISTERA_RS_15P62MS 0x0A // 15.625 ms\r
1080#define V_PCH_RTC_REGISTERA_RS_31P25MS 0x0B // 31.25 ms\r
1081#define V_PCH_RTC_REGISTERA_RS_62P5MS 0x0C // 62.5 ms\r
1082#define V_PCH_RTC_REGISTERA_RS_125MS 0x0D // 125 ms\r
1083#define V_PCH_RTC_REGISTERA_RS_250MS 0x0E // 250 ms\r
1084#define V_PCH_RTC_REGISTERA_RS_500MS 0x0F // 500 ms\r
1085\r
1086#define R_PCH_RTC_REGISTERB 0x0B // RTC Register B\r
1087#define B_PCH_RTC_REGISTERB_SET BIT7 // Update Cycle Inhibit 1: Stop auto update, begin set value; 0: Update cycle occurs\r
1088#define B_PCH_RTC_REGISTERB_PIE BIT6 // Periodic Interrupt Enable\r
1089#define B_PCH_RTC_REGISTERB_AIE BIT5 // Alarm Interrupt Enable\r
1090#define B_PCH_RTC_REGISTERB_UIE BIT4 // Update-ended Interrupt Enable\r
1091#define B_PCH_RTC_REGISTERB_SQWE BIT3 // Square Wave Enable (Not implemented)\r
1092#define B_PCH_RTC_REGISTERB_DM BIT2 // Data Mode 1: Binary; 0:BCD\r
1093#define B_PCH_RTC_REGISTERB_HF BIT1 // Hour Format 1: 24 mode; 0: 12 mode.\r
1094#define B_PCH_RTC_REGISTERB_DSE BIT0 // Daylight Savings Enable (Not Implemented)\r
1095\r
1096#define R_PCH_RTC_REGISTERC 0x0C // RTC Register C\r
1097#define B_PCH_RTC_REGISTERC_IRQF BIT7 // Interrupt Request Flag\r
1098#define B_PCH_RTC_REGISTERC_PF BIT6 // Periodic Interrupt Flag\r
1099#define B_PCH_RTC_REGISTERC_AF BIT5 // Alarm Flag\r
1100#define B_PCH_RTC_REGISTERC_UF BIT4 // Update-ended Flag\r
1101#define B_PCH_RTC_REGISTERC_RESERVED (BIT3 | BIT2 | BIT1 | BIT0)\r
1102\r
1103#define R_PCH_RTC_REGISTERD 0x0D // RTC Register D\r
1104#define B_PCH_RTC_REGISTERD_VRT BIT7 // Valid RAM and Time Bit\r
1105#define B_PCH_RTC_REGISTERD_RESERVED BIT6\r
1106#define B_PCH_RTC_REGISTERD_DA 0x3F // Date Alarm\r
1107\r
1108#define B_PCH_RTC_CENTURY 0x32 // Century Data\r
1109\r
1110//\r
1111// APM Registers\r
1112//\r
1113#define R_PCH_APM_CNT 0xB2 // Advanced Power Management Control Port\r
1114#define R_PCH_APM_STS 0xB3 // Advanced Power Management Status Port\r
1115\r
1116//\r
1117// INIT Register\r
1118//\r
1119#define R_PCH_PORT92 0x92\r
1120#define B_PCH_PORT92_ALT_A20_GATE BIT1 // Alternate A20 Gate\r
1121#define B_PCH_PORT92_INIT_NOW BIT0 // Init Now\r
1122\r
1123//\r
1124// PCU UART\r
1125//\r
1126#define R_PCH_COM1_BASE 0x3F8 // COM1 IO BASE\r
1127\r
1128//\r
1129// Reset Control Register\r
1130//\r
1131#define R_PCH_RST_CNT 0xCF9 // Reset Control\r
1132#define B_PCH_RST_CNT_FULL_RST BIT3\r
1133#define B_PCH_RST_CNT_RST_CPU BIT2\r
1134#define B_PCH_RST_CNT_SYS_RST BIT1\r
1135#define V_PCH_RST_CNT_FULLRESET 0x0E\r
1136#define V_PCH_RST_CNT_HARDRESET 0x06\r
1137#define V_PCH_RST_CNT_SOFTRESET 0x04 // Not supported by VLV\r
1138#define V_PCH_RST_CNT_HARDSTARTSTATE 0x02\r
1139#define V_PCH_RST_CNT_SOFTSTARTSTATE 0x00\r
1140\r
1141//\r
1142// Fixed Memory Region\r
1143//\r
1144\r
1145//\r
1146// IO APIC Registers\r
1147//\r
1148#define R_PCH_IO_APIC_INDEX 0xFEC00000 // IOAPIC Index Register, 8bit\r
1149#define R_PCH_IO_APIC_WINDOW 0xFEC00010 // IOAPIC Window Register, 32bit\r
1150#define R_PCH_IO_APIC_EOI 0xFEC00040 // IOAPIC EOI Register, 8bit\r
1151\r
1152#define R_PCH_IO_APIC_ID 0x00 // Identification\r
1153#define B_PCH_IO_APIC_ID_AID (BIT27 | BIT26 | BIT25 | BIT24) // APIC Identification\r
1154\r
1155#define R_PCH_IO_APIC_VS 0x01 // Version\r
1156#define B_PCH_IO_APIC_VS_MRE 0xFF0000 // Maximum Redirection Entries\r
1157#define B_PCH_IO_APIC_VS_PRQ BIT15 // Pin Assertion Register Supported\r
1158#define B_PCH_IO_APIC_VS_VS 0xFF // Version\r
1159\r
1160//\r
1161// HPET Registers\r
1162//\r
1163#define R_PCH_PCH_HPET 0xFED00000 // HPET Base Address\r
1164\r
1165#define R_PCH_PCH_HPET_GCID 0x00 // HPET General Capabilities and ID, 64bit\r
1166#define B_PCH_PCH_HPET_GCID_CTP 0xFFFFFFFF00000000 // Counter Tick Period\r
1167#define B_PCH_PCH_HPET_GCID_VID 0xFFFF0000 // Vendor ID\r
1168#define B_PCH_PCH_HPET_GCID_LRC BIT15 // Legacy Rout Capable\r
1169#define B_PCH_PCH_HPET_GCID_CS BIT13 // Counter Size\r
1170#define B_PCH_PCH_HPET_GCID_NT 0x1F00 // Number of Timers\r
1171#define B_PCH_PCH_HPET_GCID_RID 0xFF // Revision ID\r
1172#define N_PCH_HPET_ADDR_ASEL 12\r
1173\r
1174#define R_PCH_PCH_HPET_GCFG 0x10 // HPET General Configuration\r
1175#define B_PCH_PCH_HPET_GCFG_LRE BIT1 // Legacy Rout Enable\r
1176#define B_PCH_PCH_HPET_GCFG_EN BIT0 // Overall Enable\r
1177\r
1178#define R_PCH_PCH_HPET_GIS 0x20 // HPET General Interrupt Status\r
1179#define B_PCH_PCH_HPET_GIS_T2 BIT2 // Timer 2 Status\r
1180#define B_PCH_PCH_HPET_GIS_T1 BIT1 // Timer 1 Status\r
1181#define B_PCH_PCH_HPET_GIS_T0 BIT0 // Timer 0 Status\r
1182\r
1183#define R_PCH_PCH_HPET_MCV 0xF0 // HPET Main Counter Value, 64bit\r
1184\r
1185#define R_PCH_PCH_HPET_T0C 0x100 // HPET Timer 0 Config and Capabilities\r
1186#define R_PCH_PCH_HPET_T0CV_L 0x108 // HPET Timer 0 Lower Comparator Value\r
1187#define R_PCH_PCH_HPET_T0CV_H 0x10C // HPET Timer 0 Upper Comparator Value\r
1188\r
1189#define R_PCH_PCH_HPET_T1C 0x120 // HPET Timer 1 Config and Capabilities\r
1190#define R_PCH_PCH_HPET_T1CV 0x128 // HPET Timer 1 Comparator Value\r
1191\r
1192#define R_PCH_PCH_HPET_T2C 0x140 // HPET Timer 2 Config and Capabilities\r
1193#define R_PCH_PCH_HPET_T2CV 0x148 // HPET Timer 2 Comparator Value\r
1194\r
1195#define B_PCH_PCH_HPET_TXC_IRC 0xFFFFFFFF00000000 // Interrupt Rout Capability\r
1196#define B_PCH_PCH_HPET_TXC_FID BIT15 // FSB Interrupt Delivery\r
1197#define B_PCH_PCH_HPET_TXC_FE BIT14 // FSB Enable\r
1198#define B_PCH_PCH_HPET_TXC_IR 0x3E00 // Interrupt Rout\r
1199#define B_PCH_PCH_HPET_TXC_T32M BIT8 // Timer 32-bit Mode\r
1200#define B_PCH_PCH_HPET_TXC_TVS BIT6 // Timer Value Set\r
1201#define B_PCH_PCH_HPET_TXC_TS BIT5 // Timer Size\r
1202#define B_PCH_PCH_HPET_TXC_PIC BIT4 // Periodic Interrupt Capable\r
1203#define B_PCH_PCH_HPET_TXC_TYP BIT3 // Timer Type\r
1204#define B_PCH_PCH_HPET_TXC_IE BIT2 // Interrupt Enable\r
1205#define B_PCH_PCH_HPET_TXC_IT BIT1 // Timer Interrupt Type\r
1206\r
1207#endif\r