projects / mirror_edk2.git / blame
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|---|---|---|
| 3cbfba02 DW |
1 | /**\r |
| 2 | \r | |
| 3 | Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved\r | |
| 4 | \r | |
| 5 | This program and the accompanying materials are licensed and made available under\r | |
| 6 | the terms and conditions of the BSD License that accompanies this distribution.\r | |
| 7 | The full text of the license may be found at\r | |
| 8 | http://opensource.org/licenses/bsd-license.php.\r | |
| 9 | \r | |
| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 12 | \r | |
| 13 | \r | |
| 14 | \r | |
| 15 | @file\r | |
| 16 | PchRegsRcrb.h\r | |
| 17 | \r | |
| 18 | @brief\r | |
| 19 | Register names for VLV Chipset Configuration Registers\r | |
| 20 | \r | |
| 21 | Conventions:\r | |
| 22 | \r | |
| 23 | - Prefixes:\r | |
| 24 | Definitions beginning with "R_" are registers\r | |
| 25 | Definitions beginning with "B_" are bits within registers\r | |
| 26 | Definitions beginning with "V_" are meaningful values of bits within the registers\r | |
| 27 | Definitions beginning with "S_" are register sizes\r | |
| 28 | Definitions beginning with "N_" are the bit position\r | |
| 29 | - In general, PCH registers are denoted by "_PCH_" in register names\r | |
| 30 | - Registers / bits that are different between PCH generations are denoted by\r | |
| 31 | "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"\r | |
| 32 | - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"\r | |
| 33 | at the end of the register/bit names\r | |
| 34 | - Registers / bits of new devices introduced in a PCH generation will be just named\r | |
| 35 | as "_PCH_" without <generation_name> inserted.\r | |
| 36 | \r | |
| 37 | **/\r | |
| 38 | #ifndef _PCH_REGS_RCRB_H_\r | |
| 39 | #define _PCH_REGS_RCRB_H_\r | |
| 40 | \r | |
| 41 | ///\r | |
| 42 | /// Chipset Configuration Registers (Memory space)\r | |
| 43 | /// RCBA\r | |
| 44 | ///\r | |
| 45 | #define R_PCH_RCRB_GCS 0x00 // General Control and Status\r | |
| 46 | #define B_PCH_RCRB_GCS_BBSIZE (BIT30 | BIT29) // Boot Block Size\r | |
| 47 | #define B_PCH_RCRB_GCS_BBS (BIT11 | BIT10) // Boot BIOS Straps\r | |
| 48 | #define V_PCH_RCRB_GCS_BBS_SPI (3 << 10) // Boot BIOS strapped to SPI\r | |
| 49 | #define V_PCH_RCRB_GCS_BBS_LPC (0 << 10) // Boot BIOS strapped to LPC\r | |
| 50 | #define B_PCH_RCRB_GCS_TS BIT1 // Top Swap\r | |
| 51 | #define B_PCH_RCRB_GCS_BILD BIT0 // BIOS Interface Lock-Down\r | |
| 52 | \r | |
| 53 | \r | |
| 54 | #endif\r |