Vlv2DeviceRefCodePkg: Replace BSD License with BSD+Patent License

[mirror_edk2.git] / Vlv2DeviceRefCodePkg / ValleyView2Soc / SouthCluster / Include / PchRegs / PchRegsRcrb.h

/**\r
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Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved\r
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  SPDX-License-Identifier: BSD-2-Clause-Patent\r
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  @file\r
  PchRegsRcrb.h\r
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  @brief\r
  Register names for VLV Chipset Configuration Registers\r
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  Conventions:\r
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  - Prefixes:\r
    Definitions beginning with "R_" are registers\r
    Definitions beginning with "B_" are bits within registers\r
    Definitions beginning with "V_" are meaningful values of bits within the registers\r
    Definitions beginning with "S_" are register sizes\r
    Definitions beginning with "N_" are the bit position\r
  - In general, PCH registers are denoted by "_PCH_" in register names\r
  - Registers / bits that are different between PCH generations are denoted by\r
    "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"\r
  - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"\r
    at the end of the register/bit names\r
  - Registers / bits of new devices introduced in a PCH generation will be just named\r
    as "_PCH_" without <generation_name> inserted.\r
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**/\r
#ifndef _PCH_REGS_RCRB_H_\r
#define _PCH_REGS_RCRB_H_\r
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///\r
/// Chipset Configuration Registers (Memory space)\r
/// RCBA\r
///\r
#define R_PCH_RCRB_GCS                    0x00  // General Control and Status\r
#define B_PCH_RCRB_GCS_BBSIZE             (BIT30 | BIT29) // Boot Block Size\r
#define B_PCH_RCRB_GCS_BBS                (BIT11 | BIT10) // Boot BIOS Straps\r
#define V_PCH_RCRB_GCS_BBS_SPI            (3 << 10) // Boot BIOS strapped to SPI\r
#define V_PCH_RCRB_GCS_BBS_LPC            (0 << 10) // Boot BIOS strapped to LPC\r
#define B_PCH_RCRB_GCS_TS                 BIT1 // Top Swap\r
#define B_PCH_RCRB_GCS_BILD               BIT0 // BIOS Interface Lock-Down\r
\r
\r
#endif\r