projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3cbfba02 DW |
1 | /**\r |
| 2 | \r | |
| 3 | Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved\r | |
| 4 | \r | |
| 7ede8060 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 3cbfba02 DW |
6 | \r |
| 7 | \r | |
| 8 | \r | |
| 9 | @file\r | |
| 10 | PchRegsSmbus.h\r | |
| 11 | \r | |
| 12 | @brief\r | |
| 13 | Register names for VLV Smbus Device.\r | |
| 14 | \r | |
| 15 | Conventions:\r | |
| 16 | \r | |
| 17 | - Prefixes:\r | |
| 18 | Definitions beginning with "R_" are registers\r | |
| 19 | Definitions beginning with "B_" are bits within registers\r | |
| 20 | Definitions beginning with "V_" are meaningful values of bits within the registers\r | |
| 21 | Definitions beginning with "S_" are register sizes\r | |
| 22 | Definitions beginning with "N_" are the bit position\r | |
| 23 | - In general, PCH registers are denoted by "_PCH_" in register names\r | |
| 24 | - Registers / bits that are different between PCH generations are denoted by\r | |
| 25 | "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"\r | |
| 26 | - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"\r | |
| 27 | at the end of the register/bit names\r | |
| 28 | - Registers / bits of new devices introduced in a PCH generation will be just named\r | |
| 29 | as "_PCH_" without <generation_name> inserted.\r | |
| 30 | \r | |
| 31 | **/\r | |
| 32 | #ifndef _PCH_REGS_SMBUS_H_\r | |
| 33 | #define _PCH_REGS_SMBUS_H_\r | |
| 34 | \r | |
| 35 | ///\r | |
| 36 | /// SMBus Controller Registers (D31:F3)\r | |
| 37 | ///\r | |
| 38 | #define PCI_DEVICE_NUMBER_PCH_SMBUS 31\r | |
| 39 | #define PCI_FUNCTION_NUMBER_PCH_SMBUS 3\r | |
| 40 | \r | |
| 41 | #define R_PCH_SMBUS_VENDOR_ID 0x00 // Vendor ID\r | |
| 42 | #define V_PCH_SMBUS_VENDOR_ID V_PCH_INTEL_VENDOR_ID // Intel Vendor ID\r | |
| 43 | \r | |
| 44 | #define R_PCH_SMBUS_DEVICE_ID 0x02 // Device ID\r | |
| 45 | #define V_PCH_SMBUS_DEVICE_ID 0x0F12\r | |
| 46 | \r | |
| 47 | #define R_PCH_SMBUS_PCICMD 0x04 // CMD register enables/disables, Memory/IO space access and interrupt\r | |
| 48 | #define B_PCH_SMBUS_PCICMD_INTR_DIS BIT10 // Interrupt Disable\r | |
| 49 | #define B_PCH_SMBUS_PCICMD_FBE BIT9 // FBE - reserved as '0'\r | |
| 50 | #define B_PCH_SMBUS_PCICMD_SERR_EN BIT8 // SERR Enable - reserved as '0'\r | |
| 51 | #define B_PCH_SMBUS_PCICMD_WCC BIT7 // Wait Cycle Control - reserved as '0'\r | |
| 52 | #define B_PCH_SMBUS_PCICMD_PER BIT6 // Parity Error - reserved as '0'\r | |
| 53 | #define B_PCH_SMBUS_PCICMD_VPS BIT5 // VGA Palette Snoop - reserved as '0'\r | |
| 54 | #define B_PCH_SMBUS_PCICMD_PMWE BIT4 // Postable Memory Write Enable - reserved as '0'\r | |
| 55 | #define B_PCH_SMBUS_PCICMD_SCE BIT3 // Special Cycle Enable - reserved as '0'\r | |
| 56 | #define B_PCH_SMBUS_PCICMD_BME BIT2 // Bus Master Enable - reserved as '0'\r | |
| 57 | #define B_PCH_SMBUS_PCICMD_MSE BIT1 // Memory Space Enable\r | |
| 58 | #define B_PCH_SMBUS_PCICMD_IOSE BIT0 // I/O Space Enable\r | |
| 59 | \r | |
| 60 | #define R_PCH_SMBUS_BASE 0x20 // The I/O memory bar\r | |
| 61 | #define B_PCH_SMBUS_BASE_BAR 0x0000FFE0 // Base Address\r | |
| 62 | #define B_PCH_SMBUS_BASE_IOSI BIT0 // IO Space Indicator\r | |
| 63 | \r | |
| 64 | #define R_PCH_SMBUS_SVID 0x2C // Subsystem Vendor ID\r | |
| 65 | #define B_PCH_SMBUS_SVID 0xFFFF // Subsystem Vendor ID\r | |
| 66 | \r | |
| 67 | //\r | |
| 68 | // SMBus I/O Registers\r | |
| 69 | //\r | |
| 70 | #define R_PCH_SMBUS_HSTS 0x00 // Host Status Register R/W\r | |
| 71 | #define B_PCH_SMBUS_HSTS_ALL 0xFF\r | |
| 72 | #define B_PCH_SMBUS_BYTE_DONE_STS BIT7 // Byte Done Status\r | |
| 73 | #define B_PCH_SMBUS_IUS BIT6 // In Use Status\r | |
| 74 | #define B_PCH_SMBUS_SMBALERT_STS BIT5 // SMBUS Alert\r | |
| 75 | #define B_PCH_SMBUS_FAIL BIT4 // Failed\r | |
| 76 | #define B_PCH_SMBUS_BERR BIT3 // Bus Error\r | |
| 77 | #define B_PCH_SMBUS_DERR BIT2 // Device Error\r | |
| 78 | #define B_PCH_SMBUS_ERRORS (B_PCH_SMBUS_FAIL | B_PCH_SMBUS_BERR | B_PCH_SMBUS_DERR)\r | |
| 79 | #define B_PCH_SMBUS_INTR BIT1 // Interrupt\r | |
| 80 | #define B_PCH_SMBUS_HBSY BIT0 // Host Busy\r | |
| 81 | \r | |
| 82 | #define R_PCH_SMBUS_HCTL 0x02 // Host Control Register R/W\r | |
| 83 | #define B_PCH_SMBUS_PEC_EN BIT7 // Packet Error Checking Enable\r | |
| 84 | #define B_PCH_SMBUS_START BIT6 // Start\r | |
| 85 | #define B_PCH_SMBUS_LAST_BYTE BIT5 // Last Byte\r | |
| 86 | #define B_PCH_SMBUS_SMB_CMD 0x1C // SMB Command\r | |
| 87 | #define V_PCH_SMBUS_SMB_CMD_BLOCK_PROCESS 0x1C // Block Process\r | |
| 88 | #define V_PCH_SMBUS_SMB_CMD_IIC_READ 0x18 // I2C Read\r | |
| 89 | #define V_PCH_SMBUS_SMB_CMD_BLOCK 0x14 // Block\r | |
| 90 | #define V_PCH_SMBUS_SMB_CMD_PROCESS_CALL 0x10 // Process Call\r | |
| 91 | #define V_PCH_SMBUS_SMB_CMD_WORD_DATA 0x0C // Word Data\r | |
| 92 | #define V_PCH_SMBUS_SMB_CMD_BYTE_DATA 0x08 // Byte Data\r | |
| 93 | #define V_PCH_SMBUS_SMB_CMD_BYTE 0x04 // Byte\r | |
| 94 | #define V_PCH_SMBUS_SMB_CMD_QUICK 0x00 // Quick\r | |
| 95 | #define B_PCH_SMBUS_KILL BIT1 // Kill\r | |
| 96 | #define B_PCH_SMBUS_INTREN BIT0 // Interrupt Enable\r | |
| 97 | \r | |
| 98 | #define R_PCH_SMBUS_HCMD 0x03 // Host Command Register R/W\r | |
| 99 | #define B_PCH_SMBUS_HCMD 0xFF // Command to be transmitted\r | |
| 100 | \r | |
| 101 | #define R_PCH_SMBUS_TSA 0x04 // Transmit Slave Address Register R/W\r | |
| 102 | #define B_PCH_SMBUS_ADDRESS 0xFE // 7-bit address of the targeted slave\r | |
| 103 | #define B_PCH_SMBUS_RW_SEL BIT0 // Direction of the host transfer, 1 = read, 0 = write\r | |
| 104 | #define B_PCH_SMBUS_RW_SEL_READ 0x01 // Read\r | |
| 105 | #define B_PCH_SMBUS_RW_SEL_WRITE 0x00 // Write\r | |
| 106 | //\r | |
| 107 | #define R_PCH_SMBUS_HD0 0x05 // Data 0 Register R/W\r | |
| 108 | #define R_PCH_SMBUS_HD1 0x06 // Data 1 Register R/W\r | |
| 109 | #define R_PCH_SMBUS_HBD 0x07 // Host Block Data Register R/W\r | |
| 110 | #define R_PCH_SMBUS_PEC 0x08 // Packet Error Check Data Register R/W\r | |
| 111 | \r | |
| 112 | #define R_PCH_SMBUS_RSA 0x09 // Receive Slave Address Register R/W\r | |
| 113 | #define B_PCH_SMBUS_SLAVE_ADDR 0x7F // TCO slave address (Not used, reserved)\r | |
| 114 | \r | |
| 115 | #define R_PCH_SMBUS_SD 0x0A // Receive Slave Data Register R/W\r | |
| 116 | \r | |
| 117 | #define R_PCH_SMBUS_AUXS 0x0C // Auxiliary Status Register R/WC\r | |
| 118 | #define B_PCH_SMBUS_CRCE BIT0 // CRC Error\r | |
| 119 | //\r | |
| 120 | #define R_PCH_SMBUS_AUXC 0x0D // Auxiliary Control Register R/W\r | |
| 121 | #define B_PCH_SMBUS_E32B BIT1 // Enable 32-byte Buffer\r | |
| 122 | #define B_PCH_SMBUS_AAC BIT0 // Automatically Append CRC\r | |
| 123 | \r | |
| 124 | #define R_PCH_SMBUS_SMLC 0x0E // SMLINK Pin Control Register R/W\r | |
| 125 | #define B_PCH_SMBUS_SMLINK_CLK_CTL BIT2 // Not supported\r | |
| 126 | #define B_PCH_SMBUS_SMLINK1_CUR_STS BIT1 // Not supported\r | |
| 127 | #define B_PCH_SMBUS_SMLINK0_CUR_STS BIT0 // Not supported\r | |
| 128 | \r | |
| 129 | \r | |
| 130 | #define R_PCH_SMBUS_SMBC 0x0F // SMBus Pin Control Register R/W\r | |
| 131 | #define B_PCH_SMBUS_SMBCLK_CTL BIT2 // SMBCLK Control\r | |
| 132 | #define B_PCH_SMBUS_SMBDATA_CUR_STS BIT1 // SMBDATA Current Status\r | |
| 133 | #define B_PCH_SMBUS_SMBCLK_CUR_STS BIT0 // SMBCLK Current Status\r | |
| 134 | \r | |
| 135 | #define R_PCH_SMBUS_SSTS 0x10 // Slave Status Register R/WC\r | |
| 136 | #define B_PCH_SMBUS_HOST_NOTIFY_STS BIT0 // Host Notify Status\r | |
| 137 | \r | |
| 138 | #define R_PCH_SMBUS_SCMD 0x11 // Slave Command Register R/W\r | |
| 139 | #define B_PCH_SMBUS_SMBALERT_DIS BIT2 // Not supported\r | |
| 140 | #define B_PCH_SMBUS_HOST_NOTIFY_WKEN BIT1 // Host Notify Wake Enable\r | |
| 141 | #define B_PCH_SMBUS_HOST_NOTIFY_INTREN BIT0 // Host Notify Interrupt Enable\r | |
| 142 | \r | |
| 143 | #define R_PCH_SMBUS_NDA 0x14 // Notify Device Address Register RO\r | |
| 144 | #define B_PCH_SMBUS_DEVICE_ADDRESS 0xFE // Device Address\r | |
| 145 | \r | |
| 146 | #define R_PCH_SMBUS_NDLB 0x16 // Notify Data Low Byte Register RO\r | |
| 147 | #define R_PCH_SMBUS_NDHB 0x17 // Notify Data High Byte Register RO\r | |
| 148 | \r | |
| 149 | #endif\r |