[mirror_edk2.git] / Vlv2DeviceRefCodePkg / ValleyView2Soc / SouthCluster / Include / PchRegs / PchRegsSpi.h

/**\r
\r
Copyright (c) 2011  - 2014, Intel Corporation. All rights reserved\r
\r
  This program and the accompanying materials are licensed and made available under\r
  the terms and conditions of the BSD License that accompanies this distribution.\r
  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php.\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
\r
\r
  @file\r
  PchRegsSpi.h\r
\r
  @brief\r
  Register names for PCH SPI device.\r
\r
  Conventions:\r
\r
  - Prefixes:\r
    Definitions beginning with "R_" are registers\r
    Definitions beginning with "B_" are bits within registers\r
    Definitions beginning with "V_" are meaningful values of bits within the registers\r
    Definitions beginning with "S_" are register sizes\r
    Definitions beginning with "N_" are the bit position\r
  - In general, PCH registers are denoted by "_PCH_" in register names\r
  - Registers / bits that are different between PCH generations are denoted by\r
    "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"\r
  - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"\r
    at the end of the register/bit names\r
  - Registers / bits of new devices introduced in a PCH generation will be just named\r
    as "_PCH_" without <generation_name> inserted.\r
\r
**/\r
#ifndef _PCH_REGS_SPI_H_\r
#define _PCH_REGS_SPI_H_\r
\r
///\r
/// SPI Host Interface Registers\r
///\r
\r
#define R_PCH_SPI_HSFS                       0x04  // Hardware Sequencing Flash Status Register (16bits)\r
#define B_PCH_SPI_HSFS_FLOCKDN               BIT15 // Flash Configuration Lock-Down\r
#define B_PCH_SPI_HSFS_FDV                   BIT14 // Flash Descriptor Valid\r
#define B_PCH_SPI_HSFS_FDOPSS                BIT13 // Flash Descriptor Override Pin-Strap Status\r
#define B_PCH_SPI_HSFS_SCIP                  BIT5  // SPI Cycle in Progress\r
#define B_PCH_SPI_HSFS_BERASE_MASK           (BIT4 | BIT3) // Block / Sector Erase Size\r
#define V_PCH_SPI_HSFS_BERASE_256B           0x00  // Block/Sector = 256 Bytes\r
#define V_PCH_SPI_HSFS_BERASE_4K             0x01  // Block/Sector = 4K Bytes\r
#define V_PCH_SPI_HSFS_BERASE_8K             0x10  // Block/Sector = 8K Bytes\r
#define V_PCH_SPI_HSFS_BERASE_64K            0x11  // Block/Sector = 64K Bytes\r
#define B_PCH_SPI_HSFS_AEL                   BIT2  // Access Error Log\r
#define B_PCH_SPI_HSFS_FCERR                 BIT1  // Flash Cycle Error\r
#define B_PCH_SPI_HSFS_FDONE                 BIT0  // Flash Cycle Done\r
\r
#define R_PCH_SPI_PR0                        0x74  // Protected Region 0 Register\r
#define B_PCH_SPI_PR0_WPE                    BIT31 // Write Protection Enable\r
#define B_PCH_SPI_PR0_PRL_MASK               0x1FFF0000 // Protected Range Limit Mask, [28:16] here represents upper limit of address [24:12]\r
#define B_PCH_SPI_PR0_RPE                    BIT15 // Read Protection Enable\r
#define B_PCH_SPI_PR0_PRB_MASK               0x00001FFF // Protected Range Base Mask, [12:0] here represents base limit of address [24:12]\r
\r
#define R_PCH_SPI_PREOP                      0x94  // Prefix Opcode Configuration Register (16 bits)\r
#define B_PCH_SPI_PREOP1_MASK                0xFF00 // Prefix Opcode 1 Mask\r
#define B_PCH_SPI_PREOP0_MASK                0x00FF // Prefix Opcode 0 Mask\r
\r
#define R_PCH_SPI_OPTYPE                     0x96  // Opcode Type Configuration\r
#define B_PCH_SPI_OPTYPE7_MASK               (BIT15 | BIT14) // Opcode Type 7 Mask\r
#define B_PCH_SPI_OPTYPE6_MASK               (BIT13 | BIT12) // Opcode Type 6 Mask\r
#define B_PCH_SPI_OPTYPE5_MASK               (BIT11 | BIT10) // Opcode Type 5 Mask\r
#define B_PCH_SPI_OPTYPE4_MASK               (BIT9 | BIT8) // Opcode Type 4 Mask\r
#define B_PCH_SPI_OPTYPE3_MASK               (BIT7 | BIT6) // Opcode Type 3 Mask\r
#define B_PCH_SPI_OPTYPE2_MASK               (BIT5 | BIT4) // Opcode Type 2 Mask\r
#define B_PCH_SPI_OPTYPE1_MASK               (BIT3 | BIT2) // Opcode Type 1 Mask\r
#define B_PCH_SPI_OPTYPE0_MASK               (BIT1 | BIT0) // Opcode Type 0 Mask\r
#define V_PCH_SPI_OPTYPE_RDNOADDR            0x00  // Read cycle type without address\r
#define V_PCH_SPI_OPTYPE_WRNOADDR            0x01  // Write cycle type without address\r
#define V_PCH_SPI_OPTYPE_RDADDR              0x02  // Address required; Read cycle type\r
#define V_PCH_SPI_OPTYPE_WRADDR              0x03  // Address required; Write cycle type\r
\r
#define R_PCH_SPI_OPMENU0                    0x98  // Opcode Menu Configuration 0 (32bits)\r
#define R_PCH_SPI_OPMENU1                    0x9C  // Opcode Menu Configuration 1 (32bits)\r
\r
#define R_PCH_SPI_IND_LOCK                   0xA4  // Indvidual Lock\r
#define B_PCH_SPI_IND_LOCK_PR0               BIT2  // PR0 LockDown\r
\r
\r
#define R_PCH_SPI_FDOC                       0xB0  // Flash Descriptor Observability Control Register (32 bits)\r
#define B_PCH_SPI_FDOC_FDSS_MASK             (BIT14 | BIT13 | BIT12) // Flash Descriptor Section Select\r
#define V_PCH_SPI_FDOC_FDSS_FSDM             0x0000 // Flash Signature and Descriptor Map\r
#define V_PCH_SPI_FDOC_FDSS_COMP             0x1000 // Component\r
#define V_PCH_SPI_FDOC_FDSS_REGN             0x2000 // Region\r
#define V_PCH_SPI_FDOC_FDSS_MSTR             0x3000 // Master\r
#define V_PCH_SPI_FDOC_FDSS_VLVS             0x4000 // Soft Straps\r
#define B_PCH_SPI_FDOC_FDSI_MASK             0x0FFC // Flash Descriptor Section Index\r
\r
#define R_PCH_SPI_FDOD                       0xB4  // Flash Descriptor Observability Data Register (32 bits)\r
\r
#define R_PCH_SPI_BCR                        0xFC  // BIOS Control Register\r
#define S_PCH_SPI_BCR                        1\r
#define B_PCH_SPI_BCR_SMM_BWP                BIT5  // SMM BIOS Write Protect Disable\r
#define B_PCH_SPI_BCR_SRC                    (BIT3 | BIT2) // SPI Read Configuration (SRC)\r
#define V_PCH_SPI_BCR_SRC_PREF_EN_CACHE_EN   0x08  // Prefetch Enable, Cache Enable\r
#define V_PCH_SPI_BCR_SRC_PREF_DIS_CACHE_DIS 0x04  // Prefetch Disable, Cache Disable\r
#define V_PCH_SPI_BCR_SRC_PREF_DIS_CACHE_EN  0x00  // Prefetch Disable, Cache Enable\r
#define B_PCH_SPI_BCR_BLE                    BIT1  // Lock Enable (LE)\r
#define B_PCH_SPI_BCR_BIOSWE                 BIT0  // Write Protect Disable (WPD)\r
#define N_PCH_SPI_BCR_BLE                    1\r
#define N_PCH_SPI_BCR_BIOSWE                 0\r
\r
//\r
// Flash Descriptor Base Address Region (FDBAR) from Flash Region 0\r
//\r
#define R_PCH_SPI_FDBAR_FLVALSIG             0x00  // Flash Valid Signature\r
#define V_PCH_SPI_FDBAR_FLVALSIG             0x0FF0A55A\r
\r
#endif\r
Commit	Line	Data
3cbfba02 DW	1	/**\r
	2	\r
	3	Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved\r
	4	\r
	5	This program and the accompanying materials are licensed and made available under\r
	6	the terms and conditions of the BSD License that accompanies this distribution.\r
	7	The full text of the license may be found at\r
	8	http://opensource.org/licenses/bsd-license.php.\r
	9	\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	12	\r
	13	\r
	14	\r
	15	@file\r
	16	PchRegsSpi.h\r
	17	\r
	18	@brief\r
	19	Register names for PCH SPI device.\r
	20	\r
	21	Conventions:\r
	22	\r
	23	- Prefixes:\r
	24	Definitions beginning with "R_" are registers\r
	25	Definitions beginning with "B_" are bits within registers\r
	26	Definitions beginning with "V_" are meaningful values of bits within the registers\r
	27	Definitions beginning with "S_" are register sizes\r
	28	Definitions beginning with "N_" are the bit position\r
	29	- In general, PCH registers are denoted by "_PCH_" in register names\r
	30	- Registers / bits that are different between PCH generations are denoted by\r
	31	"_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"\r
	32	- Registers / bits that are different between SKUs are denoted by "_<SKU_name>"\r
	33	at the end of the register/bit names\r
	34	- Registers / bits of new devices introduced in a PCH generation will be just named\r
	35	as "_PCH_" without <generation_name> inserted.\r
	36	\r
	37	**/\r
	38	#ifndef _PCH_REGS_SPI_H_\r
	39	#define _PCH_REGS_SPI_H_\r
	40	\r
	41	///\r
	42	/// SPI Host Interface Registers\r
	43	///\r
	44	\r
	45	#define R_PCH_SPI_HSFS 0x04 // Hardware Sequencing Flash Status Register (16bits)\r
	46	#define B_PCH_SPI_HSFS_FLOCKDN BIT15 // Flash Configuration Lock-Down\r
	47	#define B_PCH_SPI_HSFS_FDV BIT14 // Flash Descriptor Valid\r
	48	#define B_PCH_SPI_HSFS_FDOPSS BIT13 // Flash Descriptor Override Pin-Strap Status\r
	49	#define B_PCH_SPI_HSFS_SCIP BIT5 // SPI Cycle in Progress\r
	50	#define B_PCH_SPI_HSFS_BERASE_MASK (BIT4 \| BIT3) // Block / Sector Erase Size\r
	51	#define V_PCH_SPI_HSFS_BERASE_256B 0x00 // Block/Sector = 256 Bytes\r
	52	#define V_PCH_SPI_HSFS_BERASE_4K 0x01 // Block/Sector = 4K Bytes\r
	53	#define V_PCH_SPI_HSFS_BERASE_8K 0x10 // Block/Sector = 8K Bytes\r
	54	#define V_PCH_SPI_HSFS_BERASE_64K 0x11 // Block/Sector = 64K Bytes\r
	55	#define B_PCH_SPI_HSFS_AEL BIT2 // Access Error Log\r
	56	#define B_PCH_SPI_HSFS_FCERR BIT1 // Flash Cycle Error\r
	57	#define B_PCH_SPI_HSFS_FDONE BIT0 // Flash Cycle Done\r
	58	\r
	59	#define R_PCH_SPI_PR0 0x74 // Protected Region 0 Register\r
	60	#define B_PCH_SPI_PR0_WPE BIT31 // Write Protection Enable\r
	61	#define B_PCH_SPI_PR0_PRL_MASK 0x1FFF0000 // Protected Range Limit Mask, [28:16] here represents upper limit of address [24:12]\r
	62	#define B_PCH_SPI_PR0_RPE BIT15 // Read Protection Enable\r
	63	#define B_PCH_SPI_PR0_PRB_MASK 0x00001FFF // Protected Range Base Mask, [12:0] here represents base limit of address [24:12]\r
	64	\r
65	#define R_PCH_SPI_PREOP 0x94 // Prefix Opcode Configuration Register (16 bits)\r
66	#define B_PCH_SPI_PREOP1_MASK 0xFF00 // Prefix Opcode 1 Mask\r
67	#define B_PCH_SPI_PREOP0_MASK 0x00FF // Prefix Opcode 0 Mask\r
68	\r
69	#define R_PCH_SPI_OPTYPE 0x96 // Opcode Type Configuration\r
70	#define B_PCH_SPI_OPTYPE7_MASK (BIT15 \| BIT14) // Opcode Type 7 Mask\r
71	#define B_PCH_SPI_OPTYPE6_MASK (BIT13 \| BIT12) // Opcode Type 6 Mask\r
72	#define B_PCH_SPI_OPTYPE5_MASK (BIT11 \| BIT10) // Opcode Type 5 Mask\r
73	#define B_PCH_SPI_OPTYPE4_MASK (BIT9 \| BIT8) // Opcode Type 4 Mask\r
74	#define B_PCH_SPI_OPTYPE3_MASK (BIT7 \| BIT6) // Opcode Type 3 Mask\r
75	#define B_PCH_SPI_OPTYPE2_MASK (BIT5 \| BIT4) // Opcode Type 2 Mask\r
76	#define B_PCH_SPI_OPTYPE1_MASK (BIT3 \| BIT2) // Opcode Type 1 Mask\r
77	#define B_PCH_SPI_OPTYPE0_MASK (BIT1 \| BIT0) // Opcode Type 0 Mask\r
78	#define V_PCH_SPI_OPTYPE_RDNOADDR 0x00 // Read cycle type without address\r
79	#define V_PCH_SPI_OPTYPE_WRNOADDR 0x01 // Write cycle type without address\r
80	#define V_PCH_SPI_OPTYPE_RDADDR 0x02 // Address required; Read cycle type\r
81	#define V_PCH_SPI_OPTYPE_WRADDR 0x03 // Address required; Write cycle type\r
82	\r
83	#define R_PCH_SPI_OPMENU0 0x98 // Opcode Menu Configuration 0 (32bits)\r
84	#define R_PCH_SPI_OPMENU1 0x9C // Opcode Menu Configuration 1 (32bits)\r
85	\r
86	#define R_PCH_SPI_IND_LOCK 0xA4 // Indvidual Lock\r
87	#define B_PCH_SPI_IND_LOCK_PR0 BIT2 // PR0 LockDown\r
88	\r
89	\r
90	#define R_PCH_SPI_FDOC 0xB0 // Flash Descriptor Observability Control Register (32 bits)\r
91	#define B_PCH_SPI_FDOC_FDSS_MASK (BIT14 \| BIT13 \| BIT12) // Flash Descriptor Section Select\r
92	#define V_PCH_SPI_FDOC_FDSS_FSDM 0x0000 // Flash Signature and Descriptor Map\r
93	#define V_PCH_SPI_FDOC_FDSS_COMP 0x1000 // Component\r
94	#define V_PCH_SPI_FDOC_FDSS_REGN 0x2000 // Region\r
95	#define V_PCH_SPI_FDOC_FDSS_MSTR 0x3000 // Master\r
96	#define V_PCH_SPI_FDOC_FDSS_VLVS 0x4000 // Soft Straps\r
97	#define B_PCH_SPI_FDOC_FDSI_MASK 0x0FFC // Flash Descriptor Section Index\r
98	\r
99	#define R_PCH_SPI_FDOD 0xB4 // Flash Descriptor Observability Data Register (32 bits)\r
100	\r
101	#define R_PCH_SPI_BCR 0xFC // BIOS Control Register\r
102	#define S_PCH_SPI_BCR 1\r
103	#define B_PCH_SPI_BCR_SMM_BWP BIT5 // SMM BIOS Write Protect Disable\r
104	#define B_PCH_SPI_BCR_SRC (BIT3 \| BIT2) // SPI Read Configuration (SRC)\r
105	#define V_PCH_SPI_BCR_SRC_PREF_EN_CACHE_EN 0x08 // Prefetch Enable, Cache Enable\r
106	#define V_PCH_SPI_BCR_SRC_PREF_DIS_CACHE_DIS 0x04 // Prefetch Disable, Cache Disable\r
107	#define V_PCH_SPI_BCR_SRC_PREF_DIS_CACHE_EN 0x00 // Prefetch Disable, Cache Enable\r
108	#define B_PCH_SPI_BCR_BLE BIT1 // Lock Enable (LE)\r
109	#define B_PCH_SPI_BCR_BIOSWE BIT0 // Write Protect Disable (WPD)\r
110	#define N_PCH_SPI_BCR_BLE 1\r
111	#define N_PCH_SPI_BCR_BIOSWE 0\r
112	\r
113	//\r
114	// Flash Descriptor Base Address Region (FDBAR) from Flash Region 0\r
115	//\r
116	#define R_PCH_SPI_FDBAR_FLVALSIG 0x00 // Flash Valid Signature\r
117	#define V_PCH_SPI_FDBAR_FLVALSIG 0x0FF0A55A\r
118	\r
119	#endif\r