projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3cbfba02 DW |
1 | /**\r |
| 2 | \r | |
| 3 | Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved\r | |
| 4 | \r | |
| 7ede8060 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 3cbfba02 DW |
6 | \r |
| 7 | \r | |
| 8 | \r | |
| 9 | @file\r | |
| 10 | PchRegsUsb.h\r | |
| 11 | \r | |
| 12 | @brief\r | |
| 13 | Register names for PCH USB devices.\r | |
| 14 | \r | |
| 15 | Conventions:\r | |
| 16 | \r | |
| 17 | - Prefixes:\r | |
| 18 | Definitions beginning with "R_" are registers\r | |
| 19 | Definitions beginning with "B_" are bits within registers\r | |
| 20 | Definitions beginning with "V_" are meaningful values of bits within the registers\r | |
| 21 | Definitions beginning with "S_" are register sizes\r | |
| 22 | Definitions beginning with "N_" are the bit position\r | |
| 23 | - In general, PCH registers are denoted by "_PCH_" in register names\r | |
| 24 | - Registers / bits that are different between PCH generations are denoted by\r | |
| 25 | "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"\r | |
| 26 | - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"\r | |
| 27 | at the end of the register/bit names\r | |
| 28 | - Registers / bits of new devices introduced in a PCH generation will be just named\r | |
| 29 | as "_PCH_" without <generation_name> inserted.\r | |
| 30 | \r | |
| 31 | **/\r | |
| 32 | #ifndef _PCH_REGS_USB_H_\r | |
| 33 | #define _PCH_REGS_USB_H_\r | |
| 34 | \r | |
| 35 | ///\r | |
| 36 | /// USB Definitions\r | |
| 37 | ///\r | |
| 38 | \r | |
| 39 | typedef enum {\r | |
| 40 | PchEhci1 = 0,\r | |
| 41 | PchEhciControllerMax\r | |
| 42 | } PCH_USB20_CONTROLLER_TYPE;\r | |
| 43 | \r | |
| 44 | #define PCH_USB_MAX_PHYSICAL_PORTS 4 /// Max Physical Connector EHCI + XHCI, not counting virtual ports like USB-R.\r | |
| 45 | #define PCH_EHCI_MAX_PORTS 4 /// Counting ports behind RMHs 8 from EHCI-1 and 6 from EHCI-2, not counting EHCI USB-R virtual ports.\r | |
| 46 | #define PCH_HSIC_MAX_PORTS 2\r | |
| 47 | #define PCH_XHCI_MAX_USB3_PORTS 1\r | |
| 48 | \r | |
| 49 | #define PCI_DEVICE_NUMBER_PCH_USB 29\r | |
| 50 | #define PCI_FUNCTION_NUMBER_PCH_EHCI 0\r | |
| 51 | \r | |
| 52 | #define R_PCH_USB_VENDOR_ID 0x00 // Vendor ID\r | |
| 53 | #define V_PCH_USB_VENDOR_ID V_PCH_INTEL_VENDOR_ID\r | |
| 54 | \r | |
| 55 | #define R_PCH_USB_DEVICE_ID 0x02 // Device ID\r | |
| 56 | #define V_PCH_USB_DEVICE_ID_0 0x0F34 // EHCI#1\r | |
| 57 | \r | |
| 58 | #define R_PCH_EHCI_SVID 0x2C // USB2 Subsystem Vendor ID\r | |
| 59 | #define B_PCH_EHCI_SVID 0xFFFF // USB2 Subsystem Vendor ID Mask\r | |
| 60 | \r | |
| 61 | #define R_PCH_EHCI_PWR_CNTL_STS 0x54 // Power Management Control / Status\r | |
| 62 | #define B_PCH_EHCI_PWR_CNTL_STS_PME_STS BIT15 // PME Status\r | |
| 63 | #define B_PCH_EHCI_PWR_CNTL_STS_DATASCL (BIT14 | BIT13) // Data Scale\r | |
| 64 | #define B_PCH_EHCI_PWR_CNTL_STS_DATASEL (BIT12 | BIT11 | BIT10 | BIT9) // Data Select\r | |
| 65 | #define B_PCH_EHCI_PWR_CNTL_STS_PME_EN BIT8 // Power Enable\r | |
| 66 | #define B_PCH_EHCI_PWR_CNTL_STS_PWR_STS (BIT1 | BIT0) // Power State\r | |
| 67 | #define V_PCH_EHCI_PWR_CNTL_STS_PWR_STS_D0 0 // D0 State\r | |
| 68 | #define V_PCH_EHCI_PWR_CNTL_STS_PWR_STS_D3 (BIT1 | BIT0) // D3 Hot State\r | |
| 69 | \r | |
| 70 | ///\r | |
| 71 | /// USB3 (XHCI) related definitions\r | |
| 72 | ///\r | |
| 73 | #define PCI_DEVICE_NUMBER_PCH_XHCI 20\r | |
| 74 | #define PCI_FUNCTION_NUMBER_PCH_XHCI 0\r | |
| 75 | //\r | |
| 76 | /////\r | |
| 77 | ///// XHCI PCI Config Space registers\r | |
| 78 | /////\r | |
| 79 | \r | |
| 80 | #define R_PCH_XHCI_SVID 0x2C\r | |
| 81 | #define B_PCH_XHCI_SVID 0xFFFF\r | |
| 82 | \r | |
| 83 | \r | |
| 84 | #define R_PCH_XHCI_PWR_CNTL_STS 0x74\r | |
| 85 | #define B_PCH_XHCI_PWR_CNTL_STS_PME_STS BIT15\r | |
| 86 | #define B_PCH_XHCI_PWR_CNTL_STS_DATASCL (BIT14 | BIT13)\r | |
| 87 | #define B_PCH_XHCI_PWR_CNTL_STS_DATASEL (BIT12 | BIT11 | BIT10 | BIT9)\r | |
| 88 | #define B_PCH_XHCI_PWR_CNTL_STS_PME_EN BIT8\r | |
| 89 | #define B_PCH_XHCI_PWR_CNTL_STS_PWR_STS (BIT1 | BIT0)\r | |
| 90 | #define V_PCH_XHCI_PWR_CNTL_STS_PWR_STS_D3 (BIT1 | BIT0)\r | |
| 91 | \r | |
| 92 | #endif\r |