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1 | /**\r |
2 | **/\r | |
3 | /**\r | |
4 | \r | |
5 | Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved\r | |
6 | \r | |
7 | This program and the accompanying materials are licensed and made available under\r | |
8 | the terms and conditions of the BSD License that accompanies this distribution.\r | |
9 | The full text of the license may be found at\r | |
10 | http://opensource.org/licenses/bsd-license.php.\r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | \r | |
15 | \r | |
16 | \r | |
17 | @file\r | |
18 | PchPlatformPolicy.h\r | |
19 | \r | |
20 | @brief\r | |
21 | PCH policy PPI produced by a platform driver specifying various\r | |
22 | expected PCH settings. This PPI is consumed by the PCH PEI modules.\r | |
23 | \r | |
24 | **/\r | |
25 | #ifndef PCH_PLATFORM_POLICY_H_\r | |
26 | #define PCH_PLATFORM_POLICY_H_\r | |
27 | //\r | |
28 | // External include files do NOT need to be explicitly specified in real EDKII\r | |
29 | // environment\r | |
30 | //\r | |
31 | \r | |
32 | \r | |
33 | #include "PchRegs.h"\r | |
34 | \r | |
35 | //\r | |
36 | #define PCH_PLATFORM_POLICY_PPI_GUID \\r | |
37 | { \\r | |
38 | 0x15344673, 0xd365, 0x4be2, 0x85, 0x13, 0x14, 0x97, 0xcc, 0x7, 0x61, 0x1d \\r | |
39 | }\r | |
40 | \r | |
41 | extern EFI_GUID gPchPlatformPolicyPpiGuid;\r | |
42 | \r | |
43 | ///\r | |
44 | /// Forward reference for ANSI C compatibility\r | |
45 | ///\r | |
46 | typedef struct _PCH_PLATFORM_POLICY_PPI PCH_PLATFORM_POLICY_PPI;\r | |
47 | \r | |
48 | ///\r | |
49 | /// PPI revision number\r | |
50 | /// Any backwards compatible changes to this PPI will result in an update in the revision number\r | |
51 | /// Major changes will require publication of a new PPI\r | |
52 | ///\r | |
53 | /// Revision 1: Original version\r | |
54 | ///\r | |
55 | #define PCH_PLATFORM_POLICY_PPI_REVISION_1 1\r | |
56 | #define PCH_PLATFORM_POLICY_PPI_REVISION_2 2\r | |
57 | #define PCH_PLATFORM_POLICY_PPI_REVISION_3 3\r | |
58 | #define PCH_PLATFORM_POLICY_PPI_REVISION_4 4\r | |
59 | #define PCH_PLATFORM_POLICY_PPI_REVISION_5 5\r | |
60 | //\r | |
61 | // Generic definitions for device enabling/disabling used by PCH code.\r | |
62 | //\r | |
63 | #define PCH_DEVICE_ENABLE 1\r | |
64 | #define PCH_DEVICE_DISABLE 0\r | |
65 | \r | |
66 | typedef struct {\r | |
67 | UINT8 ThermalDataReportEnable : 1; // OBSOLETE from Revision 5 !!! DO NOT USE !!!\r | |
68 | UINT8 MchTempReadEnable : 1;\r | |
69 | UINT8 PchTempReadEnable : 1;\r | |
70 | UINT8 CpuEnergyReadEnable : 1;\r | |
71 | UINT8 CpuTempReadEnable : 1;\r | |
72 | UINT8 Cpu2TempReadEnable : 1;\r | |
73 | UINT8 TsOnDimmEnable : 1;\r | |
74 | UINT8 Dimm1TempReadEnable : 1;\r | |
75 | \r | |
76 | UINT8 Dimm2TempReadEnable : 1;\r | |
77 | UINT8 Dimm3TempReadEnable : 1;\r | |
78 | UINT8 Dimm4TempReadEnable : 1;\r | |
79 | UINT8 Rsvdbits : 5;\r | |
80 | } PCH_THERMAL_REPORT_CONTROL;\r | |
81 | //\r | |
82 | // ---------------------------- HPET Config -----------------------------\r | |
83 | //\r | |
84 | typedef struct {\r | |
85 | BOOLEAN Enable; /// Determines if enable HPET function\r | |
86 | UINT32 Base; /// The HPET base address\r | |
87 | } PCH_HPET_CONFIG;\r | |
88 | \r | |
89 | \r | |
90 | ///\r | |
91 | /// ---------------------------- SATA Config -----------------------------\r | |
92 | ///\r | |
93 | typedef enum {\r | |
94 | PchSataModeIde,\r | |
95 | PchSataModeAhci,\r | |
96 | PchSataModeRaid,\r | |
97 | PchSataModeMax\r | |
98 | } PCH_SATA_MODE;\r | |
99 | \r | |
100 | ///\r | |
101 | /// ---------------------------- PCI Express Config -----------------------------\r | |
102 | ///\r | |
103 | typedef enum {\r | |
104 | PchPcieAuto,\r | |
105 | PchPcieGen1,\r | |
106 | PchPcieGen2\r | |
107 | } PCH_PCIE_SPEED;\r | |
108 | \r | |
109 | typedef struct {\r | |
110 | PCH_PCIE_SPEED PcieSpeed[PCH_PCIE_MAX_ROOT_PORTS];\r | |
111 | } PCH_PCIE_CONFIG;\r | |
112 | \r | |
113 | ///\r | |
114 | /// ---------------------------- IO APIC Config -----------------------------\r | |
115 | ///\r | |
116 | typedef struct {\r | |
117 | UINT8 IoApicId;\r | |
118 | } PCH_IOAPIC_CONFIG;\r | |
119 | \r | |
120 | ///\r | |
121 | /// --------------------- Low Power Input Output Config ------------------------\r | |
122 | ///\r | |
123 | typedef struct {\r | |
124 | UINT8 LpssPciModeEnabled : 1; /// Determines if LPSS PCI Mode enabled\r | |
125 | UINT8 Dma0Enabled : 1; /// Determines if LPSS DMA1 enabled\r | |
126 | UINT8 Dma1Enabled : 1; /// Determines if LPSS DMA2 enabled\r | |
127 | UINT8 I2C0Enabled : 1; /// Determines if LPSS I2C #1 enabled\r | |
128 | UINT8 I2C1Enabled : 1; /// Determines if LPSS I2C #2 enabled\r | |
129 | UINT8 I2C2Enabled : 1; /// Determines if LPSS I2C #3 enabled\r | |
130 | UINT8 I2C3Enabled : 1; /// Determines if LPSS I2C #4 enabled\r | |
131 | UINT8 I2C4Enabled : 1; /// Determines if LPSS I2C #5 enabled\r | |
132 | UINT8 I2C5Enabled : 1; /// Determines if LPSS I2C #6 enabled\r | |
133 | UINT8 I2C6Enabled : 1; /// Determines if LPSS I2C #7 enabled\r | |
134 | UINT8 Pwm0Enabled : 1; /// Determines if LPSS PWM #1 enabled\r | |
135 | UINT8 Pwm1Enabled : 1; /// Determines if LPSS PWM #2 enabled\r | |
136 | UINT8 Hsuart0Enabled : 1; /// Determines if LPSS HSUART #1 enabled\r | |
137 | UINT8 Hsuart1Enabled : 1; /// Determines if LPSS HSUART #2 enabled\r | |
138 | UINT8 SpiEnabled : 1; /// Determines if LPSS SPI enabled\r | |
139 | UINT8 Rsvdbits : 2;\r | |
140 | } PEI_PCH_LPSS_CONFIG;\r | |
141 | \r | |
142 | ///\r | |
143 | /// ------------ General PCH Platform Policy PPI definition ------------\r | |
144 | ///\r | |
145 | struct _PCH_PLATFORM_POLICY_PPI {\r | |
146 | UINT8 Revision;\r | |
147 | UINT8 BusNumber; // Bus Number of the PCH device\r | |
148 | UINT32 SpiBase; // SPI Base Address.\r | |
149 | UINT32 PmcBase; // PMC Base Address.\r | |
150 | UINT32 SmbmBase; // SMB Memory Base Address.\r | |
151 | UINT32 IoBase; // IO Base Address.\r | |
152 | UINT32 IlbBase; // Intel Legacy Block Base Address.\r | |
153 | UINT32 PUnitBase; // PUnit Base Address.\r | |
154 | UINT32 Rcba; // Root Complex Base Address.\r | |
155 | UINT32 MphyBase; // MPHY Base Address.\r | |
156 | UINT16 AcpiBase; // ACPI I/O Base address.\r | |
157 | UINT16 GpioBase; // GPIO Base address\r | |
158 | PCH_HPET_CONFIG *HpetConfig;\r | |
159 | PCH_SATA_MODE SataMode;\r | |
160 | PCH_PCIE_CONFIG *PcieConfig;\r | |
161 | PCH_IOAPIC_CONFIG *IoApicConfig;\r | |
162 | PEI_PCH_LPSS_CONFIG *LpssConfig;\r | |
163 | BOOLEAN EnableRmh; // Determines if enable USB RMH function\r | |
164 | BOOLEAN EhciPllCfgEnable;\r | |
165 | };\r | |
166 | \r | |
167 | #endif\r |