[mirror_edk2.git] / Vlv2DeviceRefCodePkg / ValleyView2Soc / SouthCluster / Include / Ppi / Sdhc.h

/**\r
**/\r
/**\r
\r
Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved\r
\r
  This program and the accompanying materials are licensed and made available under\r
  the terms and conditions of the BSD License that accompanies this distribution.\r
  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php.\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
\r
\r
  @file\r
  Spi.h\r
\r
  @brief\r
  This file defines the EFI SPI PPI which implements the\r
  Intel(R) PCH SPI Host Controller Compatibility Interface.\r
\r
**/\r
#ifndef _PEI_SDHC_H_\r
#define _PEI_SDHC_H_\r
\r
\r
\r
//\r
#define PEI_SDHC_PPI_GUID \\r
  {  \\r
    0xf4ef9d7a, 0x98c5, 0x4c1a, 0xb4, 0xd9, 0xd8, 0xd8, 0x72, 0x65, 0xbe, 0xc \\r
  }\r
typedef struct _PEI_SD_CONTROLLER_PPI PEI_SD_CONTROLLER_PPI;\r
\r
#define EFI_SD_HOST_IO_PROTOCOL_REVISION_01          0x01\r
\r
typedef enum {\r
  ResponseNo = 0,\r
  ResponseR1,\r
  ResponseR1b,\r
  ResponseR2,\r
  ResponseR3,\r
  ResponseR4,\r
  ResponseR5,\r
  ResponseR5b,\r
  ResponseR6,\r
  ResponseR7\r
} RESPONSE_TYPE;\r
\r
typedef enum {\r
  NoData = 0,\r
  InData,\r
  OutData\r
} TRANSFER_TYPE;\r
\r
typedef enum {\r
  Reset_Auto = 0,\r
  Reset_DAT,\r
  Reset_CMD,\r
  Reset_DAT_CMD,\r
  Reset_All\r
} RESET_TYPE;\r
\r
\r
\r
typedef enum {\r
  SDMA = 0,\r
  ADMA2,\r
  PIO\r
} DMA_MOD;\r
\r
typedef struct {\r
  UINT32  HighSpeedSupport:    1;  //High speed supported\r
  UINT32  V18Support:          1;  //1.8V supported\r
  UINT32  V30Support:          1;  //3.0V supported\r
  UINT32  V33Support:          1;  //3.3V supported\r
  UINT32  Reserved0:           4;\r
  UINT32  BusWidth4:           1;  // 4 bit width\r
  UINT32  BusWidth8:           1;  // 8 bit width\r
  UINT32  Reserved1:           6;\r
  UINT32  SDMASupport:         1;\r
  UINT32  ADMA2Support:        1;\r
  UINT32  DmaMode:             2;\r
  UINT32  Reserved2:           12;\r
  UINT32  BoundarySize;\r
}HOST_CAPABILITY;\r
\r
\r
#define PCI_SUBCLASS_SD_HOST_CONTROLLER   0x05\r
#define PCI_IF_STANDARD_HOST_NO_DMA       0x00\r
#define PCI_IF_STANDARD_HOST_SUPPORT_DMA  0x01\r
\r
//\r
//MMIO Registers definition for MMC/SDIO controller\r
//\r
#define  MMIO_DMAADR                     0x00\r
#define  MMIO_BLKSZ                      0x04\r
#define  MMIO_BLKCNT                     0x06\r
#define  MMIO_CMDARG                     0x08\r
#define  MMIO_XFRMODE                    0x0C\r
#define  MMIO_SDCMD                      0x0E\r
#define  MMIO_RESP                       0x10\r
#define  MMIO_BUFDATA                    0x20\r
#define  MMIO_PSTATE                     0x24\r
#define  MMIO_HOSTCTL                    0x28\r
#define  MMIO_PWRCTL                     0x29\r
#define  MMIO_BLKGAPCTL                  0x2A\r
#define  MMIO_WAKECTL                    0x2B\r
#define  MMIO_CLKCTL                     0x2C\r
#define  MMIO_TOCTL                      0x2E\r
#define  MMIO_SWRST                      0x2F\r
#define  MMIO_NINTSTS                    0x30\r
#define  MMIO_ERINTSTS                   0x32\r
#define  MMIO_NINTEN                     0x34\r
#define  MMIO_ERINTEN                    0x36\r
#define  MMIO_NINTSIGEN                  0x38\r
#define  MMIO_ERINTSIGEN                 0x3A\r
#define  MMIO_AC12ERRSTS                 0x3C\r
#define  MMIO_HOST_CTL2                  0x3E //hphang <- New in VLV2\r
#define  MMIO_CAP                        0x40\r
#define  MMIO_CAP2                       0x44 //hphang <- New in VLV2\r
#define  MMIO_MCCAP                      0x48\r
#define  MMIO_FORCEEVENTCMD12ERRSTAT     0x50 //hphang <- New in VLV2\r
#define  MMIO_FORCEEVENTERRINTSTAT       0x52 //hphang <- New in VLV2\r
#define  MMIO_ADMAERRSTAT                0x54 //hphang <- New in VLV2\r
#define  MMIO_ADMASYSADDR                0x58 //hphang <- New in VLV2\r
#define  MMIO_PRESETVALUE0               0x60 //hphang <- New in VLV2\r
#define  MMIO_PRESETVALUE1               0x64 //hphang <- New in VLV2\r
#define  MMIO_PRESETVALUE2               0x68 //hphang <- New in VLV2\r
#define  MMIO_PRESETVALUE3               0x6C //hphang <- New in VLV2\r
#define  MMIO_BOOTTIMEOUTCTRL            0x70 //hphang <- New in VLV2\r
#define  MMIO_DEBUGSEL                   0x74 //hphang <- New in VLV2\r
#define  MMIO_SHAREDBUS                  0xE0 //hphang <- New in VLV2\r
#define  MMIO_SPIINTSUP                  0xF0 //hphang <- New in VLV2\r
#define  MMIO_SLTINTSTS                  0xFC\r
#define  MMIO_CTRLRVER                   0xFE\r
#define  MMIO_SRST                       0x1FC\r
\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_SD_CONTROLLER_PPI_SEND_COMMAND) (\r
  IN  PEI_SD_CONTROLLER_PPI       *This,\r
  IN   UINT16                     CommandIndex,\r
  IN   UINT32                     Argument,\r
  IN   TRANSFER_TYPE              DataType,\r
  IN   UINT8                      *Buffer, OPTIONAL\r
  IN   UINT32                     BufferSize,\r
  IN   RESPONSE_TYPE              ResponseType,\r
  IN   UINT32                     TimeOut,\r
  OUT  UINT32                     *ResponseData OPTIONAL\r
  );\r
\r
/*++\r
\r
  Routine Description:\r
    Set max clock frequency of the host, the actual frequency\r
    may not be the same as MaxFrequency. It depends on\r
    the max frequency the host can support, divider, and host\r
    speed mode.\r
\r
  Arguments:\r
    This           - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
    MaxFrequency   - Max frequency in HZ\r
\r
  Returns:\r
    EFI_SUCCESS\r
    EFI_TIMEOUT\r
--*/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_SD_CONTROLLER_PPI_SET_CLOCK_FREQUENCY) (\r
  IN  PEI_SD_CONTROLLER_PPI      *This,\r
  IN  UINT32                     MaxFrequency\r
  );\r
\r
/*++\r
\r
  Routine Description:\r
    Set bus width of the host\r
\r
  Arguments:\r
    This       - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
    BusWidth   - Bus width in 1, 4, 8 bits\r
\r
  Returns:\r
    EFI_SUCCESS\r
    EFI_INVALID_PARAMETER\r
\r
--*/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_SD_CONTROLLER_PPI_SET_BUS_WIDTH) (\r
  IN  PEI_SD_CONTROLLER_PPI      *This,\r
  IN  UINT32                     BusWidth\r
  );\r
\r
/*++\r
\r
  Routine Description:\r
    Set Host mode in DDR\r
  Arguments:\r
    This      - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
    SetHostDdrMode   - True for DDR Mode set, false for normal mode\r
\r
  Returns:\r
    EFI_SUCCESS\r
    EFI_INVALID_PARAMETER\r
\r
--*/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE) (\r
  IN  PEI_SD_CONTROLLER_PPI    *This,\r
  IN  UINT32                     DdrMode\r
  );\r
\r
/*++\r
\r
  Routine Description:\r
    Set voltage which could supported by the host.\r
    Support 0(Power off the host), 1.8V, 3.0V, 3.3V\r
  Arguments:\r
    This      - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
    Voltage   - Units in 0.1 V\r
\r
  Returns:\r
    EFI_SUCCESS\r
    EFI_INVALID_PARAMETER\r
\r
--*/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_SD_CONTROLLER_PPI_SET_HOST_VOLTAGE) (\r
  IN  PEI_SD_CONTROLLER_PPI      *This,\r
  IN  UINT32                     Voltage\r
  );\r
\r
/*++\r
\r
  Routine Description:\r
   Reset the host\r
\r
  Arguments:\r
    This      - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
    ResetAll  - TRUE to reset all\r
\r
  Returns:\r
    EFI_SUCCESS\r
    EFI_TIMEOUT\r
\r
--*/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_SD_CONTROLLER_PPI_RESET_SD_HOST) (\r
  IN  PEI_SD_CONTROLLER_PPI      *This,\r
  IN  RESET_TYPE                 ResetType\r
  );\r
\r
/*++\r
\r
  Routine Description:\r
   Reset the host\r
\r
  Arguments:\r
    This    - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
    Enable  - TRUE to enable, FALSE to disable\r
\r
  Returns:\r
    EFI_SUCCESS\r
    EFI_TIMEOUT\r
\r
--*/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_SD_CONTROLLER_PPI_ENABLE_AUTO_STOP_CMD) (\r
  IN  PEI_SD_CONTROLLER_PPI      *This,\r
  IN  BOOLEAN                    Enable\r
  );\r
\r
/*++\r
\r
  Routine Description:\r
    Find whether these is a card inserted into the slot. If so\r
    init the host. If not, return EFI_NOT_FOUND.\r
\r
  Arguments:\r
    This      - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
\r
  Returns:\r
    EFI_SUCCESS\r
    EFI_NOT_FOUND\r
\r
--*/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_SD_CONTROLLER_PPI_DETECT_CARD_AND_INIT_HOST) (\r
  IN  PEI_SD_CONTROLLER_PPI      *This\r
  );\r
\r
/*++\r
\r
  Routine Description:\r
   Set the Block length\r
\r
  Arguments:\r
    This        - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
    BlockLength - card supportes block length\r
\r
  Returns:\r
    EFI_SUCCESS\r
    EFI_TIMEOUT\r
\r
--*/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_SD_CONTROLLER_PPI_SET_BLOCK_LENGTH) (\r
  IN  PEI_SD_CONTROLLER_PPI      *This,\r
  IN  UINT32                     BlockLength\r
  );\r
\r
/*++\r
\r
  Routine Description:\r
   Set the Block length\r
\r
  Arguments:\r
    This        - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
    BlockLength - card supportes block length\r
\r
  Returns:\r
    EFI_SUCCESS\r
    EFI_TIMEOUT\r
\r
--*/\r
\r
typedef EFI_STATUS\r
(EFIAPI *EFI_SD_CONTROLLER_PPI_SETUP_DEVICE)(\r
  IN  PEI_SD_CONTROLLER_PPI    *This\r
  );\r
\r
//\r
// Interface structure for the EFI SD Host I/O Protocol\r
//\r
struct _PEI_SD_CONTROLLER_PPI {\r
  UINT32                                           Revision;\r
  HOST_CAPABILITY                                  HostCapability;\r
  EFI_SD_CONTROLLER_PPI_SEND_COMMAND               SendCommand;\r
  EFI_SD_CONTROLLER_PPI_SET_CLOCK_FREQUENCY        SetClockFrequency;\r
  EFI_SD_CONTROLLER_PPI_SET_BUS_WIDTH              SetBusWidth;\r
  EFI_SD_CONTROLLER_PPI_SET_HOST_VOLTAGE           SetHostVoltage;\r
  EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE        SetHostDdrMode;\r
  EFI_SD_CONTROLLER_PPI_RESET_SD_HOST              ResetSdHost;\r
  EFI_SD_CONTROLLER_PPI_ENABLE_AUTO_STOP_CMD       EnableAutoStopCmd;\r
  EFI_SD_CONTROLLER_PPI_DETECT_CARD_AND_INIT_HOST  DetectCardAndInitHost;\r
  EFI_SD_CONTROLLER_PPI_SET_BLOCK_LENGTH           SetBlockLength;\r
  EFI_SD_CONTROLLER_PPI_SETUP_DEVICE               SetupDevice;\r
};\r
// Extern the GUID for PPI users.\r
//\r
extern EFI_GUID           gPeiSdhcPpiGuid;\r
\r
\r
#endif\r
Commit	Line	Data
3cbfba02 DW	1	/**\r
	2	**/\r
	3	/**\r
	4	\r
	5	Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved\r
	6	\r
	7	This program and the accompanying materials are licensed and made available under\r
	8	the terms and conditions of the BSD License that accompanies this distribution.\r
	9	The full text of the license may be found at\r
	10	http://opensource.org/licenses/bsd-license.php.\r
	11	\r
	12	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	13	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	14	\r
	15	\r
	16	\r
	17	@file\r
	18	Spi.h\r
	19	\r
	20	@brief\r
	21	This file defines the EFI SPI PPI which implements the\r
	22	Intel(R) PCH SPI Host Controller Compatibility Interface.\r
	23	\r
	24	**/\r
	25	#ifndef _PEI_SDHC_H_\r
	26	#define _PEI_SDHC_H_\r
	27	\r
	28	\r
	29	\r
	30	//\r
	31	#define PEI_SDHC_PPI_GUID \\r
	32	{ \\r
	33	0xf4ef9d7a, 0x98c5, 0x4c1a, 0xb4, 0xd9, 0xd8, 0xd8, 0x72, 0x65, 0xbe, 0xc \\r
	34	}\r
	35	typedef struct _PEI_SD_CONTROLLER_PPI PEI_SD_CONTROLLER_PPI;\r
	36	\r
	37	#define EFI_SD_HOST_IO_PROTOCOL_REVISION_01 0x01\r
	38	\r
	39	typedef enum {\r
	40	ResponseNo = 0,\r
	41	ResponseR1,\r
	42	ResponseR1b,\r
	43	ResponseR2,\r
	44	ResponseR3,\r
	45	ResponseR4,\r
	46	ResponseR5,\r
	47	ResponseR5b,\r
	48	ResponseR6,\r
	49	ResponseR7\r
	50	} RESPONSE_TYPE;\r
	51	\r
	52	typedef enum {\r
	53	NoData = 0,\r
	54	InData,\r
	55	OutData\r
	56	} TRANSFER_TYPE;\r
	57	\r
	58	typedef enum {\r
	59	Reset_Auto = 0,\r
	60	Reset_DAT,\r
	61	Reset_CMD,\r
	62	Reset_DAT_CMD,\r
	63	Reset_All\r
	64	} RESET_TYPE;\r
65	\r
66	\r
67	\r
68	typedef enum {\r
69	SDMA = 0,\r
70	ADMA2,\r
71	PIO\r
72	} DMA_MOD;\r
73	\r
74	typedef struct {\r
75	UINT32 HighSpeedSupport: 1; //High speed supported\r
76	UINT32 V18Support: 1; //1.8V supported\r
77	UINT32 V30Support: 1; //3.0V supported\r
78	UINT32 V33Support: 1; //3.3V supported\r
79	UINT32 Reserved0: 4;\r
80	UINT32 BusWidth4: 1; // 4 bit width\r
81	UINT32 BusWidth8: 1; // 8 bit width\r
82	UINT32 Reserved1: 6;\r
83	UINT32 SDMASupport: 1;\r
84	UINT32 ADMA2Support: 1;\r
85	UINT32 DmaMode: 2;\r
86	UINT32 Reserved2: 12;\r
87	UINT32 BoundarySize;\r
88	}HOST_CAPABILITY;\r
89	\r
90	\r
91	#define PCI_SUBCLASS_SD_HOST_CONTROLLER 0x05\r
92	#define PCI_IF_STANDARD_HOST_NO_DMA 0x00\r
93	#define PCI_IF_STANDARD_HOST_SUPPORT_DMA 0x01\r
94	\r
95	//\r
96	//MMIO Registers definition for MMC/SDIO controller\r
97	//\r
98	#define MMIO_DMAADR 0x00\r
99	#define MMIO_BLKSZ 0x04\r
100	#define MMIO_BLKCNT 0x06\r
101	#define MMIO_CMDARG 0x08\r
102	#define MMIO_XFRMODE 0x0C\r
103	#define MMIO_SDCMD 0x0E\r
104	#define MMIO_RESP 0x10\r
105	#define MMIO_BUFDATA 0x20\r
106	#define MMIO_PSTATE 0x24\r
107	#define MMIO_HOSTCTL 0x28\r
108	#define MMIO_PWRCTL 0x29\r
109	#define MMIO_BLKGAPCTL 0x2A\r
110	#define MMIO_WAKECTL 0x2B\r
111	#define MMIO_CLKCTL 0x2C\r
112	#define MMIO_TOCTL 0x2E\r
113	#define MMIO_SWRST 0x2F\r
114	#define MMIO_NINTSTS 0x30\r
115	#define MMIO_ERINTSTS 0x32\r
116	#define MMIO_NINTEN 0x34\r
117	#define MMIO_ERINTEN 0x36\r
118	#define MMIO_NINTSIGEN 0x38\r
119	#define MMIO_ERINTSIGEN 0x3A\r
120	#define MMIO_AC12ERRSTS 0x3C\r
121	#define MMIO_HOST_CTL2 0x3E //hphang <- New in VLV2\r
122	#define MMIO_CAP 0x40\r
123	#define MMIO_CAP2 0x44 //hphang <- New in VLV2\r
124	#define MMIO_MCCAP 0x48\r
125	#define MMIO_FORCEEVENTCMD12ERRSTAT 0x50 //hphang <- New in VLV2\r
126	#define MMIO_FORCEEVENTERRINTSTAT 0x52 //hphang <- New in VLV2\r
127	#define MMIO_ADMAERRSTAT 0x54 //hphang <- New in VLV2\r
128	#define MMIO_ADMASYSADDR 0x58 //hphang <- New in VLV2\r
129	#define MMIO_PRESETVALUE0 0x60 //hphang <- New in VLV2\r
130	#define MMIO_PRESETVALUE1 0x64 //hphang <- New in VLV2\r
131	#define MMIO_PRESETVALUE2 0x68 //hphang <- New in VLV2\r
132	#define MMIO_PRESETVALUE3 0x6C //hphang <- New in VLV2\r
133	#define MMIO_BOOTTIMEOUTCTRL 0x70 //hphang <- New in VLV2\r
134	#define MMIO_DEBUGSEL 0x74 //hphang <- New in VLV2\r
135	#define MMIO_SHAREDBUS 0xE0 //hphang <- New in VLV2\r
136	#define MMIO_SPIINTSUP 0xF0 //hphang <- New in VLV2\r
137	#define MMIO_SLTINTSTS 0xFC\r
138	#define MMIO_CTRLRVER 0xFE\r
139	#define MMIO_SRST 0x1FC\r
140	\r
141	typedef\r
142	EFI_STATUS\r
143	(EFIAPI *EFI_SD_CONTROLLER_PPI_SEND_COMMAND) (\r
144	IN PEI_SD_CONTROLLER_PPI *This,\r
145	IN UINT16 CommandIndex,\r
146	IN UINT32 Argument,\r
147	IN TRANSFER_TYPE DataType,\r
148	IN UINT8 *Buffer, OPTIONAL\r
149	IN UINT32 BufferSize,\r
150	IN RESPONSE_TYPE ResponseType,\r
151	IN UINT32 TimeOut,\r
152	OUT UINT32 *ResponseData OPTIONAL\r
153	);\r
154	\r
155	/*++\r
156	\r
157	Routine Description:\r
158	Set max clock frequency of the host, the actual frequency\r
159	may not be the same as MaxFrequency. It depends on\r
160	the max frequency the host can support, divider, and host\r
161	speed mode.\r
162	\r
163	Arguments:\r
164	This - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
165	MaxFrequency - Max frequency in HZ\r
166	\r
167	Returns:\r
168	EFI_SUCCESS\r
169	EFI_TIMEOUT\r
170	--*/\r
171	typedef\r
172	EFI_STATUS\r
173	(EFIAPI *EFI_SD_CONTROLLER_PPI_SET_CLOCK_FREQUENCY) (\r
174	IN PEI_SD_CONTROLLER_PPI *This,\r
175	IN UINT32 MaxFrequency\r
176	);\r
177	\r
178	/*++\r
179	\r
180	Routine Description:\r
181	Set bus width of the host\r
182	\r
183	Arguments:\r
184	This - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
185	BusWidth - Bus width in 1, 4, 8 bits\r
186	\r
187	Returns:\r
188	EFI_SUCCESS\r
189	EFI_INVALID_PARAMETER\r
190	\r
191	--*/\r
192	typedef\r
193	EFI_STATUS\r
194	(EFIAPI *EFI_SD_CONTROLLER_PPI_SET_BUS_WIDTH) (\r
195	IN PEI_SD_CONTROLLER_PPI *This,\r
196	IN UINT32 BusWidth\r
197	);\r
198	\r
199	/*++\r
200	\r
201	Routine Description:\r
202	Set Host mode in DDR\r
203	Arguments:\r
204	This - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
205	SetHostDdrMode - True for DDR Mode set, false for normal mode\r
206	\r
207	Returns:\r
208	EFI_SUCCESS\r
209	EFI_INVALID_PARAMETER\r
210	\r
211	--*/\r
212	typedef\r
213	EFI_STATUS\r
214	(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE) (\r
215	IN PEI_SD_CONTROLLER_PPI *This,\r
216	IN UINT32 DdrMode\r
217	);\r
218	\r
219	/*++\r
220	\r
221	Routine Description:\r
222	Set voltage which could supported by the host.\r
223	Support 0(Power off the host), 1.8V, 3.0V, 3.3V\r
224	Arguments:\r
225	This - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
226	Voltage - Units in 0.1 V\r
227	\r
228	Returns:\r
229	EFI_SUCCESS\r
230	EFI_INVALID_PARAMETER\r
231	\r
232	--*/\r
233	typedef\r
234	EFI_STATUS\r
235	(EFIAPI *EFI_SD_CONTROLLER_PPI_SET_HOST_VOLTAGE) (\r
236	IN PEI_SD_CONTROLLER_PPI *This,\r
237	IN UINT32 Voltage\r
238	);\r
239	\r
240	/*++\r
241	\r
242	Routine Description:\r
243	Reset the host\r
244	\r
245	Arguments:\r
246	This - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
247	ResetAll - TRUE to reset all\r
248	\r
249	Returns:\r
250	EFI_SUCCESS\r
251	EFI_TIMEOUT\r
252	\r
253	--*/\r
254	typedef\r
255	EFI_STATUS\r
256	(EFIAPI *EFI_SD_CONTROLLER_PPI_RESET_SD_HOST) (\r
257	IN PEI_SD_CONTROLLER_PPI *This,\r
258	IN RESET_TYPE ResetType\r
259	);\r
260	\r
261	/*++\r
262	\r
263	Routine Description:\r
264	Reset the host\r
265	\r
266	Arguments:\r
267	This - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
268	Enable - TRUE to enable, FALSE to disable\r
269	\r
270	Returns:\r
271	EFI_SUCCESS\r
272	EFI_TIMEOUT\r
273	\r
274	--*/\r
275	typedef\r
276	EFI_STATUS\r
277	(EFIAPI *EFI_SD_CONTROLLER_PPI_ENABLE_AUTO_STOP_CMD) (\r
278	IN PEI_SD_CONTROLLER_PPI *This,\r
279	IN BOOLEAN Enable\r
280	);\r
281	\r
282	/*++\r
283	\r
284	Routine Description:\r
285	Find whether these is a card inserted into the slot. If so\r
286	init the host. If not, return EFI_NOT_FOUND.\r
287	\r
288	Arguments:\r
289	This - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
290	\r
291	Returns:\r
292	EFI_SUCCESS\r
293	EFI_NOT_FOUND\r
294	\r
295	--*/\r
296	typedef\r
297	EFI_STATUS\r
298	(EFIAPI *EFI_SD_CONTROLLER_PPI_DETECT_CARD_AND_INIT_HOST) (\r
299	IN PEI_SD_CONTROLLER_PPI *This\r
300	);\r
301	\r
302	/*++\r
303	\r
304	Routine Description:\r
305	Set the Block length\r
306	\r
307	Arguments:\r
308	This - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
309	BlockLength - card supportes block length\r
310	\r
311	Returns:\r
312	EFI_SUCCESS\r
313	EFI_TIMEOUT\r
314	\r
315	--*/\r
316	typedef\r
317	EFI_STATUS\r
318	(EFIAPI *EFI_SD_CONTROLLER_PPI_SET_BLOCK_LENGTH) (\r
319	IN PEI_SD_CONTROLLER_PPI *This,\r
320	IN UINT32 BlockLength\r
321	);\r
322	\r
323	/*++\r
324	\r
325	Routine Description:\r
326	Set the Block length\r
327	\r
328	Arguments:\r
329	This - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
330	BlockLength - card supportes block length\r
331	\r
332	Returns:\r
333	EFI_SUCCESS\r
334	EFI_TIMEOUT\r
335	\r
336	--*/\r
337	\r
338	typedef EFI_STATUS\r
339	(EFIAPI *EFI_SD_CONTROLLER_PPI_SETUP_DEVICE)(\r
340	IN PEI_SD_CONTROLLER_PPI *This\r
341	);\r
342	\r
343	//\r
344	// Interface structure for the EFI SD Host I/O Protocol\r
345	//\r
346	struct _PEI_SD_CONTROLLER_PPI {\r
347	UINT32 Revision;\r
348	HOST_CAPABILITY HostCapability;\r
349	EFI_SD_CONTROLLER_PPI_SEND_COMMAND SendCommand;\r
350	EFI_SD_CONTROLLER_PPI_SET_CLOCK_FREQUENCY SetClockFrequency;\r
351	EFI_SD_CONTROLLER_PPI_SET_BUS_WIDTH SetBusWidth;\r
352	EFI_SD_CONTROLLER_PPI_SET_HOST_VOLTAGE SetHostVoltage;\r
353	EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE SetHostDdrMode;\r
354	EFI_SD_CONTROLLER_PPI_RESET_SD_HOST ResetSdHost;\r
355	EFI_SD_CONTROLLER_PPI_ENABLE_AUTO_STOP_CMD EnableAutoStopCmd;\r
356	EFI_SD_CONTROLLER_PPI_DETECT_CARD_AND_INIT_HOST DetectCardAndInitHost;\r
357	EFI_SD_CONTROLLER_PPI_SET_BLOCK_LENGTH SetBlockLength;\r
358	EFI_SD_CONTROLLER_PPI_SETUP_DEVICE SetupDevice;\r
359	};\r
360	// Extern the GUID for PPI users.\r
361	//\r
362	extern EFI_GUID gPeiSdhcPpiGuid;\r
363	\r
364	\r
365	#endif\r