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DW		 1/**\r
2**/\r
3/**\r
4\r
5Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved\r
6\r
7 This program and the accompanying materials are licensed and made available under\r
8 the terms and conditions of the BSD License that accompanies this distribution.\r
9 The full text of the license may be found at\r
10 http://opensource.org/licenses/bsd-license.php.\r
11\r
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14\r
15\r
16\r
17 @file\r
18 PchPlatformPolicy.h\r
19\r
20 @brief\r
21 PCH policy protocol produced by a platform driver specifying various\r
22 expected PCH settings. This protocol is consumed by the PCH drivers.\r
23\r
24**/\r
25#ifndef _PCH_PLATFORM_POLICY_H_\r
26#define _PCH_PLATFORM_POLICY_H_\r
27\r
28\r
29//\r
30#include "PchRegs.h"\r
31#ifndef ECP_FLAG\r
32#include "Uefi.h"\r
33#endif\r
34\r
35#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_GUID \\r
36 { \\r
37 0x4b0165a9, 0x61d6, 0x4e23, 0xa0, 0xb5, 0x3e, 0xc7, 0x9c, 0x2e, 0x30, 0xd5 \\r
38 }\r
39extern EFI_GUID gDxePchPlatformPolicyProtocolGuid;\r
40\r
41///\r
42/// Forward reference for ANSI C compatibility\r
43///\r
44typedef struct _DXE_PCH_PLATFORM_POLICY_PROTOCOL DXE_PCH_PLATFORM_POLICY_PROTOCOL;\r
45\r
46///\r
47/// Protocol revision number\r
48/// Any backwards compatible changes to this protocol will result in an update in the revision number\r
49/// Major changes will require publication of a new protocol\r
50///\r
51/// Revision 1: Original version\r
52///\r
53#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_1 1\r
54#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_2 2\r
55#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_3 3\r
56#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_4 4\r
57#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_5 5\r
58#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_6 6\r
59#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_7 7\r
60#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_8 8\r
61#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_9 9\r
62#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_10 10\r
63#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_11 11\r
64#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_12 12\r
65\r
66///\r
67/// Generic definitions for device enabling/disabling used by PCH code.\r
68///\r
69#define PCH_DEVICE_ENABLE 1\r
70#define PCH_DEVICE_DISABLE 0\r
71\r
72///\r
73/// ---------------------------- Device Enabling ------------------------------\r
74///\r
75/// PCH Device enablings\r
76///\r
77typedef struct {\r
78 UINT8 Lan : 1; /// 0: Disable; 1: Enable\r
79 UINT8 Azalia : 2; /// 0: Disable; 1: Enable; 2: Auto\r
80 UINT8 Sata : 1; /// 0: Disable; 1: Enable\r
81 UINT8 Smbus : 1; /// 0: Disable; 1: Enable\r
82 UINT8 LpeEnabled : 2; /// 0: Disabled; 1: PCI Mode 2: ACPI Mode\r
83 UINT8 Reserved[1]; /// Reserved fields for future expansion w/o protocol change\r
84} PCH_DEVICE_ENABLING;\r
85\r
86///\r
87/// ---------------------------- USB Config -----------------------------\r
88///\r
89///\r
90/// Overcurrent pins\r
91///\r
92typedef enum {\r
93 PchUsbOverCurrentPin0 = 0,\r
94 PchUsbOverCurrentPin1,\r
95 PchUsbOverCurrentPin2,\r
96 PchUsbOverCurrentPin3,\r
97 PchUsbOverCurrentPin4,\r
98 PchUsbOverCurrentPin5,\r
99 PchUsbOverCurrentPin6,\r
100 PchUsbOverCurrentPin7,\r
101 PchUsbOverCurrentPinSkip,\r
102 PchUsbOverCurrentPinMax\r
103} PCH_USB_OVERCURRENT_PIN;\r
104\r
105typedef struct {\r
106 UINT8 Enable : 1; /// 0: Disable; 1: Enable. This would take effect while UsbPerPortCtl is enabled\r
107 UINT8 Panel : 1; /// 0: Back Panel Port; 1: Front Panel Port.\r
108 UINT8 Dock : 1; /// 0: Not docking port; 1: Docking Port.\r
109 UINT8 Rsvdbits : 5;\r
110} PCH_USB_PORT_SETTINGS;\r
111\r
112typedef struct {\r
113 UINT8 Enable : 1; /// 0: Disable; 1: Enable\r
114 UINT8 Rsvdbits : 7;\r
115} PCH_USB20_CONTROLLER_SETTINGS;\r
116\r
117typedef struct {\r
118 UINT8 Enable : 2; /// 0: 0: Disabled; 1: PCI Mode 2: ACPI Mode\r
119 UINT8 Rsvdbits : 6;\r
120} PCH_USBOTG_CONTROLLER_SETTINGS;\r
121\r
122#define PCH_XHCI_MODE_OFF 0\r
123#define PCH_XHCI_MODE_ON 1\r
124#define PCH_XHCI_MODE_AUTO 2\r
125#define PCH_XHCI_MODE_SMARTAUTO 3\r
126\r
127#define PCH_EHCI_DEBUG_OFF 0\r
128#define PCH_EHCI_DEBUG_ON 1\r
129\r
130#define PCH_USB_FRONT_PANEL 1\r
131#define PCH_USB_BACK_PANEL 0\r
132\r
133typedef struct {\r
134 UINT8 Mode : 2; /// 0: Disable; 1: Enable, 2: Auto, 3: Smart Auto\r
135 UINT8 PreBootSupport : 1; /// 0: No xHCI driver available; 1: xHCI driver available\r
136 UINT8 XhciStreams : 1; /// 0: Disable; 1: Enable\r
137 UINT8 Rsvdbits : 4;\r
138} PCH_USB30_CONTROLLER_SETTINGS;\r
139\r
140typedef struct {\r
141 UINT8 UsbPerPortCtl : 1; /// 0: Disable; 1: Enable Per-port enable control\r
142 UINT8 Ehci1Usbr : 1; /// 0: Disable; 1: Enable EHCI 1 USBR\r
143 UINT8 RsvdBits : 6;\r
144 PCH_USB_PORT_SETTINGS PortSettings[PCH_USB_MAX_PHYSICAL_PORTS];\r
145 PCH_USB20_CONTROLLER_SETTINGS Usb20Settings[PchEhciControllerMax];\r
146 PCH_USB30_CONTROLLER_SETTINGS Usb30Settings;\r
147 PCH_USBOTG_CONTROLLER_SETTINGS UsbOtgSettings;\r
148 PCH_USB_OVERCURRENT_PIN Usb20OverCurrentPins[PCH_USB_MAX_PHYSICAL_PORTS];\r
149 PCH_USB_OVERCURRENT_PIN Usb30OverCurrentPins[PCH_XHCI_MAX_USB3_PORTS];\r
150 ///\r
151 /// The length of Usb Port to configure the USB transmitter,\r
152 /// Bits [16:4] represents length of Usb Port in inches using octal format and [3:0] is for the decimal Point.\r
153 ///\r
154 UINT16 Usb20PortLength[PCH_EHCI_MAX_PORTS];\r
155 UINT16 EhciDebug;\r
156 UINT16 UsbXhciLpmSupport;\r
157\r
158} PCH_USB_CONFIG;\r
159\r
160///\r
161/// ---------------------------- PCI Express Config ----------------------\r
162///\r
163/// The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature\r
164///\r
165typedef enum {\r
166 PchPcieAspmDisabled,\r
167 PchPcieAspmL0s,\r
168 PchPcieAspmL1,\r
169 PchPcieAspmL0sL1,\r
170 PchPcieAspmAutoConfig,\r
171 PchPcieAspmMax\r
172} PCH_PCI_EXPRESS_ASPM_CONTROL;\r
173\r
174///\r
175/// Refer to PCH EDS for the PCH implementation values corresponding\r
176/// to below PCI-E spec defined ranges\r
177///\r
178typedef enum {\r
179 PchPciECompletionTO_Default,\r
180 PchPciECompletionTO_50_100us,\r
181 PchPciECompletionTO_1_10ms,\r
182 PchPciECompletionTO_16_55ms,\r
183 PchPciECompletionTO_65_210ms,\r
184 PchPciECompletionTO_260_900ms,\r
185 PchPciECompletionTO_1_3P5s,\r
186 PchPciECompletionTO_4_13s,\r
187 PchPciECompletionTO_17_64s,\r
188 PchPciECompletionTO_Disabled\r
189} PCH_PCIE_COMPLETION_TIMEOUT;\r
190\r
191typedef struct {\r
192 UINT8 Enable : 1; /// Root Port enabling, 0: Disable; 1: Enable.\r
193 UINT8 Hide : 1; /// Whether or not to hide the configuration space of this port\r
194 UINT8 SlotImplemented : 1;\r
195 UINT8 HotPlug : 1;\r
196 UINT8 PmSci : 1;\r
197 UINT8 ExtSync : 1; /// Extended Synch\r
198 UINT8 Rsvdbits : 2;\r
199 ///\r
200 /// Error handlings\r
201 ///\r
202 UINT8 UnsupportedRequestReport : 1;\r
203 UINT8 FatalErrorReport : 1;\r
204 UINT8 NoFatalErrorReport : 1;\r
205 UINT8 CorrectableErrorReport : 1;\r
206 UINT8 PmeInterrupt : 1;\r
207 UINT8 SystemErrorOnFatalError : 1;\r
208 UINT8 SystemErrorOnNonFatalError : 1;\r
209 UINT8 SystemErrorOnCorrectableError : 1;\r
210\r
211 UINT8 AdvancedErrorReporting : 1;\r
212 UINT8 TransmitterHalfSwing : 1;\r
213 UINT8 Reserved : 6; /// Reserved fields for future expansion w/o protocol change\r
214\r
215 UINT8 FunctionNumber; /// The function number this root port is mapped to.\r
216 UINT8 PhysicalSlotNumber;\r
217 PCH_PCIE_COMPLETION_TIMEOUT CompletionTimeout;\r
218 PCH_PCI_EXPRESS_ASPM_CONTROL Aspm;\r
219} PCH_PCI_EXPRESS_ROOT_PORT_CONFIG;\r
220\r
221typedef struct {\r
222 /**\r
223 VendorId\r
224\r
225 The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID\r
226\r
227 DeviceId\r
228\r
229 The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID\r
230\r
231 RevId\r
232\r
233 The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings\r
234\r
235 BaseClassCode\r
236\r
237 The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class\r
238\r
239 SubClassCode\r
240\r
241 The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class\r
242\r
243\r
244 EndPointAspm\r
245\r
246 The override ASPM setting from End point\r
247 **/\r
248 UINT16 VendorId;\r
249 UINT16 DeviceId;\r
250 UINT8 RevId;\r
251 UINT8 BaseClassCode;\r
252 UINT8 SubClassCode;\r
253 PCH_PCI_EXPRESS_ASPM_CONTROL EndPointAspm;\r
254} PCH_PCIE_DEVICE_ASPM_OVERRIDE;\r
255\r
256typedef struct {\r
257 UINT16 VendorId; ///< PCI configuration space offset 0\r
258 UINT16 DeviceId; ///< PCI configuration space offset 2\r
259 UINT8 RevId; ///< PCI configuration space offset 8; 0xFF means all steppings\r
260 /**\r
261 SnoopLatency bit definition\r
262 Note: All Reserved bits must be set to 0\r
263\r
264 BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid\r
265 When clear values in bits 9:0 will be ignored\r
266 BITS[14:13] - Reserved\r
267 BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits\r
268 000b - 1 ns\r
269 001b - 32 ns\r
270 010b - 1024 ns\r
271 011b - 32,768 ns\r
272 100b - 1,048,576 ns\r
273 101b - 33,554,432 ns\r
274 110b - Reserved\r
275 111b - Reserved\r
276 BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied with\r
277 the scale in bits 12:10\r
278 **/\r
279 UINT16 SnoopLatency;\r
280 /**\r
281 NonSnoopLatency bit definition\r
282 Note: All Reserved bits must be set to 0\r
283\r
284 BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid\r
285 When clear values in bits 9:0 will be ignored\r
286 BITS[14:13] - Reserved\r
287 BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits\r
288 000b - 1 ns\r
289 001b - 32 ns\r
290 010b - 1024 ns\r
291 011b - 32,768 ns\r
292 100b - 1,048,576 ns\r
293 101b - 33,554,432 ns\r
294 110b - Reserved\r
295 111b - Reserved\r
296 BITS[9:0] - Non Snoop Latency Value. The value in these bits will be multiplied with\r
297 the scale in bits 12:10\r
298 **/\r
299 UINT16 NonSnoopLatency;\r
300} PCH_PCIE_DEVICE_LTR_OVERRIDE;\r
301\r
302typedef struct {\r
303 ///\r
304 /// Temp Bus Number range available to be assigned to\r
305 /// each root port and its downstream devices for initialization\r
306 /// of these devices before PCI Bus enumeration\r
307 ///\r
308 UINT8 TempRootPortBusNumMin;\r
309 UINT8 TempRootPortBusNumMax;\r
310 PCH_PCI_EXPRESS_ROOT_PORT_CONFIG RootPort[PCH_PCIE_MAX_ROOT_PORTS];\r
311 BOOLEAN RootPortClockGating;\r
312 UINT8 NumOfDevAspmOverride; /// Number of PCI Express card Aspm setting override\r
313 PCH_PCIE_DEVICE_ASPM_OVERRIDE *DevAspmOverride; /// The Pointer which is point to Pci Express card Aspm setting override\r
314 UINT8 PcieDynamicGating; /// Need PMC enable it first from PMC 0x3_12 MCU 318.\r
315} PCH_PCI_EXPRESS_CONFIG;\r
316\r
317\r
318///\r
319/// ---------------------------- SATA Config -----------------------------\r
320///\r
321typedef enum {\r
322 PchSataSpeedSupportGen1 = 1,\r
323 PchSataSpeedSupportGen2\r
324} PCH_SATA_SPEED_SUPPORT;\r
325\r
326typedef struct {\r
327 UINT8 Enable : 1; /// 0: Disable; 1: Enable\r
328 UINT8 HotPlug : 1; /// 0: Disable; 1: Enable\r
329 UINT8 MechSw : 1; /// 0: Disable; 1: Enable\r
330 UINT8 External : 1; /// 0: Disable; 1: Enable\r
331 UINT8 SpinUp : 1; /// 0: Disable; 1: Enable the COMRESET initialization Sequence to the device\r
332 UINT8 Rsvdbits : 3; /// Reserved fields for future expansion w/o protocol change\r
333} PCH_SATA_PORT_SETTINGS;\r
334\r
335typedef struct {\r
336 PCH_SATA_PORT_SETTINGS PortSettings[PCH_AHCI_MAX_PORTS];\r
337 UINT8 RaidAlternateId : 1; /// 0: Disable; 1: Enable\r
338 UINT8 Raid0 : 1; /// 0: Disable; 1: Enable RAID0\r
339 UINT8 Raid1 : 1; /// 0: Disable; 1: Enable RAID1\r
340 UINT8 Raid10 : 1; /// 0: Disable; 1: Enable RAID10\r
341 UINT8 Raid5 : 1; /// 0: Disable; 1: Enable RAID5\r
342 UINT8 Irrt : 1; /// 0: Disable; 1: Enable Intel Rapid Recovery Technology\r
343 UINT8 OromUiBanner : 1; /// 0: Disable; 1: Enable OROM UI and BANNER\r
344 UINT8 HddUnlock : 1; /// 0: Disable; 1: Indicates that the HDD password unlock in the OS is enabled\r
345\r
346 UINT8 LedLocate : 1; /// 0: Disable; 1: Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS\r
347 UINT8 IrrtOnly : 1; /// 0: Disable; 1: Allow only IRRT drives to span internal and external ports\r
348 UINT8 TestMode : 1; /// 0: Disable; 1: Allow entrance to the PCH SATA test modes\r
349 UINT8 SalpSupport : 1; /// 0: Disable; 1: Enable Aggressive Link Power Management\r
350 UINT8 LegacyMode : 1; /// 0: Native PCI mode; 1: Legacy mode, when SATA controller is operating in IDE mode\r
351 UINT8 SpeedSupport : 4; /// Indicates the maximum speed the SATA controller can support\r
352 /// 1h: 1.5 Gb/s (Gen 1); 2h: 3 Gb/s(Gen 2)\r
353\r
354 UINT8 Rsvdbits : 7; // Reserved fields for future expansion w/o protocol change\r
355} PCH_SATA_CONFIG;\r
356///\r
357/// --------------------------- AZALIA Config ------------------------------\r
358///\r
359typedef struct {\r
360 UINT32 VendorDeviceId;\r
361 UINT16 SubSystemId;\r
362 UINT8 RevisionId; /// 0xFF applies to all steppings\r
363 UINT8 FrontPanelSupport;\r
364 UINT16 NumberOfRearJacks;\r
365 UINT16 NumberOfFrontJacks;\r
366} PCH_AZALIA_VERB_TABLE_HEADER;\r
367\r
368typedef struct {\r
369 PCH_AZALIA_VERB_TABLE_HEADER VerbTableHeader;\r
370 UINT32 *VerbTableData;\r
371} PCH_AZALIA_VERB_TABLE;\r
372\r
373typedef struct {\r
374 UINT8 Pme : 1; /// 0: Disable; 1: Enable\r
375 UINT8 DS : 1; /// 0: Docking is not supported; 1:Docking is supported\r
376 UINT8 DA : 1; /// 0: Docking is not attached; 1:Docking is attached\r
377 UINT8 HdmiCodec : 1; /// 0: Disable; 1: Enable\r
378 UINT8 AzaliaVCi : 1; /// 0: Disable; 1: Enable\r
379 UINT8 Rsvdbits : 3;\r
380 UINT8 AzaliaVerbTableNum; /// Number of verb tables provided by platform\r
381 PCH_AZALIA_VERB_TABLE *AzaliaVerbTable; /// Pointer to the actual verb table(s)\r
382 UINT16 ResetWaitTimer; /// The delay timer after Azalia reset, the value is number of microseconds\r
383} PCH_AZALIA_CONFIG;\r
384\r
385///\r
386/// --------------------------- Smbus Config ------------------------------\r
387///\r
388typedef struct {\r
389 UINT8 NumRsvdSmbusAddresses;\r
390 UINT8 *RsvdSmbusAddressTable;\r
391} PCH_SMBUS_CONFIG;\r
392\r
393///\r
394/// --------------------------- Miscellaneous PM Config ------------------------------\r
395///\r
396typedef struct {\r
397 UINT8 MeWakeSts : 1;\r
398 UINT8 MeHrstColdSts : 1;\r
399 UINT8 MeHrstWarmSts : 1;\r
400 UINT8 MeHostPowerDn : 1;\r
401 UINT8 WolOvrWkSts : 1;\r
402 UINT8 Rsvdbits : 3;\r
403} PCH_POWER_RESET_STATUS;\r
404\r
405typedef struct {\r
406 UINT8 PmeB0S5Dis : 1;\r
407 UINT8 WolEnableOverride : 1;\r
408 UINT8 Rsvdbits : 6;\r
409} PCH_WAKE_CONFIG;\r
410\r
411typedef enum {\r
412 PchSlpS360us,\r
413 PchSlpS31ms,\r
414 PchSlpS350ms,\r
415 PchSlpS32s\r
416} PCH_SLP_S3_MIN_ASSERT;\r
417\r
418typedef enum {\r
419 PchSlpS4PchTime, /// The time defined in EDS Power Sequencing and Reset Signal Timings table\r
420 PchSlpS41s,\r
421 PchSlpS42s,\r
422 PchSlpS43s,\r
423 PchSlpS44s\r
424} PCH_SLP_S4_MIN_ASSERT;\r
425\r
426typedef struct {\r
427 ///\r
428 /// Specify which Power/Reset bits need to be cleared by\r
429 /// the PCH Init Driver.\r
430 /// Usually platform drivers take care of these bits, but if\r
431 /// not, let PCH Init driver clear the bits.\r
432 ///\r
433 PCH_POWER_RESET_STATUS PowerResetStatusClear;\r
434 ///\r
435 /// Specify Wake Policy\r
436 ///\r
437 PCH_WAKE_CONFIG WakeConfig;\r
438 ///\r
439 /// SLP_XX Minimum Assertion Width Policy\r
440 ///\r
441 PCH_SLP_S3_MIN_ASSERT PchSlpS3MinAssert;\r
442 PCH_SLP_S4_MIN_ASSERT PchSlpS4MinAssert;\r
443 UINT8 SlpStrchSusUp : 1; /// Enable/Disable SLP_X Stretching After SUS Well Power Up\r
444 UINT8 SlpLanLowDc : 1;\r
445 UINT8 Rsvdbits : 6;\r
446} PCH_MISC_PM_CONFIG;\r
447\r
448///\r
449/// --------------------------- Subsystem Vendor ID / Subsystem ID Config -----\r
450///\r
451typedef struct {\r
452 UINT16 SubSystemVendorId;\r
453 UINT16 SubSystemId;\r
454} PCH_DEFAULT_SVID_SID;\r
455\r
456///\r
457/// --------------------------- Lock Down Config ------------------------------\r
458///\r
459typedef struct {\r
460 UINT8 GlobalSmi : 1;\r
461 UINT8 BiosInterface : 1;\r
462 UINT8 RtcLock : 1;\r
463 UINT8 BiosLock : 1;\r
464 UINT8 Rsvdbits : 4;\r
465 UINT8 PchBiosLockSwSmiNumber;\r
466} PCH_LOCK_DOWN_CONFIG;\r
467//\r
468// --------------------------- Serial IRQ Config ------------------------------\r
469//\r
470typedef enum {\r
471 PchQuietMode,\r
472 PchContinuousMode\r
473} PCH_SIRQ_MODE;\r
474///\r
475/// Refer to SoC EDS for the details of Start Frame Pulse Width in Continuous and Quiet mode\r
476///\r
477\r
478typedef struct {\r
479 BOOLEAN SirqEnable; /// Determines if enable Serial IRQ\r
480 PCH_SIRQ_MODE SirqMode; /// Serial IRQ Mode Select\r
481} PCH_LPC_SIRQ_CONFIG;\r
482\r
483///\r
484/// --------------------------- Power Optimizer Config ------------------------------\r
485///\r
486typedef struct {\r
487 UINT8 NumOfDevLtrOverride; /// Number of Pci Express card listed in LTR override table\r
488 PCH_PCIE_DEVICE_LTR_OVERRIDE *DevLtrOverride; /// Pointer to Pci Express devices LTR override table\r
489} PCH_PWR_OPT_CONFIG;\r
490\r
491///\r
492/// --------------------- Low Power Input Output Config ------------------------\r
493///\r
494typedef struct {\r
495 UINT8 LpssPciModeEnabled : 1; /// Determines if LPSS PCI Mode enabled\r
496 UINT8 Dma0Enabled : 1; /// Determines if LPSS DMA1 enabled\r
497 UINT8 Dma1Enabled : 1; /// Determines if LPSS DMA2 enabled\r
498 UINT8 I2C0Enabled : 1; /// Determines if LPSS I2C #1 enabled\r
499 UINT8 I2C1Enabled : 1; /// Determines if LPSS I2C #2 enabled\r
500 UINT8 I2C2Enabled : 1; /// Determines if LPSS I2C #3 enabled\r
501 UINT8 I2C3Enabled : 1; /// Determines if LPSS I2C #4 enabled\r
502 UINT8 I2C4Enabled : 1; /// Determines if LPSS I2C #5 enabled\r
503 UINT8 I2C5Enabled : 1; /// Determines if LPSS I2C #6 enabled\r
504 UINT8 I2C6Enabled : 1; /// Determines if LPSS I2C #7 enabled\r
505 UINT8 Pwm0Enabled : 1; /// Determines if LPSS PWM #1 enabled\r
506 UINT8 Pwm1Enabled : 1; /// Determines if LPSS PWM #2 enabled\r
507 UINT8 Hsuart0Enabled : 1; /// Determines if LPSS HSUART #1 enabled\r
508 UINT8 Hsuart1Enabled : 1; /// Determines if LPSS HSUART #2 enabled\r
509 UINT8 SpiEnabled : 1; /// Determines if LPSS SPI enabled\r
510 UINT8 Rsvdbits : 2;\r
511} PCH_LPSS_CONFIG;\r
512\r
513///\r
514/// ----------------------------- SCC Config --------------------------------\r
515///\r
516typedef struct {\r
517 UINT8 eMMCEnabled : 1; /// Determines if SCC eMMC enabled\r
518 UINT8 SdioEnabled : 1; /// Determines if SCC SDIO enabled\r
519 UINT8 SdcardEnabled : 1; /// Determines if SCC SD Card enabled\r
520 UINT8 HsiEnabled : 1; /// Determines if SCC HSI enabled\r
521 UINT8 eMMC45Enabled : 1; /// Determines if SCC eMMC 4.5 enabled\r
522 UINT8 eMMC45DDR50Enabled : 1; /// Determines if DDR50 enabled for eMMC 4.5\r
523 UINT8 eMMC45HS200Enabled : 1; /// Determines if HS200nabled for eMMC 4.5\r
524 UINT8 Rsvdbits : 1;\r
525 UINT8 SdCardSDR25Enabled : 1; /// Determines if SDR25 for SD Card\r
526 UINT8 SdCardDDR50Enabled : 1; /// Determines if DDR50 for SD Card\r
527 UINT8 Rsvdbits1 : 6;\r
528 UINT8 eMMC45RetuneTimerValue; /// Determines retune timer value.\r
529} PCH_SCC_CONFIG;\r
530\r
531///\r
532/// ------------ General PCH Platform Policy protocol definition ------------\r
533///\r
534struct _DXE_PCH_PLATFORM_POLICY_PROTOCOL {\r
535 UINT8 Revision;\r
536 UINT8 BusNumber; /// PCI Bus Number of the PCH device\r
537 PCH_DEVICE_ENABLING *DeviceEnabling;\r
538 PCH_USB_CONFIG *UsbConfig;\r
539 PCH_PCI_EXPRESS_CONFIG *PciExpressConfig;\r
540\r
541 PCH_SATA_CONFIG *SataConfig;\r
542 PCH_AZALIA_CONFIG *AzaliaConfig;\r
543 PCH_SMBUS_CONFIG *SmbusConfig;\r
544 PCH_MISC_PM_CONFIG *MiscPmConfig;\r
545 PCH_DEFAULT_SVID_SID *DefaultSvidSid;\r
546 PCH_LOCK_DOWN_CONFIG *LockDownConfig;\r
547 PCH_LPC_SIRQ_CONFIG *SerialIrqConfig;\r
548 PCH_PWR_OPT_CONFIG *PwrOptConfig;\r
549 PCH_LPSS_CONFIG *LpssConfig;\r
550 PCH_SCC_CONFIG *SccConfig;\r
551 UINT8 IdleReserve;\r
552 UINT8 EhciPllCfgEnable;\r
553 UINT8 AcpiHWRed; //Hardware Reduced Mode\r
554};\r
555\r
556#endif\r
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