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1/**\r
2**/\r
3/**\r
4\r
5Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved\r
6\r
7 This program and the accompanying materials are licensed and made available under\r
8 the terms and conditions of the BSD License that accompanies this distribution.\r
9 The full text of the license may be found at\r
10 http://opensource.org/licenses/bsd-license.php.\r
11\r
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14\r
15\r
16\r
17 @file\r
18 PchS3Support.h\r
19\r
20 @brief\r
21 This file defines the PCH S3 support Protocol.\r
22\r
23**/\r
24#ifndef _PCH_S3_SUPPORT_PROTOCOL_H_\r
25#define _PCH_S3_SUPPORT_PROTOCOL_H_\r
26\r
27#ifndef ECP_FLAG\r
28#include <Pi/PiS3BootScript.h>\r
29#endif\r
30\r
31#define EFI_PCH_S3_SUPPORT_PROTOCOL_GUID \\r
32 { \\r
33 0xe287d20b, 0xd897, 0x4e1e, 0xa5, 0xd9, 0x97, 0x77, 0x63, 0x93, 0x6a, 0x4 \\r
34 }\r
35\r
36#include <Protocol/PchPlatformPolicy.h>\r
37\r
38///\r
39/// Extern the GUID for protocol users.\r
40///\r
41extern EFI_GUID gEfiPchS3SupportProtocolGuid;\r
42\r
43///\r
44/// Forward reference for ANSI C compatibility\r
45///\r
46typedef struct _EFI_PCH_S3_SUPPORT_PROTOCOL EFI_PCH_S3_SUPPORT_PROTOCOL;\r
47\r
48typedef enum {\r
49 PchS3ItemTypeSendCodecCommand,\r
50 PchS3ItemTypePollStatus,\r
51 PchS3ItemTypeInitPcieRootPortDownstream,\r
52 PchS3ItemTypePcieSetPm,\r
53 PchS3ItemTypePmTimerStall,\r
54 PchS3ItemTypeMax\r
55} EFI_PCH_S3_DISPATCH_ITEM_TYPE;\r
56\r
57///\r
58/// It's better not to use pointer here because the size of pointer in DXE is 8, but it's 4 in PEI\r
59/// plug 4 to ParameterSize in PEIM if you really need it\r
60///\r
61typedef struct {\r
62 UINT32 HdaBar;\r
63 UINT32 CodecCmdData;\r
64} EFI_PCH_S3_PARAMETER_SEND_CODEC_COMMAND;\r
65\r
66typedef struct {\r
67 UINT64 MmioAddress;\r
68 EFI_BOOT_SCRIPT_WIDTH Width;\r
69 UINT64 Mask;\r
70 UINT64 Value;\r
71 UINT32 Timeout; // us\r
72} EFI_PCH_S3_PARAMETER_POLL_STATUS;\r
73\r
74typedef struct {\r
75 UINT8 RootPortBus;\r
76 UINT8 RootPortDevice;\r
77 UINT8 RootPortFunc;\r
78 UINT8 TempBusNumberMin;\r
79 UINT8 TempBusNumberMax;\r
80} EFI_PCH_S3_PARAMETER_INIT_PCIE_ROOT_PORT_DOWNSTREAM;\r
81\r
82typedef struct {\r
83 UINT8 RootPortBus;\r
84 UINT8 RootPortDevice;\r
85 UINT8 RootPortFunc;\r
86 PCH_PCI_EXPRESS_ASPM_CONTROL RootPortAspm;\r
87 UINT8 NumOfDevAspmOverride;\r
88 UINT32 DevAspmOverrideAddr;\r
89 UINT8 TempBusNumberMin;\r
90 UINT8 TempBusNumberMax;\r
91 UINT8 NumOfDevLtrOverride;\r
92 UINT32 DevLtrOverrideAddr;\r
93} EFI_PCH_S3_PARAMETER_PCIE_SET_PM;\r
94\r
95typedef struct {\r
96 UINT32 DelayTime; // us\r
97} EFI_PCH_S3_PARAMETER_PM_TIMER_STALL;\r
98\r
99typedef struct {\r
100 EFI_PCH_S3_DISPATCH_ITEM_TYPE Type;\r
101 VOID *Parameter;\r
102} EFI_PCH_S3_DISPATCH_ITEM;\r
103\r
104///\r
105/// Member functions\r
106///\r
107typedef\r
108EFI_STATUS\r
109(EFIAPI *EFI_PCH_S3_SUPPORT_SET_S3_DISPATCH_ITEM) (\r
110 IN EFI_PCH_S3_SUPPORT_PROTOCOL * This,\r
111 IN EFI_PCH_S3_DISPATCH_ITEM * DispatchItem,\r
112 OUT EFI_PHYSICAL_ADDRESS * S3DispatchEntryPoint\r
113 );\r
114\r
115/**\r
116\r
117 @brief\r
118 Set an item to be dispatched at S3 resume time. At the same time, the entry point\r
119 of the PCH S3 support image is returned to be used in subsequent boot script save\r
120 call\r
121\r
122 @param[in] This Pointer to the protocol instance.\r
123 @param[in] DispatchItem The item to be dispatched.\r
124 @param[in] S3DispatchEntryPoint The entry point of the PCH S3 support image.\r
125\r
126 @retval EFI_STATUS Successfully completed.\r
127 @retval EFI_OUT_OF_RESOURCES Out of resources.\r
128\r
129**/\r
130\r
131///\r
132/// Protocol definition\r
133///\r
134struct _EFI_PCH_S3_SUPPORT_PROTOCOL {\r
135 EFI_PCH_S3_SUPPORT_SET_S3_DISPATCH_ITEM SetDispatchItem;\r
136};\r
137\r
138#endif\r