[mirror_edk2.git] / Vlv2DeviceRefCodePkg / ValleyView2Soc / SouthCluster / Include / Protocol / Spi.h

/**\r
**/\r
/**\r
\r
Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved\r
\r
  This program and the accompanying materials are licensed and made available under\r
  the terms and conditions of the BSD License that accompanies this distribution.\r
  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php.\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
\r
\r
  @file\r
  Spi.h\r
\r
  @brief\r
  This file defines the EFI SPI Protocol which implements the\r
  Intel(R) ICH SPI Host Controller Compatibility Interface.\r
\r
**/\r
#ifndef _EFI_SPI_H_\r
#define _EFI_SPI_H_\r
\r
\r
//\r
#define EFI_SPI_PROTOCOL_GUID \\r
  { \\r
    0x1156efc6, 0xea32, 0x4396, 0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13 \\r
  }\r
#define EFI_SMM_SPI_PROTOCOL_GUID \\r
  { \\r
    0xD9072C35, 0xEB8F, 0x43ad, 0xA2, 0x20, 0x34, 0xD4, 0x0E, 0x2A, 0x82, 0x85 \\r
  }\r
extern EFI_GUID                   gEfiSpiProtocolGuid;\r
extern EFI_GUID                   gEfiSmmSpiProtocolGuid;\r
\r
///\r
/// Forward reference for ANSI C compatibility\r
///\r
typedef struct _EFI_SPI_PROTOCOL  EFI_SPI_PROTOCOL;\r
\r
///\r
/// SPI protocol data structures and definitions\r
///\r
///\r
/// Number of Prefix Opcodes allowed on the SPI interface\r
///\r
#define SPI_NUM_PREFIX_OPCODE 2\r
\r
///\r
/// Number of Opcodes in the Opcode Menu\r
///\r
#define SPI_NUM_OPCODE  8\r
\r
///\r
/// Opcode Type\r
///    EnumSpiOpcodeCommand: Command without address\r
///    EnumSpiOpcodeRead: Read with address\r
///    EnumSpiOpcodeWrite: Write with address\r
///\r
typedef enum {\r
  EnumSpiOpcodeReadNoAddr,\r
  EnumSpiOpcodeWriteNoAddr,\r
  EnumSpiOpcodeRead,\r
  EnumSpiOpcodeWrite,\r
  EnumSpiOpcodeMax\r
} SPI_OPCODE_TYPE;\r
\r
typedef enum {\r
  EnumSpiCycle20MHz,\r
  EnumSpiCycle33MHz,\r
  EnumSpiCycle66MHz,  /// Not supported by VLV\r
  EnumSpiCycle50MHz,\r
  EnumSpiCycleMax\r
} SPI_CYCLE_FREQUENCY;\r
\r
typedef enum {\r
  EnumSpiRegionAll,\r
  EnumSpiRegionBios,\r
  EnumSpiRegionSeC,\r
  EnumSpiRegionDescriptor,\r
  EnumSpiRegionPlatformData,\r
  EnumSpiRegionMax\r
} SPI_REGION_TYPE;\r
\r
///\r
/// Hardware Sequencing required operations (as listed in Valleyview EDS "Hardware\r
/// Sequencing Commands and Opcode Requirements"\r
///\r
typedef enum {\r
  EnumSpiOperationWriteStatus,\r
  EnumSpiOperationProgramData_1_Byte,\r
  EnumSpiOperationProgramData_64_Byte,\r
  EnumSpiOperationReadData,\r
  EnumSpiOperationWriteDisable,\r
  EnumSpiOperationReadStatus,\r
  EnumSpiOperationWriteEnable,\r
  EnumSpiOperationFastRead,\r
  EnumSpiOperationEnableWriteStatus,\r
  EnumSpiOperationErase_256_Byte,\r
  EnumSpiOperationErase_4K_Byte,\r
  EnumSpiOperationErase_8K_Byte,\r
  EnumSpiOperationErase_64K_Byte,\r
  EnumSpiOperationFullChipErase,\r
  EnumSpiOperationJedecId,\r
  EnumSpiOperationDualOutputFastRead,\r
  EnumSpiOperationDiscoveryParameters,\r
  EnumSpiOperationOther,\r
  EnumSpiOperationMax\r
} SPI_OPERATION;\r
\r
///\r
/// SPI Command Configuration\r
///   Frequency       The expected frequency to be used (value to be programmed to the SSFC\r
///                   Register)\r
///   Operation       Which Hardware Sequencing required operation this opcode respoinds to.\r
///                   The required operations are listed in EDS Table 5-55: "Hardware\r
///                   Sequencing Commands and Opcode Requirements"\r
///                   If the opcode does not corresponds to any operation listed, use\r
///                   EnumSpiOperationOther, and provides TYPE and Code for it in\r
///                   SpecialOpcodeEntry.\r
///\r
typedef struct _SPI_OPCODE_MENU_ENTRY {\r
  SPI_OPCODE_TYPE     Type;\r
  UINT8               Code;\r
  SPI_CYCLE_FREQUENCY Frequency;\r
  SPI_OPERATION       Operation;\r
} SPI_OPCODE_MENU_ENTRY;\r
\r
//\r
// Initialization data table loaded to the SPI host controller\r
//    VendorId        Vendor ID of the SPI device\r
//    DeviceId0       Device ID0 of the SPI device\r
//    DeviceId1       Device ID1 of the SPI device\r
//    PrefixOpcode    Prefix opcodes which are loaded into the SPI host controller\r
//    OpcodeMenu      Opcodes which are loaded into the SPI host controller Opcode Menu\r
//    BiosStartOffset The offset of the start of the BIOS image relative to the flash device.\r
//                    Please note this is a Flash Linear Address, NOT a memory space address.\r
//                    This value is platform specific and depends on the system flash map.\r
//                    This value is only used on non Descriptor mode.\r
//    BiosSize        The the BIOS Image size in flash. This value is platform specific\r
//                    and depends on the system flash map. Please note BIOS Image size may\r
//                    be smaller than BIOS Region size (in Descriptor Mode) or the flash size\r
//                    (in Non Descriptor Mode), and in this case, BIOS Image is supposed to be\r
//                    placed at the top end of the BIOS Region (in Descriptor Mode) or the flash\r
//                    (in Non Descriptor Mode)\r
//\r
typedef struct _SPI_INIT_TABLE {\r
  UINT8                 VendorId;\r
  UINT8                 DeviceId0;\r
  UINT8                 DeviceId1;\r
  UINT8                 PrefixOpcode[SPI_NUM_PREFIX_OPCODE];\r
  SPI_OPCODE_MENU_ENTRY OpcodeMenu[SPI_NUM_OPCODE];\r
  UINTN                 BiosStartOffset;\r
  UINTN                 BiosSize;\r
} SPI_INIT_TABLE;\r
\r
//\r
// Protocol member functions\r
//\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_SPI_INIT) (\r
  IN EFI_SPI_PROTOCOL     * This,\r
  IN SPI_INIT_TABLE       * InitTable\r
  );\r
\r
/**\r
\r
  @brief\r
  Initializes the host controller to execute SPI commands.\r
\r
  @param[in] This                 Pointer to the EFI_SPI_PROTOCOL instance.\r
  @param[in] InitData             Pointer to caller-allocated buffer containing the SPI\r
                                  interface initialization table.\r
\r
  @retval EFI_SUCCESS             Opcode initialization on the SPI host controller completed.\r
  @retval EFI_ACCESS_DENIED       The SPI configuration interface is locked.\r
  @retval EFI_OUT_OF_RESOURCES    Not enough resource available to initialize the device.\r
  @retval EFI_DEVICE_ERROR        Device error, operation failed.\r
\r
**/\r
\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_SPI_LOCK) (\r
  IN EFI_SPI_PROTOCOL     * This\r
  );\r
/**\r
\r
  @brief\r
  Initializes the host controller to execute SPI commands.\r
\r
  @param[in] This                 Pointer to the EFI_SPI_PROTOCOL instance.\r
  @param[in] InitData             Pointer to caller-allocated buffer containing the SPI\r
                                  interface initialization table.\r
\r
  @retval EFI_SUCCESS             Opcode initialization on the SPI host controller completed.\r
  @retval EFI_ACCESS_DENIED       The SPI configuration interface is locked.\r
  @retval EFI_OUT_OF_RESOURCES    Not enough resource available to initialize the device.\r
  @retval EFI_DEVICE_ERROR        Device error, operation failed.\r
\r
**/\r
\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_SPI_EXECUTE) (\r
  IN     EFI_SPI_PROTOCOL   * This,\r
  IN     UINT8              OpcodeIndex,\r
  IN     UINT8              PrefixOpcodeIndex,\r
  IN     BOOLEAN            DataCycle,\r
  IN     BOOLEAN            Atomic,\r
  IN     BOOLEAN            ShiftOut,\r
  IN     UINTN              Address,\r
  IN     UINT32             DataByteCount,\r
  IN OUT UINT8              *Buffer,\r
  IN     SPI_REGION_TYPE    SpiRegionType\r
  );\r
/**\r
\r
  @brief\r
  Execute SPI commands from the host controller.\r
\r
  @param[in] This                 Pointer to the EFI_SPI_PROTOCOL instance.\r
  @param[in] OpcodeIndex          Index of the command in the OpCode Menu.\r
  @param[in] PrefixOpcodeIndex    Index of the first command to run when in an atomic cycle sequence.\r
  @param[in] DataCycle            TRUE if the SPI cycle contains data\r
  @param[in] Atomic               TRUE if the SPI cycle is atomic and interleave cycles are not allowed.\r
  @param[in] ShiftOut             If DataByteCount is not zero, TRUE to shift data out and FALSE to shift data in.\r
  @param[in] Address              In Descriptor Mode, for Descriptor Region, GbE Region, ME Region and Platform\r
                                  Region, this value specifies the offset from the Region Base; for BIOS Region,\r
                                  this value specifies the offset from the start of the BIOS Image. In Non\r
                                  Descriptor Mode, this value specifies the offset from the start of the BIOS Image.\r
                                  Please note BIOS Image size may be smaller than BIOS Region size (in Descriptor\r
                                  Mode) or the flash size (in Non Descriptor Mode), and in this case, BIOS Image is\r
                                  supposed to be placed at the top end of the BIOS Region (in Descriptor Mode) or\r
                                  the flash (in Non Descriptor Mode)\r
  @param[in] DataByteCount        Number of bytes in the data portion of the SPI cycle.\r
  @param[in] Buffer               Pointer to caller-allocated buffer containing the dada received or sent during the SPI cycle.\r
  @param[in] SpiRegionType        SPI Region type. Values EnumSpiRegionBios, EnumSpiRegionGbE, EnumSpiRegionMe,\r
                                  EnumSpiRegionDescriptor, and EnumSpiRegionPlatformData are only applicable in\r
                                  Descriptor mode. Value EnumSpiRegionAll is applicable to both Descriptor Mode\r
                                  and Non Descriptor Mode, which indicates "SpiRegionOffset" is actually relative\r
                                  to base of the 1st flash device (i.e., it is a Flash Linear Address).\r
\r
  @retval EFI_SUCCESS             Command succeed.\r
  @retval EFI_INVALID_PARAMETER   The parameters specified are not valid.\r
  @exception EFI_UNSUPPORTED      Command not supported.\r
  @retval EFI_DEVICE_ERROR        Device error, command aborts abnormally.\r
\r
**/\r
\r
///\r
/// Protocol definition\r
///\r
struct _EFI_SPI_PROTOCOL {\r
  EFI_SPI_INIT    Init;\r
  EFI_SPI_LOCK    Lock;\r
  EFI_SPI_EXECUTE Execute;\r
};\r
\r
#endif\r
Commit	Line	Data
3cbfba02 DW	1	/**\r
	2	**/\r
	3	/**\r
	4	\r
	5	Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved\r
	6	\r
	7	This program and the accompanying materials are licensed and made available under\r
	8	the terms and conditions of the BSD License that accompanies this distribution.\r
	9	The full text of the license may be found at\r
	10	http://opensource.org/licenses/bsd-license.php.\r
	11	\r
	12	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	13	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	14	\r
	15	\r
	16	\r
	17	@file\r
	18	Spi.h\r
	19	\r
	20	@brief\r
	21	This file defines the EFI SPI Protocol which implements the\r
	22	Intel(R) ICH SPI Host Controller Compatibility Interface.\r
	23	\r
	24	**/\r
	25	#ifndef _EFI_SPI_H_\r
	26	#define _EFI_SPI_H_\r
	27	\r
	28	\r
	29	//\r
	30	#define EFI_SPI_PROTOCOL_GUID \\r
	31	{ \\r
	32	0x1156efc6, 0xea32, 0x4396, 0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13 \\r
	33	}\r
	34	#define EFI_SMM_SPI_PROTOCOL_GUID \\r
	35	{ \\r
	36	0xD9072C35, 0xEB8F, 0x43ad, 0xA2, 0x20, 0x34, 0xD4, 0x0E, 0x2A, 0x82, 0x85 \\r
	37	}\r
	38	extern EFI_GUID gEfiSpiProtocolGuid;\r
	39	extern EFI_GUID gEfiSmmSpiProtocolGuid;\r
	40	\r
	41	///\r
	42	/// Forward reference for ANSI C compatibility\r
	43	///\r
	44	typedef struct _EFI_SPI_PROTOCOL EFI_SPI_PROTOCOL;\r
	45	\r
	46	///\r
	47	/// SPI protocol data structures and definitions\r
	48	///\r
	49	///\r
	50	/// Number of Prefix Opcodes allowed on the SPI interface\r
	51	///\r
	52	#define SPI_NUM_PREFIX_OPCODE 2\r
	53	\r
	54	///\r
	55	/// Number of Opcodes in the Opcode Menu\r
	56	///\r
	57	#define SPI_NUM_OPCODE 8\r
	58	\r
	59	///\r
	60	/// Opcode Type\r
	61	/// EnumSpiOpcodeCommand: Command without address\r
	62	/// EnumSpiOpcodeRead: Read with address\r
	63	/// EnumSpiOpcodeWrite: Write with address\r
	64	///\r
65	typedef enum {\r
66	EnumSpiOpcodeReadNoAddr,\r
67	EnumSpiOpcodeWriteNoAddr,\r
68	EnumSpiOpcodeRead,\r
69	EnumSpiOpcodeWrite,\r
70	EnumSpiOpcodeMax\r
71	} SPI_OPCODE_TYPE;\r
72	\r
73	typedef enum {\r
74	EnumSpiCycle20MHz,\r
75	EnumSpiCycle33MHz,\r
76	EnumSpiCycle66MHz, /// Not supported by VLV\r
77	EnumSpiCycle50MHz,\r
78	EnumSpiCycleMax\r
79	} SPI_CYCLE_FREQUENCY;\r
80	\r
81	typedef enum {\r
82	EnumSpiRegionAll,\r
83	EnumSpiRegionBios,\r
84	EnumSpiRegionSeC,\r
85	EnumSpiRegionDescriptor,\r
86	EnumSpiRegionPlatformData,\r
87	EnumSpiRegionMax\r
88	} SPI_REGION_TYPE;\r
89	\r
90	///\r
91	/// Hardware Sequencing required operations (as listed in Valleyview EDS "Hardware\r
92	/// Sequencing Commands and Opcode Requirements"\r
93	///\r
94	typedef enum {\r
95	EnumSpiOperationWriteStatus,\r
96	EnumSpiOperationProgramData_1_Byte,\r
97	EnumSpiOperationProgramData_64_Byte,\r
98	EnumSpiOperationReadData,\r
99	EnumSpiOperationWriteDisable,\r
100	EnumSpiOperationReadStatus,\r
101	EnumSpiOperationWriteEnable,\r
102	EnumSpiOperationFastRead,\r
103	EnumSpiOperationEnableWriteStatus,\r
104	EnumSpiOperationErase_256_Byte,\r
105	EnumSpiOperationErase_4K_Byte,\r
106	EnumSpiOperationErase_8K_Byte,\r
107	EnumSpiOperationErase_64K_Byte,\r
108	EnumSpiOperationFullChipErase,\r
109	EnumSpiOperationJedecId,\r
110	EnumSpiOperationDualOutputFastRead,\r
111	EnumSpiOperationDiscoveryParameters,\r
112	EnumSpiOperationOther,\r
113	EnumSpiOperationMax\r
114	} SPI_OPERATION;\r
115	\r
116	///\r
117	/// SPI Command Configuration\r
118	/// Frequency The expected frequency to be used (value to be programmed to the SSFC\r
119	/// Register)\r
120	/// Operation Which Hardware Sequencing required operation this opcode respoinds to.\r
121	/// The required operations are listed in EDS Table 5-55: "Hardware\r
122	/// Sequencing Commands and Opcode Requirements"\r
123	/// If the opcode does not corresponds to any operation listed, use\r
124	/// EnumSpiOperationOther, and provides TYPE and Code for it in\r
125	/// SpecialOpcodeEntry.\r
126	///\r
127	typedef struct _SPI_OPCODE_MENU_ENTRY {\r
128	SPI_OPCODE_TYPE Type;\r
129	UINT8 Code;\r
130	SPI_CYCLE_FREQUENCY Frequency;\r
131	SPI_OPERATION Operation;\r
132	} SPI_OPCODE_MENU_ENTRY;\r
133	\r
134	//\r
135	// Initialization data table loaded to the SPI host controller\r
136	// VendorId Vendor ID of the SPI device\r
137	// DeviceId0 Device ID0 of the SPI device\r
138	// DeviceId1 Device ID1 of the SPI device\r
139	// PrefixOpcode Prefix opcodes which are loaded into the SPI host controller\r
140	// OpcodeMenu Opcodes which are loaded into the SPI host controller Opcode Menu\r
141	// BiosStartOffset The offset of the start of the BIOS image relative to the flash device.\r
142	// Please note this is a Flash Linear Address, NOT a memory space address.\r
143	// This value is platform specific and depends on the system flash map.\r
144	// This value is only used on non Descriptor mode.\r
145	// BiosSize The the BIOS Image size in flash. This value is platform specific\r
146	// and depends on the system flash map. Please note BIOS Image size may\r
147	// be smaller than BIOS Region size (in Descriptor Mode) or the flash size\r
148	// (in Non Descriptor Mode), and in this case, BIOS Image is supposed to be\r
149	// placed at the top end of the BIOS Region (in Descriptor Mode) or the flash\r
150	// (in Non Descriptor Mode)\r
151	//\r
152	typedef struct _SPI_INIT_TABLE {\r
153	UINT8 VendorId;\r
154	UINT8 DeviceId0;\r
155	UINT8 DeviceId1;\r
156	UINT8 PrefixOpcode[SPI_NUM_PREFIX_OPCODE];\r
157	SPI_OPCODE_MENU_ENTRY OpcodeMenu[SPI_NUM_OPCODE];\r
158	UINTN BiosStartOffset;\r
159	UINTN BiosSize;\r
160	} SPI_INIT_TABLE;\r
161	\r
162	//\r
163	// Protocol member functions\r
164	//\r
165	typedef\r
166	EFI_STATUS\r
167	(EFIAPI *EFI_SPI_INIT) (\r
168	IN EFI_SPI_PROTOCOL * This,\r
169	IN SPI_INIT_TABLE * InitTable\r
170	);\r
171	\r
172	/**\r
173	\r
174	@brief\r
175	Initializes the host controller to execute SPI commands.\r
176	\r
177	@param[in] This Pointer to the EFI_SPI_PROTOCOL instance.\r
178	@param[in] InitData Pointer to caller-allocated buffer containing the SPI\r
179	interface initialization table.\r
180	\r
181	@retval EFI_SUCCESS Opcode initialization on the SPI host controller completed.\r
182	@retval EFI_ACCESS_DENIED The SPI configuration interface is locked.\r
183	@retval EFI_OUT_OF_RESOURCES Not enough resource available to initialize the device.\r
184	@retval EFI_DEVICE_ERROR Device error, operation failed.\r
185	\r
186	**/\r
187	\r
188	typedef\r
189	EFI_STATUS\r
190	(EFIAPI *EFI_SPI_LOCK) (\r
191	IN EFI_SPI_PROTOCOL * This\r
192	);\r
193	/**\r
194	\r
195	@brief\r
196	Initializes the host controller to execute SPI commands.\r
197	\r
198	@param[in] This Pointer to the EFI_SPI_PROTOCOL instance.\r
199	@param[in] InitData Pointer to caller-allocated buffer containing the SPI\r
200	interface initialization table.\r
201	\r
202	@retval EFI_SUCCESS Opcode initialization on the SPI host controller completed.\r
203	@retval EFI_ACCESS_DENIED The SPI configuration interface is locked.\r
204	@retval EFI_OUT_OF_RESOURCES Not enough resource available to initialize the device.\r
205	@retval EFI_DEVICE_ERROR Device error, operation failed.\r
206	\r
207	**/\r
208	\r
209	typedef\r
210	EFI_STATUS\r
211	(EFIAPI *EFI_SPI_EXECUTE) (\r
212	IN EFI_SPI_PROTOCOL * This,\r
213	IN UINT8 OpcodeIndex,\r
214	IN UINT8 PrefixOpcodeIndex,\r
215	IN BOOLEAN DataCycle,\r
216	IN BOOLEAN Atomic,\r
217	IN BOOLEAN ShiftOut,\r
218	IN UINTN Address,\r
219	IN UINT32 DataByteCount,\r
220	IN OUT UINT8 *Buffer,\r
221	IN SPI_REGION_TYPE SpiRegionType\r
222	);\r
223	/**\r
224	\r
225	@brief\r
226	Execute SPI commands from the host controller.\r
227	\r
228	@param[in] This Pointer to the EFI_SPI_PROTOCOL instance.\r
229	@param[in] OpcodeIndex Index of the command in the OpCode Menu.\r
230	@param[in] PrefixOpcodeIndex Index of the first command to run when in an atomic cycle sequence.\r
231	@param[in] DataCycle TRUE if the SPI cycle contains data\r
232	@param[in] Atomic TRUE if the SPI cycle is atomic and interleave cycles are not allowed.\r
233	@param[in] ShiftOut If DataByteCount is not zero, TRUE to shift data out and FALSE to shift data in.\r
234	@param[in] Address In Descriptor Mode, for Descriptor Region, GbE Region, ME Region and Platform\r
235	Region, this value specifies the offset from the Region Base; for BIOS Region,\r
236	this value specifies the offset from the start of the BIOS Image. In Non\r
237	Descriptor Mode, this value specifies the offset from the start of the BIOS Image.\r
238	Please note BIOS Image size may be smaller than BIOS Region size (in Descriptor\r
239	Mode) or the flash size (in Non Descriptor Mode), and in this case, BIOS Image is\r
240	supposed to be placed at the top end of the BIOS Region (in Descriptor Mode) or\r
241	the flash (in Non Descriptor Mode)\r
242	@param[in] DataByteCount Number of bytes in the data portion of the SPI cycle.\r
243	@param[in] Buffer Pointer to caller-allocated buffer containing the dada received or sent during the SPI cycle.\r
244	@param[in] SpiRegionType SPI Region type. Values EnumSpiRegionBios, EnumSpiRegionGbE, EnumSpiRegionMe,\r
245	EnumSpiRegionDescriptor, and EnumSpiRegionPlatformData are only applicable in\r
246	Descriptor mode. Value EnumSpiRegionAll is applicable to both Descriptor Mode\r
247	and Non Descriptor Mode, which indicates "SpiRegionOffset" is actually relative\r
248	to base of the 1st flash device (i.e., it is a Flash Linear Address).\r
249	\r
250	@retval EFI_SUCCESS Command succeed.\r
251	@retval EFI_INVALID_PARAMETER The parameters specified are not valid.\r
252	@exception EFI_UNSUPPORTED Command not supported.\r
253	@retval EFI_DEVICE_ERROR Device error, command aborts abnormally.\r
254	\r
255	**/\r
256	\r
257	///\r
258	/// Protocol definition\r
259	///\r
260	struct _EFI_SPI_PROTOCOL {\r
261	EFI_SPI_INIT Init;\r
262	EFI_SPI_LOCK Lock;\r
263	EFI_SPI_EXECUTE Execute;\r
264	};\r
265	\r
266	#endif\r