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75ce133c JY |
1 | /** @file\r |
2 | Platform Flash Access library.\r | |
3 | \r | |
27f44846 | 4 | Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r |
75ce133c JY |
5 | This program and the accompanying materials\r |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
27f44846 | 14 | #include <Uefi.h>\r |
75ce133c JY |
15 | \r |
16 | #include <PiDxe.h>\r | |
17 | \r | |
18 | #include <Library/BaseLib.h>\r | |
19 | #include <Library/BaseMemoryLib.h>\r | |
20 | #include <Library/DebugLib.h>\r | |
21 | #include <Library/PcdLib.h>\r | |
22 | #include <Library/PlatformFlashAccessLib.h>\r | |
27f44846 | 23 | //#include <Library/FlashDeviceLib.h>\r |
75ce133c | 24 | #include <Library/MemoryAllocationLib.h>\r |
27f44846 KM |
25 | #include <Protocol/Spi.h>\r |
26 | #include <Library/CacheMaintenanceLib.h>\r | |
27 | #include "PchAccess.h"\r | |
28 | #include <Library/IoLib.h>\r | |
29 | #include <Library/UefiLib.h>\r | |
30 | #include <Library/UefiBootServicesTableLib.h>\r | |
31 | #include <Library/PrintLib.h>\r | |
75ce133c | 32 | \r |
27f44846 KM |
33 | //#define SECTOR_SIZE_64KB 0x10000 // Common 64kBytes sector size\r |
34 | //#define ALINGED_SIZE SECTOR_SIZE_64KB\r | |
35 | \r | |
36 | #define BLOCK_SIZE 0x1000\r | |
37 | #define ALINGED_SIZE BLOCK_SIZE\r | |
38 | \r | |
39 | #define R_PCH_LPC_BIOS_CNTL 0xDC\r | |
40 | #define B_PCH_LPC_BIOS_CNTL_SMM_BWP 0x20 ///< SMM BIOS write protect disable\r | |
41 | \r | |
42 | //\r | |
43 | // Prefix Opcode Index on the host SPI controller\r | |
44 | //\r | |
45 | typedef enum {\r | |
46 | SPI_WREN, // Prefix Opcode 0: Write Enable\r | |
47 | SPI_EWSR, // Prefix Opcode 1: Enable Write Status Register\r | |
48 | } PREFIX_OPCODE_INDEX;\r | |
49 | //\r | |
50 | // Opcode Menu Index on the host SPI controller\r | |
51 | //\r | |
52 | typedef enum {\r | |
53 | SPI_READ_ID, // Opcode 0: READ ID, Read cycle with address\r | |
54 | SPI_READ, // Opcode 1: READ, Read cycle with address\r | |
55 | SPI_RDSR, // Opcode 2: Read Status Register, No address\r | |
56 | SPI_WRDI_SFDP, // Opcode 3: Write Disable or Discovery Parameters, No address\r | |
57 | SPI_SERASE, // Opcode 4: Sector Erase (4KB), Write cycle with address\r | |
58 | SPI_BERASE, // Opcode 5: Block Erase (32KB), Write cycle with address\r | |
59 | SPI_PROG, // Opcode 6: Byte Program, Write cycle with address\r | |
60 | SPI_WRSR, // Opcode 7: Write Status Register, No address\r | |
61 | } SPI_OPCODE_INDEX;\r | |
75ce133c JY |
62 | \r |
63 | STATIC EFI_PHYSICAL_ADDRESS mInternalFdAddress;\r | |
64 | \r | |
27f44846 KM |
65 | EFI_SPI_PROTOCOL *mSpiProtocol;\r |
66 | \r | |
67 | /**\r | |
68 | Read NumBytes bytes of data from the address specified by\r | |
69 | PAddress into Buffer.\r | |
70 | \r | |
71 | @param[in] Address The starting physical address of the read.\r | |
72 | @param[in,out] NumBytes On input, the number of bytes to read. On output, the number\r | |
73 | of bytes actually read.\r | |
74 | @param[out] Buffer The destination data buffer for the read.\r | |
75 | \r | |
76 | @retval EFI_SUCCESS Opertion is successful.\r | |
77 | @retval EFI_DEVICE_ERROR If there is any device errors.\r | |
78 | \r | |
79 | **/\r | |
80 | EFI_STATUS\r | |
81 | EFIAPI\r | |
82 | SpiFlashRead (\r | |
83 | IN UINTN Address,\r | |
84 | IN OUT UINT32 *NumBytes,\r | |
85 | OUT UINT8 *Buffer\r | |
86 | )\r | |
87 | {\r | |
88 | EFI_STATUS Status = EFI_SUCCESS;\r | |
89 | UINTN Offset = 0;\r | |
90 | \r | |
91 | ASSERT ((NumBytes != NULL) && (Buffer != NULL));\r | |
92 | \r | |
93 | \r | |
94 | //if (Address >= (UINTN)PcdGet32 (PcdGbeRomBase) && Address < (UINTN)PcdGet32 (PcdPDRRomBase)) {\r | |
95 | Offset = Address - (UINTN)PcdGet32 (PcdFlashChipBase);\r | |
96 | \r | |
97 | Status = mSpiProtocol->Execute (\r | |
98 | mSpiProtocol,\r | |
99 | 1, //SPI_READ,\r | |
100 | 0, //SPI_WREN,\r | |
101 | TRUE,\r | |
102 | TRUE,\r | |
103 | FALSE,\r | |
104 | Offset,\r | |
105 | BLOCK_SIZE,\r | |
106 | Buffer,\r | |
107 | EnumSpiRegionAll\r | |
108 | );\r | |
109 | return Status;\r | |
110 | }\r | |
111 | \r | |
112 | /**\r | |
113 | Write NumBytes bytes of data from Buffer to the address specified by\r | |
114 | PAddresss.\r | |
115 | \r | |
116 | @param[in] Address The starting physical address of the write.\r | |
117 | @param[in,out] NumBytes On input, the number of bytes to write. On output,\r | |
118 | the actual number of bytes written.\r | |
119 | @param[in] Buffer The source data buffer for the write.\r | |
120 | \r | |
121 | @retval EFI_SUCCESS Opertion is successful.\r | |
122 | @retval EFI_DEVICE_ERROR If there is any device errors.\r | |
123 | \r | |
124 | **/\r | |
125 | EFI_STATUS\r | |
126 | EFIAPI\r | |
127 | SpiFlashWrite (\r | |
128 | IN UINTN Address,\r | |
129 | IN OUT UINT32 *NumBytes,\r | |
130 | IN UINT8 *Buffer\r | |
131 | )\r | |
132 | {\r | |
133 | EFI_STATUS Status;\r | |
134 | UINTN Offset;\r | |
135 | UINT32 Length;\r | |
136 | UINT32 RemainingBytes;\r | |
137 | \r | |
138 | ASSERT ((NumBytes != NULL) && (Buffer != NULL));\r | |
139 | ASSERT (Address >= (UINTN)PcdGet32 (PcdFlashChipBase));\r | |
140 | \r | |
141 | Offset = Address - (UINTN)PcdGet32 (PcdFlashChipBase);\r | |
142 | \r | |
143 | ASSERT ((*NumBytes + Offset) <= (UINTN)PcdGet32 (PcdFlashChipSize));\r | |
144 | \r | |
145 | Status = EFI_SUCCESS;\r | |
146 | RemainingBytes = *NumBytes;\r | |
147 | \r | |
148 | while (RemainingBytes > 0) {\r | |
149 | if (RemainingBytes > SIZE_4KB) {\r | |
150 | Length = SIZE_4KB;\r | |
151 | } else {\r | |
152 | Length = RemainingBytes;\r | |
153 | }\r | |
154 | Status = mSpiProtocol->Execute (\r | |
155 | mSpiProtocol,\r | |
156 | SPI_PROG,\r | |
157 | SPI_WREN,\r | |
158 | TRUE,\r | |
159 | TRUE,\r | |
160 | TRUE,\r | |
161 | (UINT32) Offset,\r | |
162 | Length,\r | |
163 | Buffer,\r | |
164 | EnumSpiRegionAll\r | |
165 | );\r | |
166 | if (EFI_ERROR (Status)) {\r | |
167 | break;\r | |
168 | }\r | |
169 | RemainingBytes -= Length;\r | |
170 | Offset += Length;\r | |
171 | Buffer += Length;\r | |
172 | }\r | |
173 | \r | |
174 | //\r | |
175 | // Actual number of bytes written\r | |
176 | //\r | |
177 | *NumBytes -= RemainingBytes;\r | |
178 | \r | |
179 | return Status;\r | |
180 | }\r | |
181 | \r | |
182 | \r | |
183 | EFI_STATUS\r | |
184 | InternalReadBlock (\r | |
185 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
186 | OUT VOID *ReadBuffer\r | |
187 | )\r | |
188 | {\r | |
189 | EFI_STATUS Status;\r | |
190 | UINT32 BlockSize;\r | |
191 | \r | |
192 | BlockSize = BLOCK_SIZE;\r | |
193 | \r | |
194 | Status = SpiFlashRead ((UINTN) BaseAddress, &BlockSize, ReadBuffer);\r | |
195 | \r | |
196 | return Status;\r | |
197 | }\r | |
198 | \r | |
199 | /**\r | |
200 | Erase the block starting at Address.\r | |
201 | \r | |
202 | @param[in] Address The starting physical address of the block to be erased.\r | |
203 | This library assume that caller garantee that the PAddress\r | |
204 | is at the starting address of this block.\r | |
205 | @param[in] NumBytes On input, the number of bytes of the logical block to be erased.\r | |
206 | On output, the actual number of bytes erased.\r | |
207 | \r | |
208 | @retval EFI_SUCCESS. Opertion is successful.\r | |
209 | @retval EFI_DEVICE_ERROR If there is any device errors.\r | |
210 | \r | |
211 | **/\r | |
212 | EFI_STATUS\r | |
213 | EFIAPI\r | |
214 | SpiFlashBlockErase (\r | |
215 | IN UINTN Address,\r | |
216 | IN UINTN *NumBytes\r | |
217 | )\r | |
218 | {\r | |
219 | EFI_STATUS Status;\r | |
220 | UINTN Offset;\r | |
221 | UINTN RemainingBytes;\r | |
222 | \r | |
223 | ASSERT (NumBytes != NULL);\r | |
224 | ASSERT (Address >= (UINTN)PcdGet32 (PcdFlashChipBase));\r | |
225 | \r | |
226 | Offset = Address - (UINTN)PcdGet32 (PcdFlashChipBase);\r | |
227 | \r | |
228 | ASSERT ((*NumBytes % SIZE_4KB) == 0);\r | |
229 | ASSERT ((*NumBytes + Offset) <= (UINTN)PcdGet32 (PcdFlashChipSize));\r | |
230 | \r | |
231 | Status = EFI_SUCCESS;\r | |
232 | RemainingBytes = *NumBytes;\r | |
233 | \r | |
234 | //\r | |
235 | // To adjust the Offset with Bios/Gbe\r | |
236 | //\r | |
237 | // if (Address >= (UINTN)PcdGet32 (PcdFlashChipBase)) {\r | |
238 | // Offset = Address - (UINTN)PcdGet32 (PcdFlashChipBase);\r | |
239 | \r | |
240 | while (RemainingBytes > 0) {\r | |
241 | Status = mSpiProtocol->Execute (\r | |
242 | mSpiProtocol,\r | |
243 | SPI_SERASE,\r | |
244 | SPI_WREN,\r | |
245 | FALSE,\r | |
246 | TRUE,\r | |
247 | FALSE,\r | |
248 | (UINT32) Offset,\r | |
249 | 0,\r | |
250 | NULL,\r | |
251 | EnumSpiRegionAll\r | |
252 | );\r | |
253 | if (EFI_ERROR (Status)) {\r | |
254 | break;\r | |
255 | }\r | |
256 | RemainingBytes -= SIZE_4KB;\r | |
257 | Offset += SIZE_4KB;\r | |
258 | }\r | |
259 | // }\r | |
260 | \r | |
261 | //\r | |
262 | // Actual number of bytes erased\r | |
263 | //\r | |
264 | *NumBytes -= RemainingBytes;\r | |
265 | \r | |
266 | return Status;\r | |
267 | }\r | |
268 | \r | |
269 | /**\r | |
270 | \r | |
271 | Routine Description:\r | |
272 | \r | |
273 | Erase the whole block.\r | |
274 | \r | |
275 | Arguments:\r | |
276 | \r | |
277 | BaseAddress - Base address of the block to be erased.\r | |
278 | \r | |
279 | Returns:\r | |
280 | \r | |
281 | EFI_SUCCESS - The command completed successfully.\r | |
282 | Other - Device error or wirte-locked, operation failed.\r | |
283 | \r | |
284 | **/\r | |
285 | EFI_STATUS\r | |
286 | InternalEraseBlock (\r | |
287 | IN EFI_PHYSICAL_ADDRESS BaseAddress\r | |
288 | )\r | |
289 | {\r | |
290 | EFI_STATUS Status;\r | |
291 | UINTN NumBytes;\r | |
292 | \r | |
293 | NumBytes = BLOCK_SIZE;\r | |
294 | \r | |
295 | Status = SpiFlashBlockErase ((UINTN) BaseAddress, &NumBytes);\r | |
296 | \r | |
297 | return Status;\r | |
298 | }\r | |
299 | \r | |
300 | EFI_STATUS\r | |
301 | InternalCompareBlock (\r | |
302 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
303 | IN UINT8 *Buffer\r | |
304 | )\r | |
305 | {\r | |
306 | EFI_STATUS Status;\r | |
307 | VOID *CompareBuffer;\r | |
308 | UINT32 NumBytes;\r | |
309 | INTN CompareResult;\r | |
310 | \r | |
311 | NumBytes = BLOCK_SIZE;\r | |
312 | CompareBuffer = AllocatePool (NumBytes);\r | |
313 | if (CompareBuffer == NULL) {\r | |
314 | Status = EFI_OUT_OF_RESOURCES;\r | |
315 | goto Done;\r | |
316 | }\r | |
317 | \r | |
318 | Status = SpiFlashRead ((UINTN) BaseAddress, &NumBytes, CompareBuffer);\r | |
319 | if (EFI_ERROR (Status)) {\r | |
320 | goto Done;\r | |
321 | }\r | |
322 | CompareResult = CompareMem (CompareBuffer, Buffer, BLOCK_SIZE);\r | |
323 | if (CompareResult != 0) {\r | |
324 | Status = EFI_VOLUME_CORRUPTED;\r | |
325 | }\r | |
326 | \r | |
327 | Done:\r | |
328 | if (CompareBuffer != NULL) {\r | |
329 | FreePool (CompareBuffer);\r | |
330 | }\r | |
331 | \r | |
332 | return Status;\r | |
333 | }\r | |
334 | \r | |
335 | /**\r | |
336 | \r | |
337 | Routine Description:\r | |
338 | \r | |
339 | Write a block of data.\r | |
340 | \r | |
341 | Arguments:\r | |
342 | \r | |
343 | BaseAddress - Base address of the block.\r | |
344 | Buffer - Data buffer.\r | |
345 | BufferSize - Size of the buffer.\r | |
346 | \r | |
347 | Returns:\r | |
348 | \r | |
349 | EFI_SUCCESS - The command completed successfully.\r | |
350 | EFI_INVALID_PARAMETER - Invalid parameter, can not proceed.\r | |
351 | Other - Device error or wirte-locked, operation failed.\r | |
352 | \r | |
353 | **/\r | |
354 | EFI_STATUS\r | |
355 | InternalWriteBlock (\r | |
356 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
357 | IN UINT8 *Buffer,\r | |
358 | IN UINT32 BufferSize\r | |
359 | )\r | |
360 | {\r | |
361 | EFI_STATUS Status;\r | |
362 | \r | |
363 | Status = SpiFlashWrite ((UINTN) BaseAddress, &BufferSize, Buffer);\r | |
364 | \r | |
365 | if (EFI_ERROR (Status)) {\r | |
366 | DEBUG((DEBUG_ERROR, "\nFlash write error."));\r | |
367 | return Status;\r | |
368 | }\r | |
369 | \r | |
370 | WriteBackInvalidateDataCacheRange ((VOID *) (UINTN) BaseAddress, BLOCK_SIZE);\r | |
371 | \r | |
372 | Status = InternalCompareBlock (BaseAddress, Buffer);\r | |
373 | if (EFI_ERROR (Status)) {\r | |
374 | DEBUG((DEBUG_ERROR, "\nError when writing to BaseAddress %x with different at offset %x.", BaseAddress, Status));\r | |
375 | } else {\r | |
376 | DEBUG((DEBUG_INFO, "\nVerified data written to Block at %x is correct.", BaseAddress));\r | |
377 | }\r | |
378 | \r | |
379 | return Status;\r | |
380 | \r | |
381 | }\r | |
382 | \r | |
75ce133c JY |
383 | /**\r |
384 | Perform flash write opreation.\r | |
385 | \r | |
386 | @param[in] FirmwareType The type of firmware.\r | |
387 | @param[in] FlashAddress The address of flash device to be accessed.\r | |
388 | @param[in] FlashAddressType The type of flash device address.\r | |
389 | @param[in] Buffer The pointer to the data buffer.\r | |
390 | @param[in] Length The length of data buffer in bytes.\r | |
391 | \r | |
392 | @retval EFI_SUCCESS The operation returns successfully.\r | |
393 | @retval EFI_WRITE_PROTECTED The flash device is read only.\r | |
394 | @retval EFI_UNSUPPORTED The flash device access is unsupported.\r | |
395 | @retval EFI_INVALID_PARAMETER The input parameter is not valid.\r | |
396 | **/\r | |
397 | EFI_STATUS\r | |
398 | EFIAPI\r | |
399 | PerformFlashWrite (\r | |
400 | IN PLATFORM_FIRMWARE_TYPE FirmwareType,\r | |
401 | IN EFI_PHYSICAL_ADDRESS FlashAddress,\r | |
402 | IN FLASH_ADDRESS_TYPE FlashAddressType,\r | |
403 | IN VOID *Buffer,\r | |
404 | IN UINTN Length\r | |
405 | )\r | |
406 | {\r | |
27f44846 KM |
407 | EFI_STATUS Status = EFI_SUCCESS;\r |
408 | UINTN Index;\r | |
409 | EFI_PHYSICAL_ADDRESS Address;\r | |
410 | UINTN CountOfBlocks;\r | |
411 | EFI_TPL OldTpl;\r | |
412 | BOOLEAN FlashError;\r | |
413 | UINT8 *Buf;\r | |
414 | UINTN LpcBaseAddress;\r | |
415 | UINT8 Data8Or;\r | |
416 | UINT8 Data8And;\r | |
417 | UINT8 BiosCntl;\r | |
418 | \r | |
419 | Index = 0;\r | |
420 | Address = 0;\r | |
421 | CountOfBlocks = 0;\r | |
422 | FlashError = FALSE;\r | |
423 | Buf = Buffer;\r | |
75ce133c | 424 | \r |
27f44846 | 425 | DEBUG((DEBUG_INFO | DEBUG_ERROR, "PerformFlashWrite - 0x%x(%x) - 0x%x\n", (UINTN)FlashAddress, (UINTN)FlashAddressType, Length));\r |
75ce133c JY |
426 | if (FlashAddressType == FlashAddressTypeRelativeAddress) {\r |
427 | FlashAddress = FlashAddress + mInternalFdAddress;\r | |
428 | }\r | |
429 | \r | |
27f44846 KM |
430 | CountOfBlocks = (UINTN) (Length / BLOCK_SIZE);\r |
431 | Address = FlashAddress;\r | |
75ce133c | 432 | \r |
27f44846 KM |
433 | LpcBaseAddress = MmPciAddress (0,\r |
434 | DEFAULT_PCI_BUS_NUMBER_PCH,\r | |
435 | PCI_DEVICE_NUMBER_PCH_LPC,\r | |
436 | PCI_FUNCTION_NUMBER_PCH_LPC,\r | |
437 | 0\r | |
438 | );\r | |
439 | BiosCntl = MmioRead8 (LpcBaseAddress + R_PCH_LPC_BIOS_CNTL);\r | |
440 | if ((BiosCntl & B_PCH_LPC_BIOS_CNTL_SMM_BWP) == B_PCH_LPC_BIOS_CNTL_SMM_BWP) {\r | |
441 | ///\r | |
442 | /// Clear SMM_BWP bit (D31:F0:RegDCh[5])\r | |
443 | ///\r | |
444 | Data8And = (UINT8) ~B_PCH_LPC_BIOS_CNTL_SMM_BWP;\r | |
445 | Data8Or = 0x00;\r | |
446 | \r | |
447 | MmioAndThenOr8 (\r | |
448 | LpcBaseAddress + R_PCH_LPC_BIOS_CNTL,\r | |
449 | Data8And,\r | |
450 | Data8Or\r | |
451 | );\r | |
452 | DEBUG((DEBUG_INFO, "PerformFlashWrite Clear SMM_BWP bit\n"));\r | |
453 | }\r | |
454 | \r | |
455 | //\r | |
456 | // Raise TPL to TPL_NOTIFY to block any event handler,\r | |
457 | // while still allowing RaiseTPL(TPL_NOTIFY) within\r | |
458 | // output driver during Print()\r | |
75ce133c | 459 | //\r |
27f44846 KM |
460 | OldTpl = gBS->RaiseTPL (TPL_NOTIFY);\r |
461 | for (Index = 0; Index < CountOfBlocks; Index++) {\r | |
462 | //\r | |
463 | // Handle block based on address and contents.\r | |
464 | //\r | |
465 | if (!EFI_ERROR (InternalCompareBlock (Address, Buf))) {\r | |
466 | DEBUG((DEBUG_INFO, "Skipping block at 0x%lx (already programmed)\n", Address));\r | |
467 | } else {\r | |
468 | //\r | |
469 | // Display a dot for each block being updated.\r | |
470 | //\r | |
471 | Print (L".");\r | |
472 | \r | |
473 | //\r | |
474 | // Make updating process uninterruptable,\r | |
475 | // so that the flash memory area is not accessed by other entities\r | |
476 | // which may interfere with the updating process\r | |
477 | //\r | |
478 | Status = InternalEraseBlock (Address);\r | |
75ce133c | 479 | if (EFI_ERROR(Status)) {\r |
27f44846 KM |
480 | gBS->RestoreTPL (OldTpl);\r |
481 | FlashError = TRUE;\r | |
482 | goto Done;\r | |
75ce133c | 483 | }\r |
27f44846 KM |
484 | Status = InternalWriteBlock (\r |
485 | Address,\r | |
486 | Buf,\r | |
487 | (UINT32)(Length > BLOCK_SIZE ? BLOCK_SIZE : Length)\r | |
488 | );\r | |
75ce133c | 489 | if (EFI_ERROR(Status)) {\r |
27f44846 KM |
490 | gBS->RestoreTPL (OldTpl);\r |
491 | FlashError = TRUE;\r | |
492 | goto Done;\r | |
493 | }\r | |
75ce133c JY |
494 | }\r |
495 | \r | |
27f44846 KM |
496 | //\r |
497 | // Move to next block to update.\r | |
498 | //\r | |
499 | Address += BLOCK_SIZE;\r | |
500 | Buf += BLOCK_SIZE;\r | |
501 | if (Length > BLOCK_SIZE) {\r | |
502 | Length -= BLOCK_SIZE;\r | |
503 | } else {\r | |
504 | Length = 0;\r | |
505 | }\r | |
506 | }\r | |
507 | gBS->RestoreTPL (OldTpl);\r | |
508 | \r | |
509 | Done:\r | |
510 | if ((BiosCntl & B_PCH_LPC_BIOS_CNTL_SMM_BWP) == B_PCH_LPC_BIOS_CNTL_SMM_BWP) {\r | |
511 | //\r | |
512 | // Restore original control setting\r | |
513 | //\r | |
514 | MmioWrite8 (LpcBaseAddress + R_PCH_LPC_BIOS_CNTL, BiosCntl);\r | |
515 | }\r | |
516 | \r | |
517 | //\r | |
518 | // Print flash update failure message if error detected.\r | |
519 | //\r | |
520 | if (FlashError) {\r | |
521 | Print (L"No %r\n", Status);\r | |
522 | }\r | |
75ce133c JY |
523 | \r |
524 | return EFI_SUCCESS;\r | |
525 | }\r | |
526 | \r | |
527 | /**\r | |
528 | Perform microcode write opreation.\r | |
529 | \r | |
530 | @param[in] FlashAddress The address of flash device to be accessed.\r | |
531 | @param[in] Buffer The pointer to the data buffer.\r | |
532 | @param[in] Length The length of data buffer in bytes.\r | |
533 | \r | |
534 | @retval EFI_SUCCESS The operation returns successfully.\r | |
535 | @retval EFI_WRITE_PROTECTED The flash device is read only.\r | |
536 | @retval EFI_UNSUPPORTED The flash device access is unsupported.\r | |
537 | @retval EFI_INVALID_PARAMETER The input parameter is not valid.\r | |
538 | **/\r | |
539 | EFI_STATUS\r | |
540 | EFIAPI\r | |
541 | MicrocodeFlashWrite (\r | |
542 | IN EFI_PHYSICAL_ADDRESS FlashAddress,\r | |
543 | IN VOID *Buffer,\r | |
544 | IN UINTN Length\r | |
545 | )\r | |
546 | {\r | |
547 | EFI_PHYSICAL_ADDRESS AlignedFlashAddress;\r | |
548 | VOID *AlignedBuffer;\r | |
549 | UINTN AlignedLength;\r | |
550 | UINTN OffsetHead;\r | |
551 | UINTN OffsetTail;\r | |
552 | EFI_STATUS Status;\r | |
553 | \r | |
554 | DEBUG((DEBUG_INFO, "MicrocodeFlashWrite - 0x%x - 0x%x\n", (UINTN)FlashAddress, Length));\r | |
555 | \r | |
556 | //\r | |
557 | // Need make buffer 64K aligned to support ERASE\r | |
558 | //\r | |
559 | // [Aligned] FlashAddress [Aligned]\r | |
560 | // | | |\r | |
561 | // V V V\r | |
562 | // +--------------+========+------------+\r | |
563 | // | OffsetHeader | Length | OffsetTail |\r | |
564 | // +--------------+========+------------+\r | |
565 | // ^\r | |
566 | // |<-----------AlignedLength----------->\r | |
567 | // |\r | |
568 | // AlignedFlashAddress\r | |
569 | //\r | |
570 | OffsetHead = FlashAddress & (ALINGED_SIZE - 1);\r | |
571 | OffsetTail = (FlashAddress + Length) & (ALINGED_SIZE - 1);\r | |
572 | if (OffsetTail != 0) {\r | |
573 | OffsetTail = ALINGED_SIZE - OffsetTail;\r | |
574 | }\r | |
575 | \r | |
576 | if ((OffsetHead != 0) || (OffsetTail != 0)) {\r | |
577 | AlignedFlashAddress = FlashAddress - OffsetHead;\r | |
578 | AlignedLength = Length + OffsetHead + OffsetTail;\r | |
579 | \r | |
580 | AlignedBuffer = AllocatePool(AlignedLength);\r | |
581 | if (AlignedBuffer == NULL) {\r | |
582 | return EFI_OUT_OF_RESOURCES;\r | |
583 | }\r | |
584 | //\r | |
585 | // Save original buffer\r | |
586 | //\r | |
587 | if (OffsetHead != 0) {\r | |
71d86ec8 | 588 | CopyMem((UINT8 *)AlignedBuffer, (VOID *)(UINTN)AlignedFlashAddress, OffsetHead);\r |
75ce133c JY |
589 | }\r |
590 | if (OffsetTail != 0) {\r | |
71d86ec8 | 591 | CopyMem((UINT8 *)AlignedBuffer + OffsetHead + Length, (VOID *)(UINTN)(AlignedFlashAddress + OffsetHead + Length), OffsetTail);\r |
75ce133c JY |
592 | }\r |
593 | //\r | |
594 | // Override new buffer\r | |
595 | //\r | |
596 | CopyMem((UINT8 *)AlignedBuffer + OffsetHead, Buffer, Length);\r | |
597 | } else {\r | |
598 | AlignedFlashAddress = FlashAddress;\r | |
599 | AlignedBuffer = Buffer;\r | |
600 | AlignedLength = Length;\r | |
601 | }\r | |
602 | \r | |
603 | Status = PerformFlashWrite(\r | |
604 | PlatformFirmwareTypeSystemFirmware,\r | |
605 | AlignedFlashAddress,\r | |
606 | FlashAddressTypeAbsoluteAddress,\r | |
607 | AlignedBuffer,\r | |
608 | AlignedLength\r | |
609 | );\r | |
610 | if ((OffsetHead != 0) || (OffsetTail != 0)) {\r | |
611 | FreePool (AlignedBuffer);\r | |
612 | }\r | |
613 | return Status;\r | |
614 | }\r | |
615 | \r | |
616 | /**\r | |
617 | Platform Flash Access Lib Constructor.\r | |
618 | **/\r | |
619 | EFI_STATUS\r | |
620 | EFIAPI\r | |
621 | PerformFlashAccessLibConstructor (\r | |
622 | VOID\r | |
623 | )\r | |
624 | {\r | |
27f44846 | 625 | EFI_STATUS Status;\r |
75ce133c JY |
626 | mInternalFdAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32(PcdFlashAreaBaseAddress);\r |
627 | DEBUG((DEBUG_INFO, "PcdFlashAreaBaseAddress - 0x%x\n", mInternalFdAddress));\r | |
628 | \r | |
27f44846 KM |
629 | Status = gBS->LocateProtocol (\r |
630 | &gEfiSpiProtocolGuid,\r | |
631 | NULL,\r | |
632 | (VOID **) &mSpiProtocol\r | |
633 | );\r | |
634 | ASSERT_EFI_ERROR(Status);\r | |
635 | \r | |
75ce133c JY |
636 | return EFI_SUCCESS;\r |
637 | }\r |