Vlv2DeviceRefCodePkg&Vlv2TbltDevicePkg:Convert Mix to DOS.
[mirror_edk2.git] / Vlv2TbltDevicePkg / Include / Protocol / GlobalNvsArea.h
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1/** @file\r
2\r
3 Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>\r
4\r
5\r
6 This program and the accompanying materials are licensed and made available under\r
7\r
8 the terms and conditions of the BSD License that accompanies this distribution.\r
9\r
10 The full text of the license may be found at\r
11\r
12 http://opensource.org/licenses/bsd-license.php.\r
13\r
14\r
15\r
16 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
17\r
18 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
19\r
20\r
21\r
22\r
23\r
24Module Name:\r
25\r
26 GlobalNvsArea.h\r
27\r
28Abstract:\r
29\r
30 Definition of the global NVS area protocol. This protocol\r
31 publishes the address and format of a global ACPI NVS buffer used as a communications\r
32 buffer between SMM code and ASL code.\r
33 The format is derived from the ACPI reference code, version 0.95.\r
34\r
35 Note: Data structures defined in this protocol are not naturally aligned.\r
36\r
37**/\r
38\r
39\r
40#ifndef _GLOBAL_NVS_AREA_H_\r
41#define _GLOBAL_NVS_AREA_H_\r
42\r
43//\r
44// Includes\r
45//\r
46#define GLOBAL_NVS_DEVICE_ENABLE 1\r
47#define GLOBAL_NVS_DEVICE_DISABLE 0\r
48\r
49//\r
50// Forward reference for pure ANSI compatibility\r
51//\r
52\r
53//EFI_FORWARD_DECLARATION (EFI_GLOBAL_NVS_AREA_PROTOCOL);\r
54\r
55//\r
56// Global NVS Area Protocol GUID\r
57//\r
58#define EFI_GLOBAL_NVS_AREA_PROTOCOL_GUID \\r
59{ 0x74e1e48, 0x8132, 0x47a1, 0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc }\r
60\r
61//\r
62// Revision id - Added TPM related fields\r
63//\r
64#define GLOBAL_NVS_AREA_RIVISION_1 1\r
65\r
66//\r
67// Extern the GUID for protocol users.\r
68//\r
69extern EFI_GUID gEfiGlobalNvsAreaProtocolGuid;\r
70\r
71//\r
72// Global NVS Area definition\r
73//\r
74#pragma pack (1)\r
75typedef struct {\r
76 //\r
77 // Miscellaneous Dynamic Values, the definitions below need to be matched\r
78 // GNVS definitions in Platform.ASL\r
79 //\r
80 UINT16 OperatingSystem; // 00\r
81 UINT8 SmiFunction; // 02 SMI function call via IO Trap\r
82 UINT8 SmiParameter0; // 03\r
83 UINT8 SmiParameter1; // 04\r
84 UINT8 SciFunction; // 05 SCI function call via _L00\r
85 UINT8 SciParameter0; // 06\r
86 UINT8 SciParameter1; // 07\r
87 UINT8 GlobalLock; // 08 Global lock function call\r
88 UINT8 LockParameter0; // 09\r
89 UINT8 LockParameter1; // 10\r
90 UINT32 Port80DebugValue; // 11\r
91 UINT8 LidState; // 15 Open = 1\r
92 UINT8 PowerState; // 16 AC = 1\r
93 UINT8 DebugState; // 17\r
94\r
95\r
96 //\r
97 // Thermal Policy Values\r
98 //\r
99 UINT8 EnableThermalOffset; // 18 ThermalOffset for KSC\r
100 UINT8 Reserved1; // 19\r
101 UINT8 Reserved2; // 20\r
102 UINT8 PassiveThermalTripPoint; // 21\r
103 UINT8 PassiveTc1Value; // 22\r
104 UINT8 PassiveTc2Value; // 23\r
105 UINT8 PassiveTspValue; // 24\r
106 UINT8 CriticalThermalTripPoint; // 25\r
107 UINT8 EnableDigitalThermalSensor; // 26\r
108 UINT8 BspDigitalThermalSensorTemperature; // 27 Temperature of BSP\r
109 UINT8 ApDigitalThermalSensorTemperature; // 28 Temperature of AP\r
110 UINT8 DigitalThermalSensorSmiFunction; // 29 SMI function call via DTS IO Trap\r
111\r
112 //\r
113 // Battery Support Values\r
114 //\r
115 UINT8 NumberOfBatteries; // 30\r
116 UINT8 BatteryCapacity0; // 31 Battery 0 Stored Capacity\r
117 UINT8 BatteryCapacity1; // 32 Battery 1 Stored Capacity\r
118 UINT8 BatteryCapacity2; // 33 Battery 2 Stored Capacity\r
119 UINT8 BatteryStatus0; // 34 Battery 0 Stored Status\r
120 UINT8 BatteryStatus1; // 35 Battery 1 Stored Status\r
121 UINT8 BatteryStatus2; // 36 Battery 2 Stored Status\r
122\r
123 // NOTE: Do NOT Change the Offset of Revision Field\r
124 UINT8 Revision; // 37 Revision of the structure EFI_GLOBAL_NVS_AREA\r
125 UINT8 Reserved3[2]; // 38:39\r
126\r
127 //\r
128 // Processor Configuration Values\r
129 //\r
130 UINT8 ApicEnable; // 40 APIC Enabled by SBIOS (APIC Enabled = 1)\r
131 UINT8 LogicalProcessorCount; // 41 Processor Count Enabled (MP Enabled != 0)\r
132 UINT8 CurentPdcState0; // 42 PDC settings, Processor 0\r
133 UINT8 CurentPdcState1; // 43 PDC settings, Processor 1\r
134 UINT8 MaximumPpcState; // 44 Maximum PPC state\r
135 UINT32 PpmFlags; // 45:48 PPM configuration flags, same as CFGD\r
136 UINT8 Reserved4[1]; // 49\r
137\r
138 //\r
139 // SIO Configuration Values\r
140 //\r
141 UINT8 DockedSioPresent; // 50 Dock SIO Present\r
142 UINT8 DockComA; // 51 COM A Port\r
143 UINT8 DockComB; // 52 COM B Port\r
144 UINT8 LptP; // 53 LPT Port\r
145 UINT8 DockFdc; // 54 FDC Port\r
146 UINT8 OnboardCom; // 55 Onboard COM Port\r
147 UINT8 OnboardComCir; // 56 Onboard COM CIR Port\r
148\r
149 UINT8 WPCN381U; // 57\r
150 UINT8 NPCE791x; // 58\r
151 UINT8 Reserved5[1]; // 59\r
152\r
153 //\r
154 // Internal Graphics Device Values\r
155 //\r
156 UINT8 IgdState; // 60 IGD State (Primary Display = 1)\r
157 UINT8 DisplayToggleList; // 61 Display Toggle List Selection\r
158 UINT8 CurrentDeviceList; // 62 Current Attached Device List\r
159 UINT8 PreviousDeviceList; // 63 Previous Attached Device List\r
160 UINT16 CurrentDisplayState; // 64 Current Display State\r
161 UINT16 NextDisplayState; // 66 Next Display State\r
162 UINT16 SetDisplayState; // 68 Set Display State\r
163 UINT8 NumberOfValidDeviceId; // 70 Number of Valid Device IDs\r
164 UINT32 DeviceId1; // 71 Device ID 1\r
165 UINT32 DeviceId2; // 75 Device ID 2\r
166 UINT32 DeviceId3; // 79 Device ID 3\r
167 UINT32 DeviceId4; // 83 Device ID 4\r
168 UINT32 DeviceId5; // 87 Device ID 5\r
169\r
170 UINT32 AKsv0; // 91:94 First four bytes of AKSV (manufacturing mode)\r
171 UINT8 AKsv1; // 95 Fifth byte of AKSV (manufacturing mode\r
172\r
173 UINT8 Reserved6[7]; // 96:102\r
174\r
175 //\r
176 // Backlight Control Values\r
177 //\r
178 UINT8 BacklightControlSupport; // 103 Backlight Control Support\r
179 UINT8 BrightnessPercentage; // 104 Brightness Level Percentage\r
180\r
181 //\r
182 // Ambient Light Sensor Values\r
183 //\r
184 UINT8 AlsEnable; // 105 Ambient Light Sensor Enable\r
185 UINT8 AlsAdjustmentFactor; // 106 Ambient Light Adjusment Factor\r
186 UINT8 LuxLowValue; // 107 LUX Low Value\r
187 UINT8 LuxHighValue; // 108 LUX High Value\r
188\r
189 UINT8 Reserved7[1]; // 109\r
190\r
191 //\r
192 // Extended Mobile Access Values\r
193 //\r
194 UINT8 EmaEnable; // 110 EMA Enable\r
195 UINT16 EmaPointer; // 111 EMA Pointer\r
196 UINT16 EmaLength; // 113 EMA Length\r
197\r
198 UINT8 Reserved8[1]; // 115\r
199\r
200 //\r
201 // Mobile East Fork Values\r
202 //\r
203 UINT8 MefEnable; // 116 Mobile East Fork Enable\r
204\r
205 //\r
206 // PCIe Dock Status\r
207 //\r
208 UINT8 PcieDockStatus; // 117 PCIe Dock Status\r
209\r
210 UINT8 Reserved9[2]; // 118:119\r
211\r
212 //\r
213 // TPM Registers\r
214 //\r
215 UINT8 TpmPresent; // 120 TPM Present\r
216 UINT8 TpmEnable; // 121 TPM Enable\r
217\r
218 UINT8 MorData; // 122 Memory Overwrite Request Data\r
219 UINT8 TcgParamter; // 123 Used for save the Mor and/or physical presence paramter\r
220 UINT32 PPResponse; // 124 Physical Presence request operation response\r
221 UINT8 PPRequest; // 128 Physical Presence request operation\r
222 UINT8 LastPPRequest; // 129 Last Physical Presence request operation\r
223\r
224 //\r
225 // SATA Values\r
226 //\r
227 UINT8 GtfTaskFileBufferPort0[7]; // 130 GTF Task File Buffer for Port 0\r
228 UINT8 GtfTaskFileBufferPort2[7]; // 137 GTF Task File Buffer for Port 2\r
229 UINT8 IdeMode; // 144 IDE Mode (Compatible\Enhanced)\r
230 UINT8 GtfTaskFileBufferPort1[7]; // 145:151 GTF Task File Buffer for Port 1\r
231\r
232 UINT8 Reserved111[10]; // 152:161\r
233 UINT64 BootTimeLogAddress; // 162:169 Boot Time Log Table Address\r
234\r
235 UINT32 IgdOpRegionAddress; // 170 IGD OpRegion Starting Address\r
236 UINT8 IgdBootType; // 174 IGD Boot Type CMOS option\r
237 UINT8 IgdPanelType; // 175 IGD Panel Type CMOs option\r
238 UINT8 IgdTvFormat; // 176 IGD TV Format CMOS option\r
239 UINT8 IgdTvMinor; // 177 IGD TV Minor Format CMOS option\r
240 UINT8 IgdPanelScaling; // 178 IGD Panel Scaling\r
241 UINT8 IgdBlcConfig; // 179 IGD BLC Configuration\r
242 UINT8 IgdBiaConfig; // 180 IGD BIA Configuration\r
243 UINT8 IgdSscConfig; // 181 IGD SSC Configuration\r
244 UINT8 Igd409; // 182 IGD 0409 Modified Settings Flag\r
245 UINT8 Igd509; // 183 IGD 0509 Modified Settings Flag\r
246 UINT8 Igd609; // 184 IGD 0609 Modified Settings Flag\r
247 UINT8 Igd709; // 185 IGD 0709 Modified Settings Flag\r
248 UINT8 IgdPowerConservation; // 186 IGD Power Conservation Feature Flag\r
249 UINT8 IgdDvmtMemSize; // 187 IGD DVMT Memory Size\r
250 UINT8 IgdFunc1Enable; // 188 IGD Function 1 Enable\r
251 UINT8 IgdHpllVco; // 189 HPLL VCO\r
252 UINT32 NextStateDid1; // 190 Next state DID1 for _DGS\r
253 UINT32 NextStateDid2; // 194 Next state DID2 for _DGS\r
254 UINT32 NextStateDid3; // 198 Next state DID3 for _DGS\r
255 UINT32 NextStateDid4; // 202 Next state DID4 for _DGS\r
256 UINT32 NextStateDid5; // 206 Next state DID5 for _DGS\r
257 UINT32 NextStateDid6; // 210 Next state DID6 for _DGS\r
258 UINT32 NextStateDid7; // 214 Next state DID7 for _DGS\r
259 UINT32 NextStateDid8; // 218 Next state DID8 for _DGS\r
260 UINT8 IgdSciSmiMode; // 222 GMCH SMI/SCI mode (0=SCI)\r
261 UINT8 IgdPAVP; // 223 IGD PAVP data\r
262 UINT8 IgdSelfRefresh; // 224 IGD Self Refresh\r
263 UINT8 PcieOSCControl; // 225 PCIE OSC Control\r
264 UINT8 NativePCIESupport; // 226 Native PCI Express Support\r
265\r
266 //\r
267 // USB Sideband Deferring Support\r
268 //\r
269 UINT8 HostAlertVector; // 227 GPE vector used for HOST_ALERT\r
270 UINT8 HostAlertPio; // 228 PIO of USB device used for HOST_ALERT\r
271\r
272 UINT8 Reserved112[27]; // 229\r
273 UINT32 NvIgOpRegionAddress; // 256 NVIG support\r
274 UINT32 NvHmOpRegionAddress; // 260 NVHM support\r
275 UINT32 ApXmOpRegionAddress; // 264 AMDA support\r
276 UINT32 DeviceId6; // 268 Device ID 6\r
277 UINT32 DeviceId7; // 272 Device ID 7\r
278 UINT32 DeviceId8; // 276 Device ID 8\r
279 UINT32 EndpointBaseAddress; // 280 PEG Endpoint PCIe Base Address\r
280 UINT32 CapStrPresence; // 284 PEG Endpoint Capability Structure Presence\r
281 UINT32 EndpointPcieCapBaseAddress; // 288 PEG Endpoint PCIe Capability Structure Base Address\r
282 UINT32 EndpointVcCapBaseAddress; // 292 PEG Endpoint Virtual Channel Capability Structure Base Address\r
283 UINT32 XPcieCfgBaseAddress; // 296 Any Device's PCIe Config Space Base Address\r
284 UINT32 OccupiedBuses1; // 300 Occupied Buses from 0 to 31\r
285 UINT32 OccupiedBuses2; // 304 Occupied Buses from 32 to 63\r
286 UINT32 OccupiedBuses3; // 308 Occupied Buses from 64 to 95\r
287 UINT32 OccupiedBuses4; // 312 Occupied Buses from 96 to 127\r
288 UINT32 OccupiedBuses5; // 316 Occupied Buses from 128 to 159\r
289 UINT32 OccupiedBuses6; // 320 Occupied Buses from 160 to 191\r
290 UINT32 OccupiedBuses7; // 324 Occupied Buses from 192 to 223\r
291 UINT32 OccupiedBuses8; // 328 Occupied Buses from 224 to 255\r
292 UINT8 UartSelection; // 332 UART Interface Selection 0: Internal; 1: SIO\r
293 UINT8 PcuUart1Enable; // 333 PCU UART 1 Enabled\r
294 UINT8 PcuUart2Enable; // 334 PCU UART 2 Enabled\r
295\r
296 UINT32 LPEBar0; // 335~338 LPE Bar0\r
297 UINT32 LPEBar1; // 339~342 LPE Bar1\r
298\r
299 UINT32 LPEBar2; // 343~346 LPE Bar2\r
300 UINT8 AcSetup; // 347 For Ac Powered Config option - IST applet\r
301 UINT8 BatterySetup; // 348 For Battery Powered Config option - IST applet\r
302 UINT8 PlatformFlavor; // 349 0:unknown 1: Mobile; 2: desktop\r
303 UINT8 Reserved113[1]; // 350\r
304\r
305 UINT8 IsctReserve; // 351 ISCT / AOAC Configuration\r
306 UINT8 XhciMode; // 352 xHCI mode\r
307 UINT8 PmicEnable; // 353 PMIC enable\r
308\r
309 UINT8 LpeEnable; // 354 LPE enable\r
310 UINT32 ISPAddr; // 355 ISP Base address\r
311 UINT8 ISPDevSel; // 359 ISP device enabled selection 0: Disabled; 1: PCI Device 2; 2: PCI Device 3\r
312\r
313 //\r
314 // Lpss controllers\r
315 //\r
316 UINT32 PCIBottomAddress; //360 ((4+8+6)*4+2)*4=296\r
317 UINT32 PCITopAddress; //364\r
318\r
319 UINT32 LDMA1Addr; // 368\r
320 UINT32 LDMA1Len; // 372\r
321 UINT32 LDMA11Addr; // 376\r
322 UINT32 LDMA11Len; // 380\r
323 UINT32 PWM1Addr; // 384 PWM1\r
324 UINT32 PWM1Len; // 388\r
325 UINT32 PWM11Addr; // 392\r
326 UINT32 PWM11Len; // 396\r
327 UINT32 PWM2Addr; // 400 PWM2\r
328 UINT32 PWM2Len; // 404\r
329 UINT32 PWM21Addr; // 408\r
330 UINT32 PWM21Len; // 412\r
331 UINT32 UART1Addr; // 416 UART1\r
332 UINT32 UART1Len; // 420\r
333 UINT32 UART11Addr; // 424 UART1\r
334 UINT32 UART11Len; // 428\r
335 UINT32 UART2Addr; // 432 UART2\r
336 UINT32 UART2Len; // 436\r
337 UINT32 UART21Addr; // 440 UART2\r
338 UINT32 UART21Len; // 444\r
339 UINT32 SPIAddr; // 448 SPI\r
340 UINT32 SPILen; // 452\r
341 UINT32 SPI1Addr; // 456\r
342 UINT32 SPI1Len; // 460\r
343\r
344 UINT32 LDMA2Addr; // 464\r
345 UINT32 LDMA2Len; // 468\r
346 UINT32 LDMA21Addr; // 472\r
347 UINT32 LDMA21Len; // 476\r
348 UINT32 I2C1Addr; // 480 I2C1\r
349 UINT32 I2C1Len; // 484\r
350 UINT32 I2C11Addr; // 488 I2C1\r
351 UINT32 I2C11Len; // 492\r
352 UINT32 I2C2Addr; // 496 I2C2\r
353 UINT32 I2C2Len; // 500\r
354 UINT32 I2C21Addr; // 504 I2C2\r
355 UINT32 I2C21Len; // 508\r
356 UINT32 I2C3Addr; // 512 I2C3\r
357 UINT32 I2C3Len; // 516\r
358 UINT32 I2C31Addr; // 520 I2C3\r
359 UINT32 I2C31Len; // 524\r
360 UINT32 I2C4Addr; // 528 I2C4\r
361 UINT32 I2C4Len; // 532\r
362 UINT32 I2C41Addr; // 536 I2C4\r
363 UINT32 I2C41Len; // 540\r
364 UINT32 I2C5Addr; // 544 I2C5\r
365 UINT32 I2C5Len; // 548\r
366 UINT32 I2C51Addr; // 552 I2C5\r
367 UINT32 I2C51Len; // 556\r
368 UINT32 I2C6Addr; // 560 I2C6\r
369 UINT32 I2C6Len; // 564\r
370 UINT32 I2C61Addr; // 566 I2C6\r
371 UINT32 I2C61Len; // 570\r
372 UINT32 I2C7Addr; // 574 I2C7\r
373 UINT32 I2C7Len; // 578\r
374 UINT32 I2C71Addr; // 582 I2C7\r
375 UINT32 I2C71Len; // 586\r
376\r
377 //\r
378 // Scc controllers\r
379 //\r
380 UINT32 eMMCAddr; // 590 EMMC\r
381 UINT32 eMMCLen; // 594\r
382 UINT32 eMMC1Addr; // 598\r
383 UINT32 eMMC1Len; // 602\r
384 UINT32 SDIOAddr; // 606 SDIO\r
385 UINT32 SDIOLen; // 610\r
386 UINT32 SDIO1Addr; // 614\r
387 UINT32 SDIO1Len; // 618\r
388 UINT32 SDCardAddr; // 622 SDCard\r
389 UINT32 SDCardLen; // 626\r
390 UINT32 SDCard1Addr; // 630\r
391 UINT32 SDCard1Len; // 636\r
392 UINT32 MipiHsiAddr; // 640 MIPI-HSI\r
393 UINT32 MipiHsiLen; // 644\r
394 UINT32 MipiHsi1Addr; // 648\r
395 UINT32 MipiHsi1Len; // 652\r
396\r
397 UINT8 SdCardRemovable; // 656 reserve offset upto 658\r
398 UINT8 HideLPSSDevices; // 657 Hide unsupported LPSS devices when in ACPI mode\r
399 UINT8 ReservedO; // 658 OS Selection\r
400 UINT8 Reserved00; // 659\r
401 UINT8 Reserved01; // 660\r
402 UINT8 Reserved02; // 661\r
403 UINT8 Reserved03; // 662\r
404 UINT8 Reserved04; // 663\r
405 UINT8 Reserved05; // 664\r
406 UINT8 Reserved06; // 665\r
407 UINT8 Reserved07; // 666\r
408 UINT8 Reserved08; // 667\r
409 UINT8 Reserved09; // 668\r
410 UINT8 Reserved0A; // 669\r
411 UINT32 Reserved0B; // 670\r
412 UINT32 Reserved0C; // 674\r
413 UINT32 Reserved0D; // 678\r
414 UINT32 Reserved0E; // 682\r
415 UINT32 Reserved0F; // 686\r
416 UINT32 Reserved10; // 690\r
417 UINT32 Reserved11; // 694\r
418 UINT32 Reserved12; // 698\r
419 UINT32 Reserved13; // 702\r
420 UINT32 Reserved14; // 706\r
421 UINT32 Reserved15; // 710\r
422 UINT32 Reserved16; // 714\r
423 UINT8 Reserved17;\r
424 UINT32 Reserved18;\r
425 UINT32 Reserved19;\r
426 UINT32 Reserved1A;\r
427 UINT32 Reserved1B;\r
428 UINT32 Reserved1C;\r
429 UINT8 Reserved1D;\r
430 UINT32 Reserved1E;\r
431 UINT32 Reserved1F;\r
432 UINT32 Reserved20;\r
433 UINT32 Reserved21;\r
434 UINT32 Reserved22;\r
435 UINT8 Reserved23;\r
436 UINT8 BatteryChargingSolution; // 761 0-non ULPMC 1-ULPMC\r
437\r
438 //\r
439 //101 bytes\r
440 //\r
441 UINT8 NFCnSelect; // 762 NFCx Select 1: NFC1 2:NFC2\r
442 UINT8 LpssSccMode; // 763 EMMC device 0-ACPI mode, 1-PCI mode\r
443\r
444 UINT32 TPMAddress; // 764\r
445 UINT32 TPMLength; // 768\r
446\r
447 UINT8 I2CTouchAddress; // 772 I2C touch address, 0x4B:RVP 0x4A:FFRD\r
448 UINT8 IdleReserve; // 773 0 - disabled 1 - enabled\r
449 UINT8 SDIOMode; // 774 3 - Default 2 - DDR50\r
450 UINT8 emmcVersion; // 775 0 - 4.41 1 - 4.5\r
451 UINT32 BmBound; // 776 BM Bound\r
452 UINT8 FsaStatus; // 780 0 - Fsa is off, 1- Fsa is on\r
453\r
454 //\r
455 // Board Id\r
456 // This field is for the ASL code to know whether this board is Baylake or Bayley Bay etc\r
457 //\r
458 UINT8 BoardID; // 781\r
459 UINT8 FabID; // 782\r
460 UINT8 OtgMode; // 783 0- OTG disable 1- OTG PCI mode\r
461 UINT8 Stepping; // 784 Stepping\r
462 UINT8 WittEnable; // 785 WITT eanble 0 - disable 1 - enable\r
463\r
464 UINT8 SocStepping; // 786 Soc Stepping infomation\r
465 UINT8 AmbientTripPointChange; // 787 DPTF: Controls whether _ATI changes other participant's trip point(enabled/disabled)\r
466 UINT8 UtsEnable; // 788 Uart Test eanble 0 - disable 1 - enable\r
467 UINT8 DptfReserve; // 789\r
468\r
469 UINT8 SarEnable; // 790\r
470 UINT8 PssDeveice; // 791 PSS Deveice: 0 - None, 1 - Monzax 2K, 2 - Monzax 8K\r
471 UINT8 EDPV; // 792 Check for eDP display device\r
472 UINT32 DIDX; // 793 Device ID for eDP device\r
473 UINT8 MicrosoftIoT; // (794)JP1 pins are for Microsoft IoT project.\r
474 UINT8 RtcBattery; // (795) The Flag of RTC Battery Present.\r
475} EFI_GLOBAL_NVS_AREA;\r
476#pragma pack ()\r
477\r
478//\r
479// Global NVS Area Protocol\r
480//\r
481typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL {\r
482 EFI_GLOBAL_NVS_AREA *Area;\r
483} EFI_GLOBAL_NVS_AREA_PROTOCOL;\r
484\r
485#endif\r
486\r