Add code to identify D0 stepping ValleyView SoC.

[mirror_edk2.git] / Vlv2TbltDevicePkg / Library / PchPlatformLib / PchPlatformLibrary.c

/**\r
\r
Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved\r
                                                                                   \r\r
  This program and the accompanying materials are licensed and made available under\r\r
  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
  The full text of the license may be found at                                     \r\r
  http://opensource.org/licenses/bsd-license.php.                                  \r\r
                                                                                   \r\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
                                                                                   \r\r
\r
  @file\r
  PchPlatformLib.c\r
\r
  @brief\r
  PCH Platform Lib implementation.\r
\r
**/\r
\r
#include "PchPlatformLibrary.h"\r
\r
//\r
// Silicon Steppings\r
//\r
/**\r
  Return Pch stepping type\r
\r
  @param[in] None\r
\r
  @retval PCH_STEPPING            Pch stepping type\r
\r
**/\r
PCH_STEPPING\r
EFIAPI\r
PchStepping (\r
  VOID\r
  )\r
{\r
  UINT8 RevId;\r
\r
  RevId = MmioRead8 (\r
          MmPciAddress (0,\r
            DEFAULT_PCI_BUS_NUMBER_PCH,\r
            PCI_DEVICE_NUMBER_PCH_LPC,\r
            PCI_FUNCTION_NUMBER_PCH_LPC,\r
            R_PCH_LPC_RID_CC)\r
          );\r
\r
  switch (RevId) {\r
    case V_PCH_LPC_RID_0:\r
    case V_PCH_LPC_RID_1:\r
      return PchA0;\r
      break;\r
\r
    case V_PCH_LPC_RID_2:\r
    case V_PCH_LPC_RID_3:\r
      return PchA1;\r
      break;\r
\r
    case V_PCH_LPC_RID_4:\r
    case V_PCH_LPC_RID_5:\r
      return PchB0;\r
      break;\r
\r
    case V_PCH_LPC_RID_6:\r
    case V_PCH_LPC_RID_7:\r
      return PchB1;\r
      break;\r
\r
    case V_PCH_LPC_RID_8:\r
    case V_PCH_LPC_RID_9:\r
      return PchB2;\r
      break;\r
\r
    case V_PCH_LPC_RID_A:\r
    case V_PCH_LPC_RID_B:\r
      return PchB3;\r
      break;\r
\r
    case V_PCH_LPC_RID_C:\r
    case V_PCH_LPC_RID_D:\r
      return PchC0;\r
      break;\r
    \r
    case V_PCH_LPC_RID_E:\r
    case V_PCH_LPC_RID_F:\r
      return PchD0;\r
      break;\r
        \r
    default:\r
      return PchSteppingMax;\r
      break;\r
\r
  }\r
}\r
\r
/**\r
  Determine if PCH is supported\r
\r
  @param[in] None\r
\r
  @retval TRUE                    PCH is supported\r
  @retval FALSE                   PCH is not supported\r
\r
**/\r
BOOLEAN\r
IsPchSupported (\r
  VOID\r
  )\r
{\r
  UINT32  Identifiers;\r
  UINT16  PcuVendorId;\r
  UINT16  PcuDeviceId;\r
\r
  Identifiers = MmioRead32 (\r
                  MmPciAddress (0,\r
                  DEFAULT_PCI_BUS_NUMBER_PCH,\r
                  PCI_DEVICE_NUMBER_PCH_LPC,\r
                  PCI_FUNCTION_NUMBER_PCH_LPC,\r
                  R_PCH_LPC_REG_ID)\r
                );\r
\r
  PcuDeviceId = (UINT16) ((Identifiers & B_PCH_LPC_DEVICE_ID) >> 16);\r
  PcuVendorId = (UINT16) (Identifiers & B_PCH_LPC_VENDOR_ID);\r
\r
  //\r
  // Verify that this is a supported chipset\r
  //\r
  if (PcuVendorId != (UINT16) V_PCH_LPC_VENDOR_ID || !IS_PCH_VLV_LPC_DEVICE_ID (PcuDeviceId)) {\r
    DEBUG ((EFI_D_ERROR, "VLV SC code doesn't support the PcuDeviceId: 0x%04x!\n", PcuDeviceId));\r
    return FALSE;\r
  }\r
  return TRUE;\r
}\r