]> git.proxmox.com Git - mirror_edk2.git/blame - Vlv2TbltDevicePkg/PlatformDxe/Platform.c
projects / mirror_edk2.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Set RTC initial time to be BIOS Release time.
[mirror_edk2.git] / Vlv2TbltDevicePkg / PlatformDxe / Platform.c
CommitLineData
3cbfba02
DW		 1/** @file\r
2\r
d71c25cf
DW		 3 Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>\r
4 \r
5\r
6 This program and the accompanying materials are licensed and made available under\r
7\r
8 the terms and conditions of the BSD License that accompanies this distribution. \r
9\r
10 The full text of the license may be found at \r
11\r
12 http://opensource.org/licenses/bsd-license.php. \r
13\r
14 \r
15\r
16 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
17\r
18 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
19\r
20 \r
21\r
3cbfba02
DW		 22\r
23Module Name:\r
24\r
25\r
26 Platform.c\r
27\r
28Abstract:\r
29\r
30 Platform Initialization Driver.\r
31\r
32\r
33--*/\r
34\r
35#include "PlatformDxe.h"\r
36#include "Platform.h"\r
37#include "PchCommonDefinitions.h"\r
38#include <Protocol/UsbPolicy.h>\r
39#include <Protocol/PchPlatformPolicy.h>\r
40#include <Protocol/TpmMp.h>\r
41#include <Protocol/CpuIo2.h>\r
42#include <Library/S3BootScriptLib.h>\r
43#include <Guid/PciLanInfo.h>\r
44#include <Guid/ItkData.h>\r
45#include <Library/PciLib.h>\r
46#include <PlatformBootMode.h>\r
47#include <Guid/EventGroup.h>\r
48#include <Guid/Vlv2Variable.h>\r
49#include <Protocol/GlobalNvsArea.h>\r
50#include <Protocol/IgdOpRegion.h>\r
51#include <Library/PcdLib.h>\r
52\r
53//\r
54// VLV2 GPIO GROUP OFFSET\r
55//\r
56#define GPIO_SCORE_OFFSET 0x0000\r
57#define GPIO_NCORE_OFFSET 0x1000\r
58#define GPIO_SSUS_OFFSET 0x2000\r
59\r
60typedef struct {\r
61 UINT32 offset;\r
62 UINT32 val;\r
63} CFIO_PNP_INIT;\r
64\r
65GPIO_CONF_PAD_INIT mTB_BL_GpioInitData_SC_TRI_Exit_boot_Service[] =\r
66{\r
67// Pad Name GPIO Number Used As GPO Default Function# INT Capable Interrupt Type PULL H/L MMIO Offset\r
68 GPIO_INIT_ITEM("LPC_CLKOUT0 GPIOC_47 " ,TRISTS ,NA ,F0 , , ,NONE ,0x47),\r
69 GPIO_INIT_ITEM("LPC_CLKOUT1 GPIOC_48 " ,TRISTS ,NA ,F0 , , ,NONE ,0x41),\r
70};\r
71\r
72\r
73EFI_GUID mSystemHiiExportDatabase = EFI_HII_EXPORT_DATABASE_GUID;\r
74EFI_GUID mPlatformDriverGuid = EFI_PLATFORM_DRIVER_GUID;\r
75SYSTEM_CONFIGURATION mSystemConfiguration;\r
76SYSTEM_PASSWORDS mSystemPassword;\r
77EFI_HANDLE mImageHandle;\r
78BOOLEAN mMfgMode = FALSE;\r
79VOID *mDxePlatformStringPack;\r
80UINT32 mPlatformBootMode = PLATFORM_NORMAL_MODE;\r
81extern CHAR16 gItkDataVarName[];\r
82\r
83\r
84EFI_PLATFORM_INFO_HOB mPlatformInfo;\r
85EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo;\r
86EFI_EVENT mReadyToBootEvent;\r
87\r
88UINT8 mSmbusRsvdAddresses[] = PLATFORM_SMBUS_RSVD_ADDRESSES;\r
89UINT8 mNumberSmbusAddress = sizeof( mSmbusRsvdAddresses ) / sizeof( mSmbusRsvdAddresses[0] );\r
90UINT32 mSubsystemVidDid;\r
91UINT32 mSubsystemAudioVidDid;\r
92\r
93UINTN mPciLanCount = 0;\r
94VOID *mPciLanInfo = NULL;\r
95UINTN SpiBase;\r
96\r
97static EFI_SPEAKER_IF_PROTOCOL mSpeakerInterface = {\r
98 ProgramToneFrequency,\r
99 GenerateBeepTone\r
100};\r
101\r
102EFI_USB_POLICY_PROTOCOL mUsbPolicyData = {0};\r
103\r
104\r
105CFIO_PNP_INIT mTB_BL_GpioInitData_SC_TRI_S0ix_Exit_boot_Service[] =\r
106{\r
107 {0x410 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout1_pconf0\r
108 {0x470 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout0_pconf0\r
109 {0x560 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_ilb_serirq_pconf0\r
110 {0x450 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_frameb_pconf0\r
111 {0x480 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkrunb_pconf0\r
112 {0x420 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad3_pconf0\r
113 {0x430 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad2_pconf0\r
114 {0x440 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad1_pconf0\r
115 {0x460 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad0_pconf0\r
116 {0x418 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout1_pad_val\r
117 {0x478 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout0_pad_val\r
118 {0x568 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_ilb_serirq_pad_val\r
119 {0x458 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_frameb_pad_val\r
120 {0x488 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkrunb_pad_val\r
121 {0x428 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad3_pad_val\r
122 {0x438 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad2_pad_val\r
123 {0x448 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad1_pad_val\r
124 {0x468 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad0_pad_val\r
125};\r
126\r
127VOID\r
128EfiOrMem (\r
129 IN VOID *Destination,\r
130 IN VOID *Source,\r
131 IN UINTN Length\r
132 );\r
133\r
134#if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)\r
135STATIC\r
136VOID\r
137InitFirmwareId();\r
138#endif\r
139\r
140\r
141VOID\r
142InitializeClockRouting(\r
143 );\r
144\r
145VOID\r
146InitializeSlotInfo (\r
147 );\r
148\r
149#if defined(SENSOR_INFO_VAR_SUPPORT) && SENSOR_INFO_VAR_SUPPORT != 0\r
150VOID\r
151InitializeSensorInfoVariable (\r
152 );\r
153#endif\r
154\r
155VOID\r
156InitTcoReset (\r
157 );\r
158\r
159VOID\r
160InitExI ();\r
161\r
162VOID\r
163InitItk();\r
164\r
165VOID\r
166InitPlatformBootMode();\r
167\r
168VOID\r
169InitMfgAndConfigModeStateVar();\r
170\r
171VOID\r
172InitPchPlatformPolicy (\r
173 IN EFI_PLATFORM_INFO_HOB *PlatformInfo\r
174 );\r
175\r
176VOID\r
177InitVlvPlatformPolicy (\r
178 );\r
179\r
180VOID\r
181InitSioPlatformPolicy(\r
182 );\r
183\r
184VOID\r
185PchInitBeforeBoot(\r
186 );\r
187\r
188VOID\r
189UpdateDVMTSetup(\r
190 );\r
191\r
192VOID\r
193InitPlatformUsbPolicy (\r
194 VOID\r
195 );\r
196\r
197VOID\r
198InitRC6Policy(\r
199 VOID\r
200 );\r
201\r
202\r
203VOID\r
204TristateLpcGpioConfig (\r
205 IN UINT32 Gpio_Mmio_Offset,\r
206 IN UINT32 Gpio_Pin_Num,\r
207 GPIO_CONF_PAD_INIT* Gpio_Conf_Data\r
208 )\r
209\r
210{\r
211 UINT32 index;\r
212 UINT32 mmio_conf0;\r
213 UINT32 mmio_padval;\r
214 PAD_CONF0 conf0_val;\r
215 PAD_VAL pad_val;\r
216\r
217 //\r
218 // GPIO WELL -- Memory base registers\r
219 //\r
220\r
221 //\r
222 // A0 BIOS Spec doesn't mention it although X0 does. comment out now.\r
223 // GPIO write 0x01001002 to IOBASE + Gpio_Mmio_Offset + 0x0900\r
224 //\r
225\r
226 for(index=0; index < Gpio_Pin_Num; index++)\r
227 {\r
228 //\r
229 // Calculate the MMIO Address for specific GPIO pin CONF0 register pointed by index.\r
230 //\r
231 mmio_conf0 = IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_CONF0 + Gpio_Conf_Data[index].offset * 16;\r
232 mmio_padval= IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_VAL + Gpio_Conf_Data[index].offset * 16;\r
233\r
234#ifdef EFI_DEBUG\r
235 DEBUG ((EFI_D_INFO, "%s, ", Gpio_Conf_Data[index].pad_name));\r
236\r
237#endif\r
238 DEBUG ((EFI_D_INFO, "Usage = %d, Func# = %d, IntType = %d, Pull Up/Down = %d, MMIO Base = 0x%08x, ",\r
239 Gpio_Conf_Data[index].usage,\r
240 Gpio_Conf_Data[index].func,\r
241 Gpio_Conf_Data[index].int_type,\r
242 Gpio_Conf_Data[index].pull,\r
243 mmio_conf0));\r
244\r
245 //\r
246 // Step 1: PadVal Programming\r
247 //\r
248 pad_val.dw = MmioRead32(mmio_padval);\r
249\r
250 //\r
251 // Config PAD_VAL only for GPIO (Non-Native) Pin\r
252 //\r
253 if(Native != Gpio_Conf_Data[index].usage)\r
254 {\r
255 pad_val.dw &= ~0x6; // Clear bits 1:2\r
256 pad_val.dw |= (Gpio_Conf_Data[index].usage & 0x6); // Set bits 1:2 according to PadVal\r
257\r
258 //\r
259 // set GPO default value\r
260 //\r
261 if(Gpio_Conf_Data[index].usage == GPO && Gpio_Conf_Data[index].gpod4 != NA)\r
262 {\r
263 pad_val.r.pad_val = Gpio_Conf_Data[index].gpod4;\r
264 }\r
265 }\r
266\r
267\r
268 DEBUG ((EFI_D_INFO, "Set PAD_VAL = 0x%08x, ", pad_val.dw));\r
269\r
270 MmioWrite32(mmio_padval, pad_val.dw);\r
271\r
272 //\r
273 // Step 2: CONF0 Programming\r
274 // Read GPIO default CONF0 value, which is assumed to be default value after reset.\r
275 //\r
276 conf0_val.dw = MmioRead32(mmio_conf0);\r
277\r
278 //\r
279 // Set Function #\r
280 //\r
281 conf0_val.r.Func_Pin_Mux = Gpio_Conf_Data[index].func;\r
282\r
283 if(GPO == Gpio_Conf_Data[index].usage)\r
284 {\r
285 //\r
286 // If used as GPO, then internal pull need to be disabled\r
287 //\r
288 conf0_val.r.Pull_assign = 0; // Non-pull\r
289 }\r
290 else\r
291 {\r
292 //\r
293 // Set PullUp / PullDown\r
294 //\r
295 if(P_20K_H == Gpio_Conf_Data[index].pull)\r
296 {\r
297 conf0_val.r.Pull_assign = 0x1; // PullUp\r
298 conf0_val.r.Pull_strength = 0x2;// 20K\r
299 }\r
300 else if(P_20K_L == Gpio_Conf_Data[index].pull)\r
301 {\r
302 conf0_val.r.Pull_assign = 0x2; // PullDown\r
303 conf0_val.r.Pull_strength = 0x2;// 20K\r
304 }\r
305 else if(P_NONE == Gpio_Conf_Data[index].pull)\r
306 {\r
307 conf0_val.r.Pull_assign = 0; // Non-pull\r
308 }\r
309 else\r
310 {\r
311 ASSERT(FALSE); // Invalid value\r
312 }\r
313 }\r
314\r
315 //\r
316 // Set INT Trigger Type\r
317 //\r
318 conf0_val.dw &= ~0x0f000000; // Clear bits 27:24\r
319\r
320 //\r
321 // Set INT Trigger Type\r
322 //\r
323 if(TRIG_ == Gpio_Conf_Data[index].int_type)\r
324 {\r
325 //\r
326 // Interrupt not capable, clear bits 27:24\r
327 //\r
328 }\r
329 else\r
330 {\r
331 conf0_val.dw |= (Gpio_Conf_Data[index].int_type & 0x0f)<<24;\r
332 }\r
333\r
334 DEBUG ((EFI_D_INFO, "Set CONF0 = 0x%08x\n", conf0_val.dw));\r
335\r
336 //\r
337 // Write back the targeted GPIO config value according to platform (board) GPIO setting\r
338 //\r
339 MmioWrite32 (mmio_conf0, conf0_val.dw);\r
340 }\r
341\r
342 // A0 BIOS Spec doesn't mention it although X0 does. comment out now.\r
343 // GPIO SCORE write 0x01001002 to IOBASE + 0x0900\r
344 //\r
345}\r
346\r
347VOID\r
348EFIAPI\r
349SpiBiosProtectionFunction(\r
350 EFI_EVENT Event,\r
351 VOID *Context\r
352 )\r
353{\r
354\r
355 UINTN mPciD31F0RegBase;\r
356 UINTN BiosFlaLower = 0;\r
357 UINTN BiosFlaLimit = 0x7fffff;\r
358\r
359 BiosFlaLower = PcdGet32(PcdFlashMicroCodeAddress)-PcdGet32(PcdFlashAreaBaseAddress);\r
360\r
361\r
362 mPciD31F0RegBase = MmPciAddress (0,\r
363 DEFAULT_PCI_BUS_NUMBER_PCH,\r
364 PCI_DEVICE_NUMBER_PCH_LPC,\r
365 PCI_FUNCTION_NUMBER_PCH_LPC,\r
366 0\r
367 );\r
368 SpiBase = MmioRead32(mPciD31F0RegBase + R_PCH_LPC_SPI_BASE) & B_PCH_LPC_SPI_BASE_BAR;\r
369\r
370 //\r
371 //Set SMM_BWP, WPD and LE bit\r
372 //\r
373 MmioOr32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8) B_PCH_SPI_BCR_SMM_BWP);\r
374 MmioAnd32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8)(~B_PCH_SPI_BCR_BIOSWE));\r
375 MmioOr32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8) B_PCH_SPI_BCR_BLE);\r
376\r
377 //\r
378 //First check if FLOCKDN or PR0FLOCKDN is set. No action if either of them set already.\r
379 //\r
380 if( (MmioRead16(SpiBase + R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FLOCKDN) != 0 ||\r
381 (MmioRead32(SpiBase + R_PCH_SPI_IND_LOCK)& B_PCH_SPI_IND_LOCK_PR0) != 0) {\r
382 //\r
383 //Already locked. we could take no action here\r
384 //\r
385 DEBUG((EFI_D_INFO, "PR0 already locked down. Stop configuring PR0.\n"));\r
386 return;\r
387 }\r
388\r
389 //\r
390 //Set PR0\r
391 //\r
392 MmioOr32((UINTN)(SpiBase + R_PCH_SPI_PR0),\r
393 B_PCH_SPI_PR0_RPE|B_PCH_SPI_PR0_WPE|\\r
394 (B_PCH_SPI_PR0_PRB_MASK&(BiosFlaLower>>12))|(B_PCH_SPI_PR0_PRL_MASK&(BiosFlaLimit>>12)<<16));\r
395\r
396 //\r
397 //Lock down PR0\r
398 //\r
399 MmioOr16 ((UINTN) (SpiBase + R_PCH_SPI_HSFS), (UINT16) (B_PCH_SPI_HSFS_FLOCKDN));\r
400\r
401 //\r
402 // Verify if it's really locked.\r
403 //\r
404 if ((MmioRead16 (SpiBase + R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FLOCKDN) == 0) {\r
405 DEBUG((EFI_D_ERROR, "Failed to lock down PR0.\n"));\r
406 }\r
407\r
408 return;\r
409\r
410}\r
411\r
412VOID\r
413EFIAPI\r
414InitPciDevPME (\r
415 EFI_EVENT Event,\r
416 VOID *Context\r
417 )\r
418{\r
419 UINTN VarSize;\r
420 EFI_STATUS Status;\r
421\r
422 VarSize = sizeof(SYSTEM_CONFIGURATION);\r
423 Status = gRT->GetVariable(\r
424 NORMAL_SETUP_NAME,\r
425 &gEfiNormalSetupGuid,\r
426 NULL,\r
427 &VarSize,\r
428 &mSystemConfiguration\r
429 );\r
430\r
431 //\r
432 //Program HDA PME_EN\r
433 //\r
434 PchAzaliaPciCfg32Or (R_PCH_HDA_PCS, B_PCH_HDA_PCS_PMEE);\r
435\r
436 //\r
437 //Program SATA PME_EN\r
438 //\r
439 PchSataPciCfg32Or (R_PCH_SATA_PMCS, B_PCH_SATA_PMCS_PMEE);\r
440\r
441 DEBUG ((EFI_D_INFO, "InitPciDevPME mSystemConfiguration.EhciPllCfgEnable = 0x%x \n",mSystemConfiguration.EhciPllCfgEnable));\r
442 if (mSystemConfiguration.EhciPllCfgEnable != 1) {\r
443 //\r
444 //Program EHCI PME_EN\r
445 //\r
446 PchMmPci32Or (\r
447 0,\r
448 0,\r
449 PCI_DEVICE_NUMBER_PCH_USB,\r
450 PCI_FUNCTION_NUMBER_PCH_EHCI,\r
451 R_PCH_EHCI_PWR_CNTL_STS,\r
452 B_PCH_EHCI_PWR_CNTL_STS_PME_EN\r
453 );\r
454 }\r
455 {\r
456 UINTN EhciPciMmBase;\r
457 UINT32 Buffer32 = 0;\r
458\r
459 EhciPciMmBase = MmPciAddress (0,\r
460 0,\r
461 PCI_DEVICE_NUMBER_PCH_USB,\r
462 PCI_FUNCTION_NUMBER_PCH_EHCI,\r
463 0\r
464 );\r
465 DEBUG ((EFI_D_INFO, "ConfigureAdditionalPm() EhciPciMmBase = 0x%x \n",EhciPciMmBase));\r
466 Buffer32 = MmioRead32(EhciPciMmBase + R_PCH_EHCI_PWR_CNTL_STS);\r
467 DEBUG ((EFI_D_INFO, "ConfigureAdditionalPm() R_PCH_EHCI_PWR_CNTL_STS = 0x%x \n",Buffer32));\r
468 }\r
469}\r
470\r
471#if defined SUPPORT_LVDS_DISPLAY && SUPPORT_LVDS_DISPLAY\r
472\r
473#endif\r
474\r
475\r
476EFI_STATUS\r
477EFIAPI\r
478TristateLpcGpioS0i3Config (\r
479 UINT32 Gpio_Mmio_Offset,\r
480 UINT32 Gpio_Pin_Num,\r
481 CFIO_PNP_INIT* Gpio_Conf_Data\r
482 )\r
483{\r
484\r
485 UINT32 index;\r
486 UINT32 mmio_reg;\r
487 UINT32 mmio_val;\r
488\r
489 DEBUG ((DEBUG_INFO, "TristateLpcGpioS0i3Config\n"));\r
490\r
491 for(index=0; index < Gpio_Pin_Num; index++)\r
492 {\r
493 mmio_reg = IO_BASE_ADDRESS + Gpio_Mmio_Offset + Gpio_Conf_Data[index].offset;\r
494\r
495 MmioWrite32(mmio_reg, Gpio_Conf_Data[index].val);\r
496 mmio_val = 0;\r
497 mmio_val = MmioRead32(mmio_reg);\r
498\r
499 DEBUG ((EFI_D_INFO, "Set MMIO=0x%08x PAD_VAL = 0x%08x,\n", mmio_reg, mmio_val));\r
500 }\r
501\r
502 return EFI_SUCCESS;\r
503}\r
504\r
505\r
506EFI_BOOT_SCRIPT_SAVE_PROTOCOL *mBootScriptSave;\r
507\r
508/**\r
509 Event Notification during exit boot service to enabel ACPI mode\r
510\r
511 Disable SW SMI Timer, SMI from USB & Intel Specific USB 2\r
512\r
513 Clear all ACPI event status and disable all ACPI events\r
514 Disable PM sources except power button\r
515 Clear status bits\r
516\r
517 Guarantee day-of-month alarm is invalid (ACPI 5.0 Section 4.8.2.4 "Real Time Clock Alarm")\r
518\r
519 Update EC to disable SMI and enable SCI\r
520\r
521 Enable SCI\r
522\r
523 Enable PME_B0_EN in GPE0a_EN\r
524\r
525 @param Event - EFI Event Handle\r
526 @param Context - Pointer to Notify Context\r
527\r
528 @retval Nothing\r
529\r
530**/\r
531VOID\r
532EFIAPI\r
533EnableAcpiCallback (\r
534 IN EFI_EVENT Event,\r
535 IN VOID *Context\r
536 )\r
537{\r
538 UINT32 RegData32;\r
539 UINT16 Pm1Cnt;\r
540 UINT16 AcpiBase;\r
541 UINT32 Gpe0aEn;\r
542\r
543 AcpiBase = MmioRead16 (\r
544 PchPciDeviceMmBase (DEFAULT_PCI_BUS_NUMBER_PCH,\r
545 PCI_DEVICE_NUMBER_PCH_LPC,\r
546 PCI_FUNCTION_NUMBER_PCH_LPC) + R_PCH_LPC_ACPI_BASE\r
547 ) & B_PCH_LPC_ACPI_BASE_BAR;\r
548\r
549 DEBUG ((EFI_D_INFO, "EnableAcpiCallback: AcpiBase = %x\n", AcpiBase));\r
550\r
551 //\r
552 // Disable SW SMI Timer, SMI from USB & Intel Specific USB 2\r
553 //\r
554 RegData32 = IoRead32(AcpiBase + R_PCH_SMI_EN);\r
555 RegData32 &= ~(B_PCH_SMI_EN_SWSMI_TMR | B_PCH_SMI_EN_LEGACY_USB2 | B_PCH_SMI_EN_INTEL_USB2);\r
556 IoWrite32(AcpiBase + R_PCH_SMI_EN, RegData32);\r
557\r
558 RegData32 = IoRead32(AcpiBase + R_PCH_SMI_STS);\r
559 RegData32 |= B_PCH_SMI_STS_SWSMI_TMR;\r
560 IoWrite32(AcpiBase + R_PCH_SMI_STS, RegData32);\r
561\r
562 //\r
563 // Disable PM sources except power button\r
564 // power button is enabled only for PCAT. Disabled it on Tablet platform\r
565 //\r
566\r
567 IoWrite16(AcpiBase + R_PCH_ACPI_PM1_EN, B_PCH_ACPI_PM1_EN_PWRBTN);\r
568 IoWrite16(AcpiBase + R_PCH_ACPI_PM1_STS, 0xffff);\r
569\r
570 //\r
571 // Guarantee day-of-month alarm is invalid (ACPI 5.0 Section 4.8.2.4 "Real Time Clock Alarm")\r
572 // Clear Status D reg VM bit, Date of month Alarm to make Data in CMOS RAM is no longer Valid\r
573 //\r
574 IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_D);\r
575 IoWrite8 (PCAT_RTC_DATA_REGISTER, 0x0);\r
576\r
577 RegData32 = IoRead32(AcpiBase + R_PCH_ALT_GP_SMI_EN);\r
578 RegData32 &= ~(BIT7);\r
579 IoWrite32((AcpiBase + R_PCH_ALT_GP_SMI_EN), RegData32);\r
580\r
581 //\r
582 // Enable SCI\r
583 //\r
584 Pm1Cnt = IoRead16(AcpiBase + R_PCH_ACPI_PM1_CNT);\r
585 Pm1Cnt |= B_PCH_ACPI_PM1_CNT_SCI_EN;\r
586 IoWrite16(AcpiBase + R_PCH_ACPI_PM1_CNT, Pm1Cnt);\r
587\r
588 IoWrite8(0x80, 0xA0); //SW_SMI_ACPI_ENABLE\r
589\r
590 //\r
591 // Enable PME_B0_EN in GPE0a_EN\r
592 // Caution: Enable PME_B0_EN must be placed after enabling SCI.\r
593 // Otherwise, USB PME could not be handled as SMI event since no handler is there.\r
594 //\r
595 Gpe0aEn = IoRead32 (AcpiBase + R_PCH_ACPI_GPE0a_EN);\r
596 Gpe0aEn |= B_PCH_ACPI_GPE0a_EN_PME_B0;\r
597 IoWrite32(AcpiBase + R_PCH_ACPI_GPE0a_EN, Gpe0aEn);\r
598\r
599}\r
600\r
601/**\r
602\r
603 Routine Description:\r
604\r
605 This is the standard EFI driver point for the Driver. This\r
606 driver is responsible for setting up any platform specific policy or\r
607 initialization information.\r
608\r
609 @param ImageHandle Handle for the image of this driver.\r
610 @param SystemTable Pointer to the EFI System Table.\r
611\r
612 @retval EFI_SUCCESS Policy decisions set.\r
613\r
614**/\r
615EFI_STATUS\r
616EFIAPI\r
617InitializePlatform (\r
618 IN EFI_HANDLE ImageHandle,\r
619 IN EFI_SYSTEM_TABLE *SystemTable\r
620 )\r
621{\r
622 EFI_STATUS Status;\r
623 UINTN VarSize;\r
624 EFI_HANDLE Handle = NULL;\r
3cbfba02 625 EFI_EVENT mEfiExitBootServicesEvent;\r
d71c25cf
DW		 626 EFI_EVENT RtcEvent;\r
627 VOID *RtcCallbackReg = NULL;\r
628 \r
629 mImageHandle = ImageHandle;\r
3cbfba02
DW		 630\r
631 Status = gBS->InstallProtocolInterface (\r
632 &Handle,\r
633 &gEfiSpeakerInterfaceProtocolGuid,\r
634 EFI_NATIVE_INTERFACE,\r
635 &mSpeakerInterface\r
636 );\r
637\r
638 Status = gBS->LocateProtocol (\r
639 &gEfiPciRootBridgeIoProtocolGuid,\r
640 NULL,\r
641 (VOID **) &mPciRootBridgeIo\r
642 );\r
643 ASSERT_EFI_ERROR (Status);\r
644\r
645 VarSize = sizeof(EFI_PLATFORM_INFO_HOB);\r
646 Status = gRT->GetVariable(\r
647 L"PlatformInfo",\r
648 &gEfiVlv2VariableGuid,\r
649 NULL,\r
650 &VarSize,\r
651 &mPlatformInfo\r
652 );\r
653\r
654 //\r
655 // Initialize Product Board ID variable\r
656 //\r
657 InitMfgAndConfigModeStateVar();\r
658 InitPlatformBootMode();\r
659\r
660 //\r
661 // Install Observable protocol\r
662 //\r
663 InitializeObservableProtocol();\r
664\r
665\r
666 VarSize = sizeof(SYSTEM_CONFIGURATION);\r
667 Status = gRT->GetVariable(\r
668 NORMAL_SETUP_NAME,\r
669 &gEfiNormalSetupGuid,\r
670 NULL,\r
671 &VarSize,\r
672 &mSystemConfiguration\r
673 );\r
674\r
675\r
676 Status = EfiCreateEventReadyToBootEx (\r
677 TPL_CALLBACK,\r
678 ReadyToBootFunction,\r
679 NULL,\r
680 &mReadyToBootEvent\r
681 );\r
682\r
683 //\r
684 // Create a ReadyToBoot Event to run the PME init process\r
685 //\r
686 Status = EfiCreateEventReadyToBootEx (\r
687 TPL_CALLBACK,\r
688 InitPciDevPME,\r
689 NULL,\r
690 &mReadyToBootEvent\r
691 );\r
692 //\r
693 // Create a ReadyToBoot Event to run enable PR0 and lock down\r
694 //\r
695 if(mSystemConfiguration.SpiRwProtect==1) {\r
696 Status = EfiCreateEventReadyToBootEx (\r
697 TPL_CALLBACK,\r
698 SpiBiosProtectionFunction,\r
699 NULL,\r
700 &mReadyToBootEvent\r
701 );\r
702 }\r
703\r
704 ReportStatusCodeEx (\r
705 EFI_PROGRESS_CODE,\r
706 EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP1,\r
707 0,\r
708 &gEfiCallerIdGuid,\r
709 NULL,\r
710 NULL,\r
711 0\r
712 );\r
713\r
714#if defined(SENSOR_INFO_VAR_SUPPORT) && SENSOR_INFO_VAR_SUPPORT != 0\r
715 //\r
716 // Initialize Sensor Info variable\r
717 //\r
718 InitializeSensorInfoVariable();\r
719#endif\r
720 InitPchPlatformPolicy(&mPlatformInfo);\r
721 InitVlvPlatformPolicy();\r
722\r
723 //\r
724 // Add usb policy\r
725 //\r
726 InitPlatformUsbPolicy();\r
727 InitSioPlatformPolicy();\r
728 InitializeClockRouting();\r
729 InitializeSlotInfo();\r
730 InitTcoReset();\r
731\r
732 //\r
733 //Init ExI\r
734 //\r
735 InitExI();\r
736\r
737 ReportStatusCodeEx (\r
738 EFI_PROGRESS_CODE,\r
739 EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP2,\r
740 0,\r
741 &gEfiCallerIdGuid,\r
742 NULL,\r
743 NULL,\r
744 0\r
745 );\r
746\r
747 //\r
748 // Install PCI Bus Driver Hook\r
749 //\r
750 PciBusDriverHook();\r
751\r
752 InitItk();\r
753\r
754 ReportStatusCodeEx (\r
755 EFI_PROGRESS_CODE,\r
756 EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP3,\r
757 0,\r
758 &gEfiCallerIdGuid,\r
759 NULL,\r
760 NULL,\r
761 0\r
762 );\r
763\r
764\r
765 //\r
766 // Initialize Password States and Callbacks\r
767 //\r
768 PchInitBeforeBoot();\r
769\r
770#if defined SUPPORT_LVDS_DISPLAY && SUPPORT_LVDS_DISPLAY\r
771\r
772#endif\r
773\r
774#if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)\r
775 //\r
776 // Re-write Firmware ID if it is changed\r
777 //\r
778 InitFirmwareId();\r
779#endif\r
780\r
781 ReportStatusCodeEx (\r
782 EFI_PROGRESS_CODE,\r
783 EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP4,\r
784 0,\r
785 &gEfiCallerIdGuid,\r
786 NULL,\r
787 NULL,\r
788 0\r
789 );\r
790\r
791\r
792 Status = gBS->CreateEventEx (\r
793 EVT_NOTIFY_SIGNAL,\r
794 TPL_NOTIFY,\r
795 EnableAcpiCallback,\r
796 NULL,\r
797 &gEfiEventExitBootServicesGuid,\r
798 &mEfiExitBootServicesEvent\r
799 );\r
800\r
d71c25cf
DW		 801 //\r
802 // Adjust RTC deafult time to be BIOS-built time.\r
803 //\r
804 Status = gBS->CreateEvent (\r
805 EVT_NOTIFY_SIGNAL,\r
806 TPL_CALLBACK,\r
807 AdjustDefaultRtcTimeCallback,\r
808 NULL,\r
809 &RtcEvent\r
810 );\r
811 if (!EFI_ERROR (Status)) {\r
812 Status = gBS->RegisterProtocolNotify (\r
813 &gExitPmAuthProtocolGuid,\r
814 RtcEvent,\r
815 &RtcCallbackReg\r
816 );\r
3cbfba02 817\r
d71c25cf 818 }\r
3cbfba02
DW		 819\r
820 return EFI_SUCCESS;\r
821}\r
822\r
823/**\r
824 Source Or Destination with Length bytes.\r
825\r
826 @param[in] Destination Target memory\r
827 @param[in] Source Source memory\r
828 @param[in] Length Number of bytes\r
829\r
830 @retval None\r
831\r
832**/\r
833VOID\r
834EfiOrMem (\r
835 IN VOID *Destination,\r
836 IN VOID *Source,\r
837 IN UINTN Length\r
838 )\r
839{\r
840 CHAR8 *Destination8;\r
841 CHAR8 *Source8;\r
842\r
843 if (Source < Destination) {\r
844 Destination8 = (CHAR8 *) Destination + Length - 1;\r
845 Source8 = (CHAR8 *) Source + Length - 1;\r
846 while (Length--) {\r
847 *(Destination8--) |= *(Source8--);\r
848 }\r
849 } else {\r
850 Destination8 = (CHAR8 *) Destination;\r
851 Source8 = (CHAR8 *) Source;\r
852 while (Length--) {\r
853 *(Destination8++) |= *(Source8++);\r
854 }\r
855 }\r
856}\r
857\r
858VOID\r
859PchInitBeforeBoot()\r
860{\r
861 //\r
862 // Saved SPI Opcode menu to fix EFI variable unable to write after S3 resume.\r
863 //\r
864 S3BootScriptSaveMemWrite (\r
865 EfiBootScriptWidthUint32,\r
866 (UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU0)),\r
867 1,\r
868 (VOID *)(UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU0)));\r
869\r
870 S3BootScriptSaveMemWrite (\r
871 EfiBootScriptWidthUint32,\r
872 (UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU1)),\r
873 1,\r
874 (VOID *)(UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU1)));\r
875\r
876 S3BootScriptSaveMemWrite (\r
877 EfiBootScriptWidthUint16,\r
878 (UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_OPTYPE),\r
879 1,\r
880 (VOID *)(UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_OPTYPE));\r
881\r
882 S3BootScriptSaveMemWrite (\r
883 EfiBootScriptWidthUint16,\r
884 (UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_PREOP),\r
885 1,\r
886 (VOID *)(UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_PREOP));\r
887\r
888 //\r
889 // Saved MTPMC_1 for S3 resume.\r
890 //\r
891 S3BootScriptSaveMemWrite (\r
892 EfiBootScriptWidthUint32,\r
893 (UINTN)(PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1),\r
894 1,\r
895 (VOID *)(UINTN)(PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1));\r
896 return;\r
897}\r
898\r
899VOID\r
900EFIAPI\r
901ReadyToBootFunction (\r
902 EFI_EVENT Event,\r
903 VOID *Context\r
904 )\r
905{\r
906 EFI_STATUS Status;\r
907 EFI_ISA_ACPI_PROTOCOL *IsaAcpi;\r
908 EFI_ISA_ACPI_DEVICE_ID IsaDevice;\r
909 UINTN Size;\r
910 UINT16 State;\r
911 EFI_TPM_MP_DRIVER_PROTOCOL *TpmMpDriver;\r
912 EFI_CPU_IO_PROTOCOL *CpuIo;\r
913 UINT8 Data;\r
914 UINT8 ReceiveBuffer [64];\r
915 UINT32 ReceiveBufferSize;\r
916\r
917 UINT8 TpmForceClearCommand [] = {0x00, 0xC1,\r
918 0x00, 0x00, 0x00, 0x0A,\r
919 0x00, 0x00, 0x00, 0x5D};\r
920 UINT8 TpmPhysicalPresenceCommand [] = {0x00, 0xC1,\r
921 0x00, 0x00, 0x00, 0x0C,\r
922 0x40, 0x00, 0x00, 0x0A,\r
923 0x00, 0x00};\r
924 UINT8 TpmPhysicalDisableCommand [] = {0x00, 0xC1,\r
925 0x00, 0x00, 0x00, 0x0A,\r
926 0x00, 0x00, 0x00, 0x70};\r
927 UINT8 TpmPhysicalEnableCommand [] = {0x00, 0xC1,\r
928 0x00, 0x00, 0x00, 0x0A,\r
929 0x00, 0x00, 0x00, 0x6F};\r
930 UINT8 TpmPhysicalSetDeactivatedCommand [] = {0x00, 0xC1,\r
931 0x00, 0x00, 0x00, 0x0B,\r
932 0x00, 0x00, 0x00, 0x72,\r
933 0x00};\r
934 UINT8 TpmSetOwnerInstallCommand [] = {0x00, 0xC1,\r
935 0x00, 0x00, 0x00, 0x0B,\r
936 0x00, 0x00, 0x00, 0x71,\r
937 0x00};\r
938\r
939 Size = sizeof(UINT16);\r
940 Status = gRT->GetVariable (\r
941 VAR_EQ_FLOPPY_MODE_DECIMAL_NAME,\r
942 &gEfiNormalSetupGuid,\r
943 NULL,\r
944 &Size,\r
945 &State\r
946 );\r
947\r
948 //\r
949 // Disable Floppy Controller if needed\r
950 //\r
951 Status = gBS->LocateProtocol (&gEfiIsaAcpiProtocolGuid, NULL, (VOID **) &IsaAcpi);\r
952 if (!EFI_ERROR(Status) && (State == 0x00)) {\r
953 IsaDevice.HID = EISA_PNP_ID(0x604);\r
954 IsaDevice.UID = 0;\r
955 Status = IsaAcpi->EnableDevice(IsaAcpi, &IsaDevice, FALSE);\r
956 }\r
957\r
958 //\r
959 // save LAN info to a variable\r
960 //\r
961 if (NULL != mPciLanInfo) {\r
962 gRT->SetVariable (\r
963 L"PciLanInfo",\r
964 &gEfiPciLanInfoGuid,\r
965 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,\r
966 mPciLanCount * sizeof(PCI_LAN_INFO),\r
967 mPciLanInfo\r
968 );\r
969 }\r
970\r
971 if (NULL != mPciLanInfo) {\r
972 gBS->FreePool (mPciLanInfo);\r
973 mPciLanInfo = NULL;\r
974 }\r
975 \r
976\r
977 //\r
978 // Handle ACPI OS TPM requests here\r
979 //\r
980 Status = gBS->LocateProtocol (\r
981 &gEfiCpuIoProtocolGuid,\r
982 NULL,\r
983 (VOID **)&CpuIo\r
984 );\r
985 Status = gBS->LocateProtocol (\r
986 &gEfiTpmMpDriverProtocolGuid,\r
987 NULL,\r
988 (VOID **)&TpmMpDriver\r
989 );\r
990 if (!EFI_ERROR (Status))\r
991 {\r
992 Data = ReadCmosBank1Byte (CpuIo, ACPI_TPM_REQUEST);\r
993\r
994 //\r
995 // Clear pending ACPI TPM request indicator\r
996 //\r
997 WriteCmosBank1Byte (CpuIo, ACPI_TPM_REQUEST, 0x00);\r
998 if (Data != 0)\r
999 {\r
1000 WriteCmosBank1Byte (CpuIo, ACPI_TPM_LAST_REQUEST, Data);\r
1001\r
1002 //\r
1003 // Assert Physical Presence for these commands\r
1004 //\r
1005 TpmPhysicalPresenceCommand [11] = 0x20;\r
1006 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1007 Status = TpmMpDriver->Transmit (\r
1008 TpmMpDriver, TpmPhysicalPresenceCommand,\r
1009 sizeof (TpmPhysicalPresenceCommand),\r
1010 ReceiveBuffer, &ReceiveBufferSize\r
1011 );\r
1012 //\r
1013 // PF PhysicalPresence = TRUE\r
1014 //\r
1015 TpmPhysicalPresenceCommand [11] = 0x08;\r
1016 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1017 Status = TpmMpDriver->Transmit (\r
1018 TpmMpDriver, TpmPhysicalPresenceCommand,\r
1019 sizeof (TpmPhysicalPresenceCommand),\r
1020 ReceiveBuffer,\r
1021 &ReceiveBufferSize\r
1022 );\r
1023 if (Data == 0x01)\r
1024 {\r
1025 //\r
1026 // TPM_PhysicalEnable\r
1027 //\r
1028 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1029 Status = TpmMpDriver->Transmit (\r
1030 TpmMpDriver, TpmPhysicalEnableCommand,\r
1031 sizeof (TpmPhysicalEnableCommand),\r
1032 ReceiveBuffer, &ReceiveBufferSize\r
1033 );\r
1034 }\r
1035 if (Data == 0x02)\r
1036 {\r
1037 //\r
1038 // TPM_PhysicalDisable\r
1039 //\r
1040 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1041 Status = TpmMpDriver->Transmit (\r
1042 TpmMpDriver, TpmPhysicalDisableCommand,\r
1043 sizeof (TpmPhysicalDisableCommand),\r
1044 ReceiveBuffer,\r
1045 &ReceiveBufferSize\r
1046 );\r
1047 }\r
1048 if (Data == 0x03)\r
1049 {\r
1050 //\r
1051 // TPM_PhysicalSetDeactivated=FALSE\r
1052 //\r
1053 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1054 TpmPhysicalSetDeactivatedCommand [10] = 0x00;\r
1055 Status = TpmMpDriver->Transmit (\r
1056 TpmMpDriver,\r
1057 TpmPhysicalSetDeactivatedCommand,\r
1058 sizeof (TpmPhysicalSetDeactivatedCommand),\r
1059 ReceiveBuffer, &ReceiveBufferSize\r
1060 );\r
1061 gRT->ResetSystem (EfiResetWarm, EFI_SUCCESS, 0, NULL);\r
1062 }\r
1063 if (Data == 0x04)\r
1064 {\r
1065 //\r
1066 // TPM_PhysicalSetDeactivated=TRUE\r
1067 //\r
1068 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1069 TpmPhysicalSetDeactivatedCommand [10] = 0x01;\r
1070 Status = TpmMpDriver->Transmit (\r
1071 TpmMpDriver,\r
1072 TpmPhysicalSetDeactivatedCommand,\r
1073 sizeof (TpmPhysicalSetDeactivatedCommand),\r
1074 ReceiveBuffer,\r
1075 &ReceiveBufferSize\r
1076 );\r
1077 gRT->ResetSystem (\r
1078 EfiResetWarm,\r
1079 EFI_SUCCESS,\r
1080 0,\r
1081 NULL\r
1082 );\r
1083 }\r
1084 if (Data == 0x05)\r
1085 {\r
1086 //\r
1087 // TPM_ForceClear\r
1088 //\r
1089 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1090 Status = TpmMpDriver->Transmit (\r
1091 TpmMpDriver,\r
1092 TpmForceClearCommand,\r
1093 sizeof (TpmForceClearCommand),\r
1094 ReceiveBuffer,\r
1095 &ReceiveBufferSize\r
1096 );\r
1097 gRT->ResetSystem (\r
1098 EfiResetWarm,\r
1099 EFI_SUCCESS,\r
1100 0,\r
1101 NULL\r
1102 );\r
1103 }\r
1104 if (Data == 0x06)\r
1105 {\r
1106 //\r
1107 // TPM_PhysicalEnable\r
1108 //\r
1109 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1110 Status = TpmMpDriver->Transmit (\r
1111 TpmMpDriver,\r
1112 TpmPhysicalEnableCommand,\r
1113 sizeof (TpmPhysicalEnableCommand),\r
1114 ReceiveBuffer,\r
1115 &ReceiveBufferSize\r
1116 );\r
1117 //\r
1118 // TPM_PhysicalSetDeactivated=FALSE\r
1119 //\r
1120 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1121 TpmPhysicalSetDeactivatedCommand [10] = 0x00;\r
1122 Status = TpmMpDriver->Transmit (\r
1123 TpmMpDriver,\r
1124 TpmPhysicalSetDeactivatedCommand,\r
1125 sizeof (TpmPhysicalSetDeactivatedCommand),\r
1126 ReceiveBuffer,\r
1127 &ReceiveBufferSize\r
1128 );\r
1129 gRT->ResetSystem (\r
1130 EfiResetWarm,\r
1131 EFI_SUCCESS,\r
1132 0,\r
1133 NULL\r
1134 );\r
1135 }\r
1136 if (Data == 0x07)\r
1137 {\r
1138 //\r
1139 // TPM_PhysicalSetDeactivated=TRUE\r
1140 //\r
1141 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1142 TpmPhysicalSetDeactivatedCommand [10] = 0x01;\r
1143 Status = TpmMpDriver->Transmit (\r
1144 TpmMpDriver,\r
1145 TpmPhysicalSetDeactivatedCommand,\r
1146 sizeof (TpmPhysicalSetDeactivatedCommand),\r
1147 ReceiveBuffer,\r
1148 &ReceiveBufferSize\r
1149 );\r
1150 //\r
1151 // TPM_PhysicalDisable\r
1152 //\r
1153 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1154 Status = TpmMpDriver->Transmit (\r
1155 TpmMpDriver,\r
1156 TpmPhysicalDisableCommand,\r
1157 sizeof (TpmPhysicalDisableCommand),\r
1158 ReceiveBuffer,\r
1159 &ReceiveBufferSize\r
1160 );\r
1161 gRT->ResetSystem (\r
1162 EfiResetWarm,\r
1163 EFI_SUCCESS,\r
1164 0,\r
1165 NULL\r
1166 );\r
1167 }\r
1168 if (Data == 0x08)\r
1169 {\r
1170 //\r
1171 // TPM_SetOwnerInstall=TRUE\r
1172 //\r
1173 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1174 TpmSetOwnerInstallCommand [10] = 0x01;\r
1175 Status = TpmMpDriver->Transmit (\r
1176 TpmMpDriver,\r
1177 TpmSetOwnerInstallCommand,\r
1178 sizeof (TpmSetOwnerInstallCommand),\r
1179 ReceiveBuffer,\r
1180 &ReceiveBufferSize\r
1181 );\r
1182 }\r
1183 if (Data == 0x09)\r
1184 {\r
1185 //\r
1186 // TPM_SetOwnerInstall=FALSE\r
1187 //\r
1188 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1189 TpmSetOwnerInstallCommand [10] = 0x00;\r
1190 Status = TpmMpDriver->Transmit (\r
1191 TpmMpDriver,\r
1192 TpmSetOwnerInstallCommand,\r
1193 sizeof (TpmSetOwnerInstallCommand),\r
1194 ReceiveBuffer,\r
1195 &ReceiveBufferSize\r
1196 );\r
1197 }\r
1198 if (Data == 0x0A)\r
1199 {\r
1200 //\r
1201 // TPM_PhysicalEnable\r
1202 //\r
1203 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1204 Status = TpmMpDriver->Transmit (\r
1205 TpmMpDriver,\r
1206 TpmPhysicalEnableCommand,\r
1207 sizeof (TpmPhysicalEnableCommand),\r
1208 ReceiveBuffer,\r
1209 &ReceiveBufferSize\r
1210 );\r
1211 //\r
1212 // TPM_PhysicalSetDeactivated=FALSE\r
1213 //\r
1214 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1215 TpmPhysicalSetDeactivatedCommand [10] = 0x00;\r
1216 Status = TpmMpDriver->Transmit (\r
1217 TpmMpDriver,\r
1218 TpmPhysicalSetDeactivatedCommand,\r
1219 sizeof (TpmPhysicalSetDeactivatedCommand),\r
1220 ReceiveBuffer,\r
1221 &ReceiveBufferSize\r
1222 );\r
1223 //\r
1224 // Do TPM_SetOwnerInstall=TRUE on next reboot\r
1225 //\r
1226\r
1227 WriteCmosBank1Byte (CpuIo, ACPI_TPM_REQUEST, 0xF0);\r
1228\r
1229 gRT->ResetSystem (\r
1230 EfiResetWarm,\r
1231 EFI_SUCCESS,\r
1232 0,\r
1233 NULL\r
1234 );\r
1235 }\r
1236 if (Data == 0x0B)\r
1237 {\r
1238 //\r
1239 // TPM_SetOwnerInstall=FALSE\r
1240 //\r
1241 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1242 TpmSetOwnerInstallCommand [10] = 0x00;\r
1243 Status = TpmMpDriver->Transmit (\r
1244 TpmMpDriver,\r
1245 TpmSetOwnerInstallCommand,\r
1246 sizeof (TpmSetOwnerInstallCommand),\r
1247 ReceiveBuffer,\r
1248 &ReceiveBufferSize\r
1249 );\r
1250 //\r
1251 // TPM_PhysicalSetDeactivated=TRUE\r
1252 //\r
1253 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1254 TpmPhysicalSetDeactivatedCommand [10] = 0x01;\r
1255 Status = TpmMpDriver->Transmit (\r
1256 TpmMpDriver,\r
1257 TpmPhysicalSetDeactivatedCommand,\r
1258 sizeof (TpmPhysicalSetDeactivatedCommand),\r
1259 ReceiveBuffer,\r
1260 &ReceiveBufferSize\r
1261 );\r
1262 //\r
1263 // TPM_PhysicalDisable\r
1264 //\r
1265 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1266 Status = TpmMpDriver->Transmit (\r
1267 TpmMpDriver,\r
1268 TpmPhysicalDisableCommand,\r
1269 sizeof (TpmPhysicalDisableCommand),\r
1270 ReceiveBuffer,\r
1271 &ReceiveBufferSize\r
1272 );\r
1273 gRT->ResetSystem (\r
1274 EfiResetWarm,\r
1275 EFI_SUCCESS,\r
1276 0,\r
1277 NULL\r
1278 );\r
1279 }\r
1280 if (Data == 0x0E)\r
1281 {\r
1282 //\r
1283 // TPM_ForceClear\r
1284 //\r
1285 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1286 Status = TpmMpDriver->Transmit (\r
1287 TpmMpDriver,\r
1288 TpmForceClearCommand,\r
1289 sizeof (TpmForceClearCommand),\r
1290 ReceiveBuffer,\r
1291 &ReceiveBufferSize\r
1292 );\r
1293 //\r
1294 // TPM_PhysicalEnable\r
1295 //\r
1296 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1297 Status = TpmMpDriver->Transmit (\r
1298 TpmMpDriver,\r
1299 TpmPhysicalEnableCommand,\r
1300 sizeof (TpmPhysicalEnableCommand),\r
1301 ReceiveBuffer,\r
1302 &ReceiveBufferSize\r
1303 );\r
1304 //\r
1305 // TPM_PhysicalSetDeactivated=FALSE\r
1306 //\r
1307 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1308 TpmPhysicalSetDeactivatedCommand [10] = 0x00;\r
1309 Status = TpmMpDriver->Transmit (\r
1310 TpmMpDriver,\r
1311 TpmPhysicalSetDeactivatedCommand,\r
1312 sizeof (TpmPhysicalSetDeactivatedCommand),\r
1313 ReceiveBuffer,\r
1314 &ReceiveBufferSize\r
1315 );\r
1316 gRT->ResetSystem (\r
1317 EfiResetWarm,\r
1318 EFI_SUCCESS,\r
1319 0,\r
1320 NULL\r
1321 );\r
1322 }\r
1323 if (Data == 0xF0)\r
1324 {\r
1325 //\r
1326 // Second part of ACPI TPM request 0x0A: OEM custom TPM_SetOwnerInstall=TRUE\r
1327 //\r
1328 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1329 TpmSetOwnerInstallCommand [10] = 0x01;\r
1330 Status = TpmMpDriver->Transmit (\r
1331 TpmMpDriver,\r
1332 TpmSetOwnerInstallCommand,\r
1333 sizeof (TpmSetOwnerInstallCommand),\r
1334 ReceiveBuffer,\r
1335 &ReceiveBufferSize\r
1336 );\r
1337 WriteCmosBank1Byte (CpuIo, ACPI_TPM_LAST_REQUEST, 0x0A);\r
1338 }\r
1339 //\r
1340 // Deassert Physical Presence\r
1341 //\r
1342 TpmPhysicalPresenceCommand [11] = 0x10;\r
1343 ReceiveBufferSize = sizeof(ReceiveBuffer);\r
1344 Status = TpmMpDriver->Transmit (\r
1345 TpmMpDriver,\r
1346 TpmPhysicalPresenceCommand,\r
1347 sizeof (TpmPhysicalPresenceCommand),\r
1348 ReceiveBuffer,\r
1349 &ReceiveBufferSize\r
1350 );\r
1351 }\r
1352 }\r
1353\r
1354 return;\r
1355}\r
1356\r
1357/**\r
1358\r
1359 Initializes manufacturing and config mode setting.\r
1360\r
1361**/\r
1362VOID\r
1363InitMfgAndConfigModeStateVar()\r
1364{\r
1365 EFI_PLATFORM_SETUP_ID *BootModeBuffer;\r
1366 VOID *HobList;\r
1367 UINT16 State;\r
1368\r
1369 //\r
1370 // Variable initialization\r
1371 //\r
1372 State = FALSE;\r
1373\r
1374 HobList = GetFirstGuidHob(&gEfiPlatformBootModeGuid);\r
1375 if (HobList != NULL) {\r
1376 BootModeBuffer = GET_GUID_HOB_DATA (HobList);\r
1377\r
1378 //\r
1379 // Check if in Manufacturing mode\r
1380 //\r
1381 if ( !CompareMem (\r
1382 &BootModeBuffer->SetupName,\r
1383 MANUFACTURE_SETUP_NAME,\r
1384 StrSize (MANUFACTURE_SETUP_NAME)\r
1385 ) ) {\r
1386 mMfgMode = TRUE;\r
1387 }\r
1388\r
1389 //\r
1390 // Check if in safe mode\r
1391 //\r
1392 if ( !CompareMem (\r
1393 &BootModeBuffer->SetupName,\r
1394 SAFE_SETUP_NAME,\r
1395 StrSize (SAFE_SETUP_NAME)\r
1396 ) ) {\r
1397 State = TRUE;\r
1398 }\r
1399 }\r
1400\r
1401}\r
1402\r
1403/**\r
1404\r
1405 Initializes manufacturing and config mode setting.\r
1406\r
1407**/\r
1408VOID\r
1409InitPlatformBootMode()\r
1410{\r
1411 EFI_PLATFORM_SETUP_ID *BootModeBuffer;\r
1412 VOID *HobList;\r
1413\r
1414 HobList = GetFirstGuidHob(&gEfiPlatformBootModeGuid);\r
1415 if (HobList != NULL) {\r
1416 BootModeBuffer = GET_GUID_HOB_DATA (HobList);\r
1417 mPlatformBootMode = BootModeBuffer->PlatformBootMode;\r
1418 }\r
1419}\r
1420\r
1421/**\r
1422\r
1423 Initializes ITK.\r
1424\r
1425**/\r
1426VOID\r
1427InitItk(\r
1428 )\r
1429{\r
1430 EFI_STATUS Status;\r
1431 UINT16 ItkModBiosState;\r
1432 UINT8 Value;\r
1433 UINTN DataSize;\r
1434 UINT32 Attributes;\r
1435\r
1436 //\r
1437 // Setup local variable according to ITK variable\r
1438 //\r
1439 //\r
1440 // Read ItkBiosModVar to determine if BIOS has been modified by ITK\r
1441 // If ItkBiosModVar = 0 or if variable hasn't been initialized then BIOS has not been modified by ITK modified\r
1442 // Set local variable VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME=0 if BIOS has not been modified by ITK\r
1443 //\r
1444 DataSize = sizeof (Value);\r
1445 Status = gRT->GetVariable (\r
1446 ITK_BIOS_MOD_VAR_NAME,\r
1447 &gItkDataVarGuid,\r
1448 &Attributes,\r
1449 &DataSize,\r
1450 &Value\r
1451 );\r
1452 if (Status == EFI_NOT_FOUND) {\r
1453 //\r
1454 // Variable not found, hasn't been initialized, intialize to 0\r
1455 //\r
1456 Value=0x00;\r
1457 //\r
1458 // Write variable to flash.\r
1459 //\r
1460 gRT->SetVariable (\r
1461 ITK_BIOS_MOD_VAR_NAME,\r
1462 &gItkDataVarGuid,\r
1463 EFI_VARIABLE_RUNTIME_ACCESS |\r
1464 EFI_VARIABLE_NON_VOLATILE |\r
1465 EFI_VARIABLE_BOOTSERVICE_ACCESS,\r
1466 sizeof (Value),\r
1467 &Value\r
1468 );\r
1469\r
1470}\r
1471 if ( (!EFI_ERROR (Status)) || (Status == EFI_NOT_FOUND) ) {\r
1472 if (Value == 0x00) {\r
1473 ItkModBiosState = 0x00;\r
1474 } else {\r
1475 ItkModBiosState = 0x01;\r
1476 }\r
1477 gRT->SetVariable (\r
1478 VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME,\r
1479 &gEfiNormalSetupGuid,\r
1480 EFI_VARIABLE_BOOTSERVICE_ACCESS,\r
1481 2,\r
1482 (void *)&ItkModBiosState\r
1483 );\r
1484 }\r
1485}\r
1486\r
1487#if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)\r
1488\r
1489/**\r
1490\r
1491 Initializes the BIOS FIRMWARE ID from the FIRMWARE_ID build variable.\r
1492\r
1493**/\r
1494STATIC\r
1495VOID\r
1496InitFirmwareId(\r
1497 )\r
1498{\r
1499 EFI_STATUS Status;\r
1500 CHAR16 FirmwareIdNameWithPassword[] = FIRMWARE_ID_NAME_WITH_PASSWORD;\r
1501\r
1502 //\r
1503 // First try writing the variable without a password in case we are\r
1504 // upgrading from a BIOS without password protection on the FirmwareId\r
1505 //\r
1506 Status = gRT->SetVariable(\r
1507 (CHAR16 *)&gFirmwareIdName,\r
1508 &gFirmwareIdGuid,\r
1509 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS |\r
1510 EFI_VARIABLE_RUNTIME_ACCESS,\r
1511 sizeof( FIRMWARE_ID ) - 1,\r
1512 FIRMWARE_ID\r
1513 );\r
1514\r
1515 if (Status == EFI_INVALID_PARAMETER) {\r
1516\r
1517 //\r
1518 // Since setting the firmware id without the password failed,\r
1519 // a password must be required.\r
1520 //\r
1521 Status = gRT->SetVariable(\r
1522 (CHAR16 *)&FirmwareIdNameWithPassword,\r
1523 &gFirmwareIdGuid,\r
1524 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS |\r
1525 EFI_VARIABLE_RUNTIME_ACCESS,\r
1526 sizeof( FIRMWARE_ID ) - 1,\r
1527 FIRMWARE_ID\r
1528 );\r
1529 }\r
1530}\r
1531#endif\r
1532\r
1533VOID\r
1534UpdateDVMTSetup(\r
1535 )\r
1536{\r
1537 //\r
1538 // Workaround to support IIA bug.\r
1539 // IIA request to change option value to 4, 5 and 7 relatively\r
1540 // instead of 1, 2, and 3 which follow Lakeport Specs.\r
1541 // Check option value, temporary hardcode GraphicsDriverMemorySize\r
1542 // Option value to fulfill IIA requirment. So that user no need to\r
1543 // load default and update setupvariable after update BIOS.\r
1544 // Option value hardcoded as: 1 to 4, 2 to 5, 3 to 7.\r
1545 // *This is for broadwater and above product only.\r
1546 //\r
1547\r
1548 SYSTEM_CONFIGURATION SystemConfiguration;\r
1549 UINTN VarSize;\r
1550 EFI_STATUS Status;\r
1551\r
1552 VarSize = sizeof(SYSTEM_CONFIGURATION);\r
1553 Status = gRT->GetVariable(\r
1554 NORMAL_SETUP_NAME,\r
1555 &gEfiNormalSetupGuid,\r
1556 NULL,\r
1557 &VarSize,\r
1558 &SystemConfiguration\r
1559 );\r
1560\r
1561 if((SystemConfiguration.GraphicsDriverMemorySize < 4) && !EFI_ERROR(Status) ) {\r
1562 switch (SystemConfiguration.GraphicsDriverMemorySize){\r
1563 case 1:\r
1564 SystemConfiguration.GraphicsDriverMemorySize = 4;\r
1565 break;\r
1566 case 2:\r
1567 SystemConfiguration.GraphicsDriverMemorySize = 5;\r
1568 break;\r
1569 case 3:\r
1570 SystemConfiguration.GraphicsDriverMemorySize = 7;\r
1571 break;\r
1572 default:\r
1573 break;\r
1574 }\r
1575\r
1576 Status = gRT->SetVariable (\r
1577 NORMAL_SETUP_NAME,\r
1578 &gEfiNormalSetupGuid,\r
1579 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,\r
1580 sizeof(SYSTEM_CONFIGURATION),\r
1581 &SystemConfiguration\r
1582 );\r
1583 }\r
1584}\r
1585\r
1586VOID\r
1587InitPlatformUsbPolicy (\r
1588 VOID\r
1589 )\r
1590\r
1591{\r
1592 EFI_HANDLE Handle;\r
1593 EFI_STATUS Status;\r
1594\r
1595 Handle = NULL;\r
1596\r
1597 mUsbPolicyData.Version = (UINT8)USB_POLICY_PROTOCOL_REVISION_2;\r
1598 mUsbPolicyData.UsbMassStorageEmulationType = mSystemConfiguration.UsbBIOSINT13DeviceEmulation;\r
1599 if(mUsbPolicyData.UsbMassStorageEmulationType == 3) {\r
1600 mUsbPolicyData.UsbEmulationSize = mSystemConfiguration.UsbBIOSINT13DeviceEmulationSize;\r
1601 } else {\r
1602 mUsbPolicyData.UsbEmulationSize = 0;\r
1603 }\r
1604 mUsbPolicyData.UsbZipEmulationType = mSystemConfiguration.UsbZipEmulation;\r
1605 mUsbPolicyData.UsbOperationMode = HIGH_SPEED;\r
1606\r
1607 //\r
1608 // Some chipset need Period smi, 0 = LEGACY_PERIOD_UN_SUPP\r
1609 //\r
1610 mUsbPolicyData.USBPeriodSupport = LEGACY_PERIOD_UN_SUPP;\r
1611\r
1612 //\r
1613 // Some platform need legacyfree, 0 = LEGACY_FREE_UN_SUPP\r
1614 //\r
1615 mUsbPolicyData.LegacyFreeSupport = LEGACY_FREE_UN_SUPP;\r
1616\r
1617 //\r
1618 // Set Code base , TIANO_CODE_BASE =0x01, ICBD =0x00\r
1619 //\r
1620 mUsbPolicyData.CodeBase = (UINT8)ICBD_CODE_BASE;\r
1621\r
1622 //\r
1623 // Some chispet 's LpcAcpibase are diffrent,set by platform or chipset,\r
1624 // default is Ich acpibase =0x040. acpitimerreg=0x08.\r
1625 mUsbPolicyData.LpcAcpiBase = 0x40;\r
1626 mUsbPolicyData.AcpiTimerReg = 0x08;\r
1627\r
1628 //\r
1629 // Set for reduce usb post time\r
1630 //\r
1631 mUsbPolicyData.UsbTimeTue = 0x00;\r
1632 mUsbPolicyData.InternelHubExist = 0x00; //TigerPoint doesn't have RMH\r
1633 mUsbPolicyData.EnumWaitPortStableStall = 100;\r
1634\r
1635\r
1636 Status = gBS->InstallProtocolInterface (\r
1637 &Handle,\r
1638 &gUsbPolicyGuid,\r
1639 EFI_NATIVE_INTERFACE,\r
1640 &mUsbPolicyData\r
1641 );\r
1642 ASSERT_EFI_ERROR(Status);\r
1643\r
1644}\r
1645\r
1646UINT8\r
1647ReadCmosBank1Byte (\r
1648 IN EFI_CPU_IO_PROTOCOL *CpuIo,\r
1649 IN UINT8 Index\r
1650 )\r
1651{\r
1652 UINT8 Data;\r
1653\r
1654 CpuIo->Io.Write (CpuIo, EfiCpuIoWidthUint8, 0x72, 1, &Index);\r
1655 CpuIo->Io.Read (CpuIo, EfiCpuIoWidthUint8, 0x73, 1, &Data);\r
1656 return Data;\r
1657}\r
1658\r
1659VOID\r
1660WriteCmosBank1Byte (\r
1661 IN EFI_CPU_IO_PROTOCOL *CpuIo,\r
1662 IN UINT8 Index,\r
1663 IN UINT8 Data\r
1664 )\r
1665{\r
1666 CpuIo->Io.Write (\r
1667 CpuIo,\r
1668 EfiCpuIoWidthUint8,\r
1669 0x72,\r
1670 1,\r
1671 &Index\r
1672 );\r
1673 CpuIo->Io.Write (\r
1674 CpuIo,\r
1675 EfiCpuIoWidthUint8,\r
1676 0x73,\r
1677 1,\r
1678 &Data\r
1679 );\r
1680}\r
1681\r
EFI Development Kit II mirror for PVE