]> git.proxmox.com Git - mirror_edk2.git/blame_incremental - ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c
projects / mirror_edk2.git / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
ArmPkg/ArmMmuLib ARM: assume page tables are in writeback cacheable memory
[mirror_edk2.git] / ArmPkg / Library / ArmMmuLib / Arm / ArmMmuLibCore.c
... / ...
CommitLineData
1/** @file\r
2* File managing the MMU for ARMv7 architecture\r
3*\r
4* Copyright (c) 2011-2016, ARM Limited. All rights reserved.\r
5*\r
6* This program and the accompanying materials\r
7* are licensed and made available under the terms and conditions of the BSD License\r
8* which accompanies this distribution. The full text of the license may be found at\r
9* http://opensource.org/licenses/bsd-license.php\r
10*\r
11* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13*\r
14**/\r
15\r
16#include <Uefi.h>\r
17#include <Chipset/ArmV7.h>\r
18#include <Library/BaseMemoryLib.h>\r
19#include <Library/CacheMaintenanceLib.h>\r
20#include <Library/MemoryAllocationLib.h>\r
21#include <Library/ArmLib.h>\r
22#include <Library/BaseLib.h>\r
23#include <Library/DebugLib.h>\r
24#include <Library/PcdLib.h>\r
25\r
26#define ID_MMFR0_SHARELVL_SHIFT 12\r
27#define ID_MMFR0_SHARELVL_MASK 0xf\r
28#define ID_MMFR0_SHARELVL_ONE 0\r
29#define ID_MMFR0_SHARELVL_TWO 1\r
30\r
31#define ID_MMFR0_INNERSHR_SHIFT 28\r
32#define ID_MMFR0_INNERSHR_MASK 0xf\r
33#define ID_MMFR0_OUTERSHR_SHIFT 8\r
34#define ID_MMFR0_OUTERSHR_MASK 0xf\r
35\r
36#define ID_MMFR0_SHR_IMP_UNCACHED 0\r
37#define ID_MMFR0_SHR_IMP_HW_COHERENT 1\r
38#define ID_MMFR0_SHR_IGNORED 0xf\r
39\r
40#define __EFI_MEMORY_RWX 0 // no restrictions\r
41\r
42#define CACHE_ATTRIBUTE_MASK (EFI_MEMORY_UC | \\r
43 EFI_MEMORY_WC | \\r
44 EFI_MEMORY_WT | \\r
45 EFI_MEMORY_WB | \\r
46 EFI_MEMORY_UCE | \\r
47 EFI_MEMORY_WP)\r
48\r
49UINTN\r
50EFIAPI\r
51ArmReadIdMmfr0 (\r
52 VOID\r
53 );\r
54\r
55BOOLEAN\r
56EFIAPI\r
57ArmHasMpExtensions (\r
58 VOID\r
59 );\r
60\r
61UINT32\r
62ConvertSectionAttributesToPageAttributes (\r
63 IN UINT32 SectionAttributes,\r
64 IN BOOLEAN IsLargePage\r
65 )\r
66{\r
67 UINT32 PageAttributes;\r
68\r
69 PageAttributes = 0;\r
70 PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY (SectionAttributes, IsLargePage);\r
71 PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_AP (SectionAttributes);\r
72 PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_XN (SectionAttributes, IsLargePage);\r
73 PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_NG (SectionAttributes);\r
74 PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_S (SectionAttributes);\r
75\r
76 return PageAttributes;\r
77}\r
78\r
79STATIC\r
80BOOLEAN\r
81PreferNonshareableMemory (\r
82 VOID\r
83 )\r
84{\r
85 UINTN Mmfr;\r
86 UINTN Val;\r
87\r
88 if (FeaturePcdGet (PcdNormalMemoryNonshareableOverride)) {\r
89 return TRUE;\r
90 }\r
91\r
92 //\r
93 // Check whether the innermost level of shareability (the level we will use\r
94 // by default to map normal memory) is implemented with hardware coherency\r
95 // support. Otherwise, revert to mapping as non-shareable.\r
96 //\r
97 Mmfr = ArmReadIdMmfr0 ();\r
98 switch ((Mmfr >> ID_MMFR0_SHARELVL_SHIFT) & ID_MMFR0_SHARELVL_MASK) {\r
99 case ID_MMFR0_SHARELVL_ONE:\r
100 // one level of shareability\r
101 Val = (Mmfr >> ID_MMFR0_OUTERSHR_SHIFT) & ID_MMFR0_OUTERSHR_MASK;\r
102 break;\r
103 case ID_MMFR0_SHARELVL_TWO:\r
104 // two levels of shareability\r
105 Val = (Mmfr >> ID_MMFR0_INNERSHR_SHIFT) & ID_MMFR0_INNERSHR_MASK;\r
106 break;\r
107 default:\r
108 // unexpected value -> shareable is the safe option\r
109 ASSERT (FALSE);\r
110 return FALSE;\r
111 }\r
112 return Val != ID_MMFR0_SHR_IMP_HW_COHERENT;\r
113}\r
114\r
115STATIC\r
116VOID\r
117PopulateLevel2PageTable (\r
118 IN UINT32 *SectionEntry,\r
119 IN UINT32 PhysicalBase,\r
120 IN UINT32 RemainLength,\r
121 IN ARM_MEMORY_REGION_ATTRIBUTES Attributes\r
122 )\r
123{\r
124 UINT32* PageEntry;\r
125 UINT32 Pages;\r
126 UINT32 Index;\r
127 UINT32 PageAttributes;\r
128 UINT32 SectionDescriptor;\r
129 UINT32 TranslationTable;\r
130 UINT32 BaseSectionAddress;\r
131 UINT32 FirstPageOffset;\r
132\r
133 switch (Attributes) {\r
134 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:\r
135 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:\r
136 PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_BACK;\r
137 break;\r
138 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:\r
139 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:\r
140 PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_THROUGH;\r
141 break;\r
142 case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:\r
143 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:\r
144 PageAttributes = TT_DESCRIPTOR_PAGE_DEVICE;\r
145 break;\r
146 case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:\r
147 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:\r
148 PageAttributes = TT_DESCRIPTOR_PAGE_UNCACHED;\r
149 break;\r
150 default:\r
151 PageAttributes = TT_DESCRIPTOR_PAGE_UNCACHED;\r
152 break;\r
153 }\r
154\r
155 if (PreferNonshareableMemory ()) {\r
156 PageAttributes &= ~TT_DESCRIPTOR_PAGE_S_SHARED;\r
157 }\r
158\r
159 // Check if the Section Entry has already been populated. Otherwise attach a\r
160 // Level 2 Translation Table to it\r
161 if (*SectionEntry != 0) {\r
162 // The entry must be a page table. Otherwise it exists an overlapping in the memory map\r
163 if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(*SectionEntry)) {\r
164 TranslationTable = *SectionEntry & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK;\r
165 } else if ((*SectionEntry & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) {\r
166 // Case where a virtual memory map descriptor overlapped a section entry\r
167\r
168 // Allocate a Level2 Page Table for this Section\r
169 TranslationTable = (UINTN)AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_PAGE_SIZE + TRANSLATION_TABLE_PAGE_ALIGNMENT));\r
170 TranslationTable = ((UINTN)TranslationTable + TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK;\r
171\r
172 // Translate the Section Descriptor into Page Descriptor\r
173 SectionDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionAttributesToPageAttributes (*SectionEntry, FALSE);\r
174\r
175 BaseSectionAddress = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(*SectionEntry);\r
176\r
177 // Populate the new Level2 Page Table for the section\r
178 PageEntry = (UINT32*)TranslationTable;\r
179 for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) {\r
180 PageEntry[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseSectionAddress + (Index << 12)) | SectionDescriptor;\r
181 }\r
182\r
183 // Overwrite the section entry to point to the new Level2 Translation Table\r
184 *SectionEntry = (TranslationTable & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) |\r
185 (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(Attributes) ? (1 << 3) : 0) |\r
186 TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;\r
187 } else {\r
188 // We do not support the other section type (16MB Section)\r
189 ASSERT(0);\r
190 return;\r
191 }\r
192 } else {\r
193 TranslationTable = (UINTN)AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_PAGE_SIZE + TRANSLATION_TABLE_PAGE_ALIGNMENT));\r
194 TranslationTable = ((UINTN)TranslationTable + TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK;\r
195\r
196 ZeroMem ((VOID *)TranslationTable, TRANSLATION_TABLE_PAGE_SIZE);\r
197\r
198 *SectionEntry = (TranslationTable & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) |\r
199 (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(Attributes) ? (1 << 3) : 0) |\r
200 TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;\r
201 }\r
202\r
203 FirstPageOffset = (PhysicalBase & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;\r
204 PageEntry = (UINT32 *)TranslationTable + FirstPageOffset;\r
205 Pages = RemainLength / TT_DESCRIPTOR_PAGE_SIZE;\r
206\r
207 ASSERT (FirstPageOffset + Pages <= TRANSLATION_TABLE_PAGE_COUNT);\r
208\r
209 for (Index = 0; Index < Pages; Index++) {\r
210 *PageEntry++ = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(PhysicalBase) | PageAttributes;\r
211 PhysicalBase += TT_DESCRIPTOR_PAGE_SIZE;\r
212 }\r
213\r
214}\r
215\r
216STATIC\r
217VOID\r
218FillTranslationTable (\r
219 IN UINT32 *TranslationTable,\r
220 IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion\r
221 )\r
222{\r
223 UINT32 *SectionEntry;\r
224 UINT32 Attributes;\r
225 UINT32 PhysicalBase;\r
226 UINT64 RemainLength;\r
227 UINT32 PageMapLength;\r
228\r
229 ASSERT(MemoryRegion->Length > 0);\r
230\r
231 if (MemoryRegion->PhysicalBase >= SIZE_4GB) {\r
232 return;\r
233 }\r
234\r
235 PhysicalBase = MemoryRegion->PhysicalBase;\r
236 RemainLength = MIN(MemoryRegion->Length, SIZE_4GB - PhysicalBase);\r
237\r
238 switch (MemoryRegion->Attributes) {\r
239 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:\r
240 Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);\r
241 break;\r
242 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:\r
243 Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);\r
244 break;\r
245 case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:\r
246 Attributes = TT_DESCRIPTOR_SECTION_DEVICE(0);\r
247 break;\r
248 case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:\r
249 Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);\r
250 break;\r
251 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:\r
252 Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);\r
253 break;\r
254 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:\r
255 Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1);\r
256 break;\r
257 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:\r
258 Attributes = TT_DESCRIPTOR_SECTION_DEVICE(1);\r
259 break;\r
260 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:\r
261 Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1);\r
262 break;\r
263 default:\r
264 Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);\r
265 break;\r
266 }\r
267\r
268 if (PreferNonshareableMemory ()) {\r
269 Attributes &= ~TT_DESCRIPTOR_SECTION_S_SHARED;\r
270 }\r
271\r
272 // Get the first section entry for this mapping\r
273 SectionEntry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);\r
274\r
275 while (RemainLength != 0) {\r
276 if (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE == 0 &&\r
277 RemainLength >= TT_DESCRIPTOR_SECTION_SIZE) {\r
278 // Case: Physical address aligned on the Section Size (1MB) && the length\r
279 // is greater than the Section Size\r
280 *SectionEntry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;\r
281 PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;\r
282 RemainLength -= TT_DESCRIPTOR_SECTION_SIZE;\r
283 } else {\r
284 PageMapLength = MIN (RemainLength, TT_DESCRIPTOR_SECTION_SIZE) -\r
285 (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE);\r
286\r
287 // Case: Physical address aligned on the Section Size (1MB) && the length\r
288 // does not fill a section\r
289 // Case: Physical address NOT aligned on the Section Size (1MB)\r
290 PopulateLevel2PageTable (SectionEntry++, PhysicalBase, PageMapLength,\r
291 MemoryRegion->Attributes);\r
292\r
293 // If it is the last entry\r
294 if (RemainLength < TT_DESCRIPTOR_SECTION_SIZE) {\r
295 break;\r
296 }\r
297\r
298 PhysicalBase += PageMapLength;\r
299 RemainLength -= PageMapLength;\r
300 }\r
301 }\r
302}\r
303\r
304RETURN_STATUS\r
305EFIAPI\r
306ArmConfigureMmu (\r
307 IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,\r
308 OUT VOID **TranslationTableBase OPTIONAL,\r
309 OUT UINTN *TranslationTableSize OPTIONAL\r
310 )\r
311{\r
312 VOID* TranslationTable;\r
313 ARM_MEMORY_REGION_ATTRIBUTES TranslationTableAttribute;\r
314 UINT32 TTBRAttributes;\r
315\r
316 // Allocate pages for translation table.\r
317 TranslationTable = AllocatePages (EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_SECTION_SIZE + TRANSLATION_TABLE_SECTION_ALIGNMENT));\r
318 if (TranslationTable == NULL) {\r
319 return RETURN_OUT_OF_RESOURCES;\r
320 }\r
321 TranslationTable = (VOID*)(((UINTN)TranslationTable + TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK);\r
322\r
323 if (TranslationTableBase != NULL) {\r
324 *TranslationTableBase = TranslationTable;\r
325 }\r
326\r
327 if (TranslationTableSize != NULL) {\r
328 *TranslationTableSize = TRANSLATION_TABLE_SECTION_SIZE;\r
329 }\r
330\r
331 ZeroMem (TranslationTable, TRANSLATION_TABLE_SECTION_SIZE);\r
332\r
333 // By default, mark the translation table as belonging to a uncached region\r
334 TranslationTableAttribute = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;\r
335 while (MemoryTable->Length != 0) {\r
336 // Find the memory attribute for the Translation Table\r
337 if (((UINTN)TranslationTable >= MemoryTable->PhysicalBase) && ((UINTN)TranslationTable <= MemoryTable->PhysicalBase - 1 + MemoryTable->Length)) {\r
338 TranslationTableAttribute = MemoryTable->Attributes;\r
339 }\r
340\r
341 FillTranslationTable (TranslationTable, MemoryTable);\r
342 MemoryTable++;\r
343 }\r
344\r
345 // Translate the Memory Attributes into Translation Table Register Attributes\r
346 if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||\r
347 (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) {\r
348 TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_BACK_ALLOC : TTBR_WRITE_BACK_ALLOC;\r
349 } else {\r
350 // Page tables must reside in memory mapped as write-back cacheable\r
351 ASSERT (0);\r
352 return RETURN_UNSUPPORTED;\r
353 }\r
354\r
355 if (TTBRAttributes & TTBR_SHAREABLE) {\r
356 if (PreferNonshareableMemory ()) {\r
357 TTBRAttributes ^= TTBR_SHAREABLE;\r
358 } else {\r
359 //\r
360 // Unlike the S bit in the short descriptors, which implies inner shareable\r
361 // on an implementation that supports two levels, the meaning of the S bit\r
362 // in the TTBR depends on the NOS bit, which defaults to Outer Shareable.\r
363 // However, we should only set this bit after we have confirmed that the\r
364 // implementation supports multiple levels, or else the NOS bit is UNK/SBZP\r
365 //\r
366 if (((ArmReadIdMmfr0 () >> 12) & 0xf) != 0) {\r
367 TTBRAttributes |= TTBR_NOT_OUTER_SHAREABLE;\r
368 }\r
369 }\r
370 }\r
371\r
372 ArmCleanInvalidateDataCache ();\r
373 ArmInvalidateInstructionCache ();\r
374\r
375 ArmDisableDataCache ();\r
376 ArmDisableInstructionCache();\r
377 // TLBs are also invalidated when calling ArmDisableMmu()\r
378 ArmDisableMmu ();\r
379\r
380 // Make sure nothing sneaked into the cache\r
381 ArmCleanInvalidateDataCache ();\r
382 ArmInvalidateInstructionCache ();\r
383\r
384 ArmSetTTBR0 ((VOID *)(UINTN)(((UINTN)TranslationTable & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) | (TTBRAttributes & 0x7F)));\r
385\r
386 //\r
387 // The TTBCR register value is undefined at reset in the Non-Secure world.\r
388 // Writing 0 has the effect of:\r
389 // Clearing EAE: Use short descriptors, as mandated by specification.\r
390 // Clearing PD0 and PD1: Translation Table Walk Disable is off.\r
391 // Clearing N: Perform all translation table walks through TTBR0.\r
392 // (0 is the default reset value in systems not implementing\r
393 // the Security Extensions.)\r
394 //\r
395 ArmSetTTBCR (0);\r
396\r
397 ArmSetDomainAccessControl (DOMAIN_ACCESS_CONTROL_NONE(15) |\r
398 DOMAIN_ACCESS_CONTROL_NONE(14) |\r
399 DOMAIN_ACCESS_CONTROL_NONE(13) |\r
400 DOMAIN_ACCESS_CONTROL_NONE(12) |\r
401 DOMAIN_ACCESS_CONTROL_NONE(11) |\r
402 DOMAIN_ACCESS_CONTROL_NONE(10) |\r
403 DOMAIN_ACCESS_CONTROL_NONE( 9) |\r
404 DOMAIN_ACCESS_CONTROL_NONE( 8) |\r
405 DOMAIN_ACCESS_CONTROL_NONE( 7) |\r
406 DOMAIN_ACCESS_CONTROL_NONE( 6) |\r
407 DOMAIN_ACCESS_CONTROL_NONE( 5) |\r
408 DOMAIN_ACCESS_CONTROL_NONE( 4) |\r
409 DOMAIN_ACCESS_CONTROL_NONE( 3) |\r
410 DOMAIN_ACCESS_CONTROL_NONE( 2) |\r
411 DOMAIN_ACCESS_CONTROL_NONE( 1) |\r
412 DOMAIN_ACCESS_CONTROL_CLIENT(0));\r
413\r
414 ArmEnableInstructionCache();\r
415 ArmEnableDataCache();\r
416 ArmEnableMmu();\r
417 return RETURN_SUCCESS;\r
418}\r
419\r
420STATIC\r
421EFI_STATUS\r
422ConvertSectionToPages (\r
423 IN EFI_PHYSICAL_ADDRESS BaseAddress\r
424 )\r
425{\r
426 UINT32 FirstLevelIdx;\r
427 UINT32 SectionDescriptor;\r
428 UINT32 PageTableDescriptor;\r
429 UINT32 PageDescriptor;\r
430 UINT32 Index;\r
431\r
432 volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r
433 volatile ARM_PAGE_TABLE_ENTRY *PageTable;\r
434\r
435 DEBUG ((EFI_D_PAGE, "Converting section at 0x%x to pages\n", (UINTN)BaseAddress));\r
436\r
437 // Obtain page table base\r
438 FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();\r
439\r
440 // Calculate index into first level translation table for start of modification\r
441 FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;\r
442 ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);\r
443\r
444 // Get section attributes and convert to page attributes\r
445 SectionDescriptor = FirstLevelTable[FirstLevelIdx];\r
446 PageDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionAttributesToPageAttributes (SectionDescriptor, FALSE);\r
447\r
448 // Allocate a page table for the 4KB entries (we use up a full page even though we only need 1KB)\r
449 PageTable = (volatile ARM_PAGE_TABLE_ENTRY *)AllocatePages (1);\r
450 if (PageTable == NULL) {\r
451 return EFI_OUT_OF_RESOURCES;\r
452 }\r
453\r
454 // Write the page table entries out\r
455 for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) {\r
456 PageTable[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseAddress + (Index << 12)) | PageDescriptor;\r
457 }\r
458\r
459 // Formulate page table entry, Domain=0, NS=0\r
460 PageTableDescriptor = (((UINTN)PageTable) & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;\r
461\r
462 // Write the page table entry out, replacing section entry\r
463 FirstLevelTable[FirstLevelIdx] = PageTableDescriptor;\r
464\r
465 return EFI_SUCCESS;\r
466}\r
467\r
468STATIC\r
469EFI_STATUS\r
470UpdatePageEntries (\r
471 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
472 IN UINT64 Length,\r
473 IN UINT64 Attributes,\r
474 OUT BOOLEAN *FlushTlbs OPTIONAL\r
475 )\r
476{\r
477 EFI_STATUS Status;\r
478 UINT32 EntryValue;\r
479 UINT32 EntryMask;\r
480 UINT32 FirstLevelIdx;\r
481 UINT32 Offset;\r
482 UINT32 NumPageEntries;\r
483 UINT32 Descriptor;\r
484 UINT32 p;\r
485 UINT32 PageTableIndex;\r
486 UINT32 PageTableEntry;\r
487 UINT32 CurrentPageTableEntry;\r
488 VOID *Mva;\r
489\r
490 volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r
491 volatile ARM_PAGE_TABLE_ENTRY *PageTable;\r
492\r
493 Status = EFI_SUCCESS;\r
494\r
495 // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)\r
496 // EntryValue: values at bit positions specified by EntryMask\r
497 EntryMask = TT_DESCRIPTOR_PAGE_TYPE_MASK | TT_DESCRIPTOR_PAGE_AP_MASK;\r
498 if (Attributes & EFI_MEMORY_XP) {\r
499 EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN;\r
500 } else {\r
501 EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE;\r
502 }\r
503\r
504 // Although the PI spec is unclear on this, the GCD guarantees that only\r
505 // one Attribute bit is set at a time, so the order of the conditionals below\r
506 // is irrelevant. If no memory attribute is specified, we preserve whatever\r
507 // memory type is set in the page tables, and update the permission attributes\r
508 // only.\r
509 if (Attributes & EFI_MEMORY_UC) {\r
510 // modify cacheability attributes\r
511 EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;\r
512 // map to strongly ordered\r
513 EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0\r
514 } else if (Attributes & EFI_MEMORY_WC) {\r
515 // modify cacheability attributes\r
516 EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;\r
517 // map to normal non-cachable\r
518 EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0\r
519 } else if (Attributes & EFI_MEMORY_WT) {\r
520 // modify cacheability attributes\r
521 EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;\r
522 // write through with no-allocate\r
523 EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0\r
524 } else if (Attributes & EFI_MEMORY_WB) {\r
525 // modify cacheability attributes\r
526 EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;\r
527 // write back (with allocate)\r
528 EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1\r
529 } else if (Attributes & CACHE_ATTRIBUTE_MASK) {\r
530 // catch unsupported memory type attributes\r
531 ASSERT (FALSE);\r
532 return EFI_UNSUPPORTED;\r
533 }\r
534\r
535 if (Attributes & EFI_MEMORY_RO) {\r
536 EntryValue |= TT_DESCRIPTOR_PAGE_AP_RO_RO;\r
537 } else {\r
538 EntryValue |= TT_DESCRIPTOR_PAGE_AP_RW_RW;\r
539 }\r
540\r
541 // Obtain page table base\r
542 FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();\r
543\r
544 // Calculate number of 4KB page table entries to change\r
545 NumPageEntries = Length / TT_DESCRIPTOR_PAGE_SIZE;\r
546\r
547 // Iterate for the number of 4KB pages to change\r
548 Offset = 0;\r
549 for(p = 0; p < NumPageEntries; p++) {\r
550 // Calculate index into first level translation table for page table value\r
551\r
552 FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress + Offset) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;\r
553 ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);\r
554\r
555 // Read the descriptor from the first level page table\r
556 Descriptor = FirstLevelTable[FirstLevelIdx];\r
557\r
558 // Does this descriptor need to be converted from section entry to 4K pages?\r
559 if (!TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Descriptor)) {\r
560 Status = ConvertSectionToPages (FirstLevelIdx << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
561 if (EFI_ERROR(Status)) {\r
562 // Exit for loop\r
563 break;\r
564 }\r
565\r
566 // Re-read descriptor\r
567 Descriptor = FirstLevelTable[FirstLevelIdx];\r
568 if (FlushTlbs != NULL) {\r
569 *FlushTlbs = TRUE;\r
570 }\r
571 }\r
572\r
573 // Obtain page table base address\r
574 PageTable = (ARM_PAGE_TABLE_ENTRY *)TT_DESCRIPTOR_PAGE_BASE_ADDRESS(Descriptor);\r
575\r
576 // Calculate index into the page table\r
577 PageTableIndex = ((BaseAddress + Offset) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;\r
578 ASSERT (PageTableIndex < TRANSLATION_TABLE_PAGE_COUNT);\r
579\r
580 // Get the entry\r
581 CurrentPageTableEntry = PageTable[PageTableIndex];\r
582\r
583 // Mask off appropriate fields\r
584 PageTableEntry = CurrentPageTableEntry & ~EntryMask;\r
585\r
586 // Mask in new attributes and/or permissions\r
587 PageTableEntry |= EntryValue;\r
588\r
589 if (CurrentPageTableEntry != PageTableEntry) {\r
590 Mva = (VOID *)(UINTN)((((UINTN)FirstLevelIdx) << TT_DESCRIPTOR_SECTION_BASE_SHIFT) + (PageTableIndex << TT_DESCRIPTOR_PAGE_BASE_SHIFT));\r
591\r
592 // Only need to update if we are changing the entry\r
593 PageTable[PageTableIndex] = PageTableEntry;\r
594 ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], Mva);\r
595 }\r
596\r
597 Status = EFI_SUCCESS;\r
598 Offset += TT_DESCRIPTOR_PAGE_SIZE;\r
599\r
600 } // End first level translation table loop\r
601\r
602 return Status;\r
603}\r
604\r
605STATIC\r
606EFI_STATUS\r
607UpdateSectionEntries (\r
608 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
609 IN UINT64 Length,\r
610 IN UINT64 Attributes\r
611 )\r
612{\r
613 EFI_STATUS Status = EFI_SUCCESS;\r
614 UINT32 EntryMask;\r
615 UINT32 EntryValue;\r
616 UINT32 FirstLevelIdx;\r
617 UINT32 NumSections;\r
618 UINT32 i;\r
619 UINT32 CurrentDescriptor;\r
620 UINT32 Descriptor;\r
621 VOID *Mva;\r
622 volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r
623\r
624 // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)\r
625 // EntryValue: values at bit positions specified by EntryMask\r
626\r
627 // Make sure we handle a section range that is unmapped\r
628 EntryMask = TT_DESCRIPTOR_SECTION_TYPE_MASK | TT_DESCRIPTOR_SECTION_XN_MASK |\r
629 TT_DESCRIPTOR_SECTION_AP_MASK;\r
630 EntryValue = TT_DESCRIPTOR_SECTION_TYPE_SECTION;\r
631\r
632 // Although the PI spec is unclear on this, the GCD guarantees that only\r
633 // one Attribute bit is set at a time, so the order of the conditionals below\r
634 // is irrelevant. If no memory attribute is specified, we preserve whatever\r
635 // memory type is set in the page tables, and update the permission attributes\r
636 // only.\r
637 if (Attributes & EFI_MEMORY_UC) {\r
638 // modify cacheability attributes\r
639 EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;\r
640 // map to strongly ordered\r
641 EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0\r
642 } else if (Attributes & EFI_MEMORY_WC) {\r
643 // modify cacheability attributes\r
644 EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;\r
645 // map to normal non-cachable\r
646 EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0\r
647 } else if (Attributes & EFI_MEMORY_WT) {\r
648 // modify cacheability attributes\r
649 EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;\r
650 // write through with no-allocate\r
651 EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0\r
652 } else if (Attributes & EFI_MEMORY_WB) {\r
653 // modify cacheability attributes\r
654 EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;\r
655 // write back (with allocate)\r
656 EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1\r
657 } else if (Attributes & CACHE_ATTRIBUTE_MASK) {\r
658 // catch unsupported memory type attributes\r
659 ASSERT (FALSE);\r
660 return EFI_UNSUPPORTED;\r
661 }\r
662\r
663 if (Attributes & EFI_MEMORY_RO) {\r
664 EntryValue |= TT_DESCRIPTOR_SECTION_AP_RO_RO;\r
665 } else {\r
666 EntryValue |= TT_DESCRIPTOR_SECTION_AP_RW_RW;\r
667 }\r
668\r
669 if (Attributes & EFI_MEMORY_XP) {\r
670 EntryValue |= TT_DESCRIPTOR_SECTION_XN_MASK;\r
671 }\r
672\r
673 // obtain page table base\r
674 FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();\r
675\r
676 // calculate index into first level translation table for start of modification\r
677 FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;\r
678 ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);\r
679\r
680 // calculate number of 1MB first level entries this applies to\r
681 NumSections = Length / TT_DESCRIPTOR_SECTION_SIZE;\r
682\r
683 // iterate through each descriptor\r
684 for(i=0; i<NumSections; i++) {\r
685 CurrentDescriptor = FirstLevelTable[FirstLevelIdx + i];\r
686\r
687 // has this descriptor already been coverted to pages?\r
688 if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(CurrentDescriptor)) {\r
689 // forward this 1MB range to page table function instead\r
690 Status = UpdatePageEntries (\r
691 (FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT,\r
692 TT_DESCRIPTOR_SECTION_SIZE,\r
693 Attributes,\r
694 NULL);\r
695 } else {\r
696 // still a section entry\r
697\r
698 // mask off appropriate fields\r
699 Descriptor = CurrentDescriptor & ~EntryMask;\r
700\r
701 // mask in new attributes and/or permissions\r
702 Descriptor |= EntryValue;\r
703\r
704 if (CurrentDescriptor != Descriptor) {\r
705 Mva = (VOID *)(UINTN)(((UINTN)FirstLevelTable) << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
706\r
707 // Only need to update if we are changing the descriptor\r
708 FirstLevelTable[FirstLevelIdx + i] = Descriptor;\r
709 ArmUpdateTranslationTableEntry ((VOID *)&FirstLevelTable[FirstLevelIdx + i], Mva);\r
710 }\r
711\r
712 Status = EFI_SUCCESS;\r
713 }\r
714 }\r
715\r
716 return Status;\r
717}\r
718\r
719EFI_STATUS\r
720ArmSetMemoryAttributes (\r
721 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
722 IN UINT64 Length,\r
723 IN UINT64 Attributes\r
724 )\r
725{\r
726 EFI_STATUS Status;\r
727 UINT64 ChunkLength;\r
728 BOOLEAN FlushTlbs;\r
729\r
730 if (Length == 0) {\r
731 return EFI_SUCCESS;\r
732 }\r
733\r
734 FlushTlbs = FALSE;\r
735 while (Length > 0) {\r
736 if ((BaseAddress % TT_DESCRIPTOR_SECTION_SIZE == 0) &&\r
737 Length >= TT_DESCRIPTOR_SECTION_SIZE) {\r
738\r
739 ChunkLength = Length - Length % TT_DESCRIPTOR_SECTION_SIZE;\r
740\r
741 DEBUG ((DEBUG_PAGE,\r
742 "SetMemoryAttributes(): MMU section 0x%lx length 0x%lx to %lx\n",\r
743 BaseAddress, ChunkLength, Attributes));\r
744\r
745 Status = UpdateSectionEntries (BaseAddress, ChunkLength, Attributes);\r
746\r
747 FlushTlbs = TRUE;\r
748 } else {\r
749\r
750 //\r
751 // Process page by page until the next section boundary, but only if\r
752 // we have more than a section's worth of area to deal with after that.\r
753 //\r
754 ChunkLength = TT_DESCRIPTOR_SECTION_SIZE -\r
755 (BaseAddress % TT_DESCRIPTOR_SECTION_SIZE);\r
756 if (ChunkLength + TT_DESCRIPTOR_SECTION_SIZE > Length) {\r
757 ChunkLength = Length;\r
758 }\r
759\r
760 DEBUG ((DEBUG_PAGE,\r
761 "SetMemoryAttributes(): MMU page 0x%lx length 0x%lx to %lx\n",\r
762 BaseAddress, ChunkLength, Attributes));\r
763\r
764 Status = UpdatePageEntries (BaseAddress, ChunkLength, Attributes,\r
765 &FlushTlbs);\r
766 }\r
767\r
768 if (EFI_ERROR (Status)) {\r
769 break;\r
770 }\r
771\r
772 BaseAddress += ChunkLength;\r
773 Length -= ChunkLength;\r
774 }\r
775\r
776 if (FlushTlbs) {\r
777 ArmInvalidateTlb ();\r
778 }\r
779 return Status;\r
780}\r
781\r
782EFI_STATUS\r
783ArmSetMemoryRegionNoExec (\r
784 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
785 IN UINT64 Length\r
786 )\r
787{\r
788 return ArmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_XP);\r
789}\r
790\r
791EFI_STATUS\r
792ArmClearMemoryRegionNoExec (\r
793 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
794 IN UINT64 Length\r
795 )\r
796{\r
797 return ArmSetMemoryAttributes (BaseAddress, Length, __EFI_MEMORY_RWX);\r
798}\r
799\r
800EFI_STATUS\r
801ArmSetMemoryRegionReadOnly (\r
802 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
803 IN UINT64 Length\r
804 )\r
805{\r
806 return ArmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_RO);\r
807}\r
808\r
809EFI_STATUS\r
810ArmClearMemoryRegionReadOnly (\r
811 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
812 IN UINT64 Length\r
813 )\r
814{\r
815 return ArmSetMemoryAttributes (BaseAddress, Length, __EFI_MEMORY_RWX);\r
816}\r
817\r
818RETURN_STATUS\r
819EFIAPI\r
820ArmMmuBaseLibConstructor (\r
821 VOID\r
822 )\r
823{\r
824 return RETURN_SUCCESS;\r
825}\r
EFI Development Kit II mirror for PVE